Influence of n+-layer-gate gap on short-channel effects of GaAs self-aligned MESFET's (SAINT)

Short-channel effects of GaAs n⁺-gate self-aligned MESFET's are investigated for different n⁺-layer-gate gaps. The gate lengths range from 0.1 to 1.5 µm. The fabrication features are self-aligned implantation for n⁺-layer technology (SAINT) and an electron-beam direct writing. The n+-layer-gate gap is controlled by the undercut process in the bottom resist of a multilayer resist acting as n⁺ion implantation mask. It is shown that the short-channel effects such as an increase in subthreshold current and a negative shift of threshold voltage can be substantially alleviated by enlarging the n⁺-layer-gate gap from 0.15 to 0.3 µm.     

Application of the lamp-annealing method to the n+-layer of WSix-gate self-aligned GaAs MESFET's

The electrical properties of the Si-implanted n+-layer and the WSix/n-GaAs Schottky contacts were investigated after lamp annealing at temperatures up to 1050°C in order to apply the lamp-annealing method to the source-drain n+-layer of WSix-gate self-aligned GaAs MESFET's. Experimental results show that WSix/n-GaAs Schottky contacts are not subjected to interfacial degradation at temperatures required for fully activating the n+-implanted dopant. It is demonstrated that this method is effective in improving FET performance at short gate lengths of 1.0 µm. About a 50- percent improvement in K-value was achieved compared to conventional furnace-annealed FET's. It is implied that this improvement is due to reduced short-channel effects.     

Improved noise performance of GaAs MESFET's with selectively ion-implanted n+source regions

Superior microwave performance of 0.5-µm-gate GaAs MESFET's has been attained by a structure with selectively ion-implanted n⁺source regions. The source series resistance is reduced and the noise figure of 2.1 dB is observed at 12 GHz.     

A self-aligned retrograde twin-well structure with buried p+-layer

The retrograde twin wells and buried p⁺ layer are fabricated by a single lithographic step using high-energy ion implantation. The retrograde n-well is self-aligned to the retrograde p-well regions. This simple process allows a scalable CMOS structure for the very tight n⁺-to-p⁺ spacing. It provides latch-up immunity at the 1.5-μm n⁺-to-p⁺ spacing and good isolation characteristics without additional n- and p-channel stops     

A self-aligned retrograde twin-well structure with buried p+-layer

A self-aligned retrograde twin-well structure with a buried p⁺-layer surrounding the n-well is presented. The retrograde twin well and buried p⁺-layer are fabricated by a single lithographic step using high-energy ion implantation. The retrograde n-well is self-aligned to the retrograde p-well regions, and the channel stop processes are eliminated by using tight spatial distributions of retrograde n- and p-wells. This simple process is compatible with both local oxidation of silicon (LOCOS) and trench isolation processes and allows a scalable CMOS structure for very tight n⁺-to-p⁺ spacing. The present CMOS structure provides high latchup immunity at 1.5-μm n⁺-to-p⁺ spacing and good isolation characteristics without additional n- and p-channel stop dopings     

Determination of effective saturation velocity in n+self-aligned GaAs MESFET's with submicrometer gate lengths

The dependence of effective saturation velocity on gate length in n⁺self-aligned GaAs MESFET's with submicrometer gate lengths has been determined by comparing experimentalI-Vcharacteristics with that obtained from one-dimensional analysis and two-dimensional simulation. The experimentalI-Vcharacteristics have been precisely matched to the theoretical ones calculated by two-dimensional simulation with a quasi-static (effective) velocity-electric-field relationship and reasonable doping profiles. The effective saturation velocity determined by best fit is 2.3 × 10⁷cm/s, and is independent of the gate length in 0.3- to 1.0-µm range. Though this high value gives evidence of the velocity overshoot effects, the constant characteristic disagrees with the expectation of the simulations based on nonstationary electron transport. On the contrary, the saturation velocity determined by using one-dimensional analysis decreases with an increase in the gate length. This dependence is explained by taking into account the channel pinchoff mechanism for drain current saturation before velocity saturation.     

High-speed logic at 300K with self-aligned submicrometer-gate GaAs MESFET's

The fastest room-temperature logic gate operation yet reported has been achieved with an improved technology for self-aligned ion-implanted GaAs MESFET's. The procedure involves fabrication of 0.75/0.6-µm "T-gate" structures using electron-beam lithography, and employs arsenic-overpressure capless annealing of the self-aligned n⁺-implant. Minimum propagation delays of 15.4 ps/ stage were obtained for several of the ring oscillators, and none of the oscillators fabricated showed propagation delays longer than 17.0 ps. The fabrication technology and experimental results are described.     

Epitaxial n+ layer GaAs mesa-finger interdigital surfacephotodetectors

Several varieties of interdigital surface photodetectors have been fabricated on semi-insulating GaAs using mesa-etched n⁺ epitaxial layers as the carrier collection electrodes. This structure provides a significant responsivity improvement over conventional metal-semiconductor-metal (MSM) photodiodes by eliminating the surface reflection of the metal fingers and by providing increased photoconductive gain. High-speed testing using 100-ps doubled Nd:YAG pulses gave FWHM (full width at half maximum) responses of less than 500 ps for a 4-μm finger width and spacing and showed minimal degradation from standard MSM detectors of the same surface geometry. By introducing no additional process steps, the mesa-finger detectors are also monolithically compatible with mesa-etched GaAs MESFET technology     

Electron-beam lithography in n+self-aligned GaAs MESFET fabrication

An electron-beam direct-writing technology for the fabrication of short-channel n⁺sef-aligned (SAINT) GaAs MESFET's is discussed. A four-level multiresist which includes a thin Mo layer is developed to avoid charging in the semi-insulating GaAs substrate. The alleviation of short channel effects is experimentally demonstrated by reducing the n⁺layer depth. A ring oscillator with a 0.3-µm-long gate SAINT FET shows a minimum propagation delay time of 16.7 ps with an associated power dissipation of 7.3 mW, which is one of the fastest among room-temperature semiconductor devices.     

Spectral response of n+-n-p and n+-p photodiodes

Results of calculations for the quantum efficiency of three different types of n⁺-p, n⁺-n-p, and OCI-HLE diodes are reported. Exact numerical modeling of current density equations, modified to include bandgap reduction and Auger recombination is used to compute the quantum efficiency of these diodes. It is found that an optimized n⁺-p structure can result in over all spectral response comparable to the n⁺-n-p structure, although it is not as good as that of the OCI-HLE type of diodes. Further, these calculations show that one can achieve low dark current in these diodes, but at the expense of lower quantum efficiency particularly for wavelengths less than 0.4 µm.     

Formation of planar n+pockets in GaAs for mixer diode fabrication

A novel technique has been developed to produce n⁺"pockets" in semi-insulating GaAs bulk material. This technique has produced thick pockets of highly conducting epitaxial material on the substrate surface. The pockets were formed by the growth of a liquid-phase epitaxial (LPE) layer into holes which had been etched into the substrate. Surface uniformity was obtained by chemo-mechanically polishing the substrate surface under tightly controlled conditions. Polishing rates as low as 0.2 µm/min have been obtained. Photographs taken of the pocket cross-sectional area have revealed that growth occurred throughout the entire pocket region. Growth was even found to have occurred along the irregularly shape walls of the pockets. The continuous growth throughout the pockets coupled with the subsequent polishing of the substrate have produced exceptionally smooth and planar surfaces. Thicknesses as great as 10 µm have been obtained for the n⁺pockets using this technique. Mixer diodes have been fabricated onto these layers and tested. Preliminary dc measurements taken on these devices have yielded a zero-biased cutoff frequency (Fco) of 800 GHz with a series resistance (Rs) of 6 Ω and a zero-biased capacitance (C0) of 30 fF.     

Characteristics including electron velocity overshoot for0.1-μm-gate-length GaAs SAINT MESFET's

Short-channel effects, substrate leakage current, and average electron velocity are investigated for 0.1-μm-gate-length GaAs MESFETs fabricated using the SAINT (self-aligned implantation for n⁺-layer technology) process. The threshold-voltage shift was scaled by the aspect ratio of the channel thickness to the gate length ( a/L_g). The substrate leakage current in a sub-quarter-micrometer MESFET is completely suppressed by the buried p layers and shallow n⁺-layers. The average electron velocity for 0.1- to 0.2-μm-gate-length FETs is estimated to be 3×10⁶ cm/s from the analysis of intrinsic FET parameters. This high value indicates electron velocity overshoot. Moreover, a very high f_T of 93.1 GHz has been attained by the 0.1-μm SAINT MESFET     

Large transconductance n+-Ge gate AlGaAs/GaAs MISFET with thin gate insulator

The effects of insulator layer thickness on an n+-Ge gate MISFET were studied. The transconductance increases with decreasing AlGaAs layer thickness from 60 down to 10 nm. From the variation of the intrinsic transconductance, the effective insulator layer thickness was found to be enlarged by about 9 nm. This is due to the finite width of two-dimensional electron gas (2-DEG). A large transconductance of 430 mS/ mm was obtained at room temperature for the 0.8-µm gate-length FET with 10-nm-thick AlGaAs. This large transconductance demonstrates the inherent potential of the n+-Ge gate MISFET for LSI application.     

Reduction of the short-channel effects for GaAs MESFETs by doubleshallow n+-layers

In order to suppress the short-channel effects of subquarter-micrometer gate-length GaAs MESFETs, it is necessary to fabricate shallow n⁺ layers without any increase of parasitic resistance. To advance this line of research, a double shallow n⁺ -layer structure was investigated using a T-shaped resist mask and oblique ion implantation. Employing this shallow n⁺-layer structure, the threshold-voltage shift was suppressed and the subthreshold characteristics were improved for subquarter-micrometer gate-length FETs. A transconductance of 500 mS/mm for the 0.15-μm gate-length FET and a cutoff frequency of 33 GHz for the 0.35-μm gate-length FET were obtained     

Carrier distribution and low-field resistance in short n+-n--n+and n+-p--n+structures

In the present paper, we calculate the potential, field, and carrier distributions in short n⁺-n^--n⁺and n⁺-p^--n⁺devices and estimate the low-field resistance. The results of the calculations present a set of universal curves which may be used to find the minimum carrier density in the sample, the barrier height, the electric field at the boundary, etc. Our calculations show that electron injection becomes very important when the doping level is smaller than 1.5 × 10¹⁴(cm^-3). (T/300 K)/ L²(µm) for GaAs diodes, whereLis the sample length. The low-field resistance of the sample is limited by the thermionic emission of the sample and by the diffusion and drift in the sample. The thermionic emission dominates at low temperatures, in short samples, and the diffusion-drift dominates in longer samples at higher temperatures. The experimental values of low-field resistance for GaAs 0.4-µm n⁺-n^--n⁺devices at 77 and 300 K are in good agreement with the predicted values. The agreement is not so good for 0.25-µm devices and for n⁺-p^--n⁺devices. In the latter case, the disagreement may be due to uncertainty in the doping level because the low-field resistance of the n⁺-p^--n⁺structure is shown to be very sensitive to the doping level of the p-region.     

A high-speed frequency divider using n+-Ge Gate AlGaAs/GaAs MISFET's

A high-speed divide-by-four static frequency divider is fabricated using n+ -Ge gate AlGaAs/GaAs heterostructure MISFET's. The divider circuit consists of two master-slave T-type flip-flops (T-FF's) and an output buffer based on source-coupled FET logic (SCFL). A maximum toggle frequency of 11.3 GHz with a power dissipation of 219 mW per T-F/F is obtained at 300 K using 1.0-µm gate FET's.     

A self-aligned gate superlattice (Al,GA)As/n+-GaAs MODFET 5 × 5-bit parallel multiplier

A 5 × 5-bit parallel multiplier circuit has been demonstrated with self-aligned gate superlattice (Al,Ga)As/n+-GaAs modulation-doped FET's (MODFET's). Multiplication times (gate delays) and corresponding power dissipations of 1.80 ns (73 ps/gate) at 0.43 mW/gate and 1.08 ns (43 ps/gate) at 0.75 mW/gate were measured at room temperature and 77 K, respectively. These are the shortest gate propagation delays ever reported for parallel multiplier circuits at room temperature or 77 K using any semiconductor IC technology.     

0.3-μm advanced SAINT FET's having asymmetricn+-layers for ultra-high-frequency GaAs MMIC's

Improvements in the microwave performance and noise performance of buried p-layer self-aligned gate (BP-SAINT) FETs are discussed. Specifically, a self-aligned gate electrode and an asymmetric n⁺ -layer structure are investigated. The self-aligned gate electrode reduces parasitic gate capacitances by 0.13 to 0.23 pF/mm compared with a conventional BP-SAINT FET. The asymmetric n⁺-layer structure reduces short-channel effects (drain conductance, threshold voltage shift, etc.) and gate-drain capacitance. A 0.3-μm gate-length FET was realized without an increase of short-channel effects by using an asymmetric n⁺-layer structure (advanced SAINT). Improvement of microwave performance is confirmed in this FET structure     

Corner currents in p+-n-n+diodes with n+isolation diffusions

The magnitude of corner currents in rectangular diffused p⁺-n-n⁺diodes with deep n⁺isolation diffusions is discussed. Curves are given to illustrate the importance of this current in diodes and IIL structures.