Explicit Analytical Charge and Capacitance Models of Undoped Double-Gate MOSFETs

An analytical, explicit, and continuous-charge model for undoped symmetrical double-gate (DG) MOSFETs is presented. This charge model allows obtaining analytical expressions of all total capacitances. The model is based on a unified-charge-control model derived from Poisson's equation and is valid from below to well above threshold, showing a smooth transition between the different regimes. The drain current, charge, and capacitances are written as continuous explicit functions of the applied bias. We obtained very good agreement between the calculated capacitance characteristics and 2-D numerical device simulations, for different silicon film thicknesses.     

Analytic Charge Model for Surrounding-Gate MOSFETs

This paper presents an analytic charge model for surrounding-gate MOSFETs. Without the charge sheet approximation, the model is based on closed-form solution of Poisson's equation, current continuity equation, and Ward-Dutton linear charge partition. It continuously covers all the operation regions, i.e., linear, saturation, and subthreshold, with unique analytic expressions. The physics-based nature makes this model free of fitting parameters and hence predictive. In addition, it is inherently not source-referenced to avoid asymmetries. It is shown that the current-voltage characteristics generated by this model agree with the numerical simulation results     

Explicit Continuous Models for Double-Gate and Surrounding-Gate MOSFETs

Explicit continuous models for both double-gate (DG) and surrounding-gate (SG) MOSFETs are presented. These models evolve from previous DG and SG MOSFETs models, which need to solve implicit equations for intermediate parameters by numerical iteration or the table lookup method. By developing approximate explicit solutions for the intermediate parameters, we can express the drain current, terminal charge, transconductance, and transcapacitance as explicit functions of applied voltages as well as the structural parameters. High accuracy and efficiency, combined with inherited favorable features from the previous models, make these new models suitable for circuit simulation programs.     

短沟道三材料柱状围栅MOSFET的解析模型

在柱坐标系下利用电势的抛物线近似,求解二维泊松方程得到了短沟道三材料柱状围栅金属氧化物半导体场效应管的中心及表面电势。推导了器件阈值电压、亚阈值区电流和亚阈值摆幅的解析模型,分析了沟道直径、栅氧化层厚度和三栅长度比对阈值电压、亚阈值区电流和亚阈值摆幅的影响。利用Atlas对具有不同结构参数的器件进行了模拟研究和比较分析。结果表明,基于解析模型得到的计算值与模拟值一致,验证了所建模型的准确性,为设计和应用此类新型器件提供了理论基础。     

Two-Dimensional Analytical Threshold Voltage and Subthreshold Swing Models of Undoped Symmetric Double-Gate MOSFETs

We have developed analytical physically based models for the threshold voltage [including the drain-induced barrier lowering (DIBL) effect] and the subthreshold swing of undoped symmetrical double-gate (DG) MOSFETs. The models are derived from an analytical solution of the 2-D Poisson equation in which the electron concentration was included. The models for DIBL, subthreshold swing, and threshold voltage roll-off have been verified by comparison with 2-D numerical simulations for different values of channel length, channel thickness, and drain-source voltage; very good agreement with the numerical simulations has been observed     

A Review of Core Compact Models for Undoped Double-Gate SOI MOSFETs

In this paper, we review the compact-modeling framework for undoped double-gate (DG) silicon-on-insulator (SOI) MOSFETs. The use of multiple gates has emerged as a new technology to possibly replace the conventional planar MOSFET when its feature size is scaled to the sub-50-nm regime. MOSFET technology has been the choice for mainstream digital circuits for very large scale integration as well as for other high-frequency applications in the low-gigahertz range. But the continuing scaling of MOSFET presents many challenges, and multiple-gate, particularly DG, SOI devices seem to be attractive alternatives as they can effectively reduce the short-channel effects and yield higher current drive. Core compact models, including the analysis for surface potential and drain-current, for both the symmetric and asymmetric DG SOI MOSFETs, are discussed and compared. Numerical simulations are also included in order to assess the validity of the models reviewed     

短沟道MOSFET本征电容模型的研究

<正> 一、引言 随着MOS集成电路向短沟道、高速化发展,MOS晶体管电容对电路性能的影响更为突出。对电路性能影响较大的栅—漏,栅—源本征电容C_(GD),C_(GS)与长沟器件的主要不同是:(1)饱和区C_(GD)≠0,随着沟道缩短,C_(GD)占总本征栅电容的比例增大。(2)C_(GD)由饱和区到线性区呈平缓过渡状。(3)饱和区C_(GS)减小,并由次开启到饱和区的上升趋势变缓。分析表明,栅电容的短沟效应与沟长调制和速度饱和迁移率有关。     

Analytical Charge Voltage Model in MOS Inversion Layer Based on Space Charge Capacitance

The concept of Space Charge Capacitance (SCC) is proposed and used to make a novel analytical charge model of quantized inversion layer in MOS structures. Based on SCC,continuous expressions of surface potential and inversion layer carrier density are derived.Quantum mechanical effects on both inversion layer carrier density and surface potential are extensively included. The accuracy of the model is verified by the numerical solution to Schrodinger and Poisson equation and the model is demonstrated,too.     

Analytical Charge Voltage Model in MOS Inversion Layer Based on Space Charge Capacitance

The2 -Dimensional nature of the inversion layer carrier in MOS structure is well-known[1 ,2 ] and the Quantum Mechanical Effects(QMEs) on MOS structure' s behaviorhave been extensively studied by numerical survey by self-consistent so...     

考虑二维量子力学效应的MOSFET解析电荷模型

在亚 5 0 nm的 MOSFET中 ,沿沟道方向上的量子力学效应对器件特性有很大的影响。基于 WKB理论 ,考虑MOSFET中该效应对垂直沟道方向上能级的影响 ,引入了其对于阈电压的修正。在此基础上 ,对沟道方向的子带作了抛物线近似 ,从而建立了一个考虑二维量子力学的电荷解析模型。根据该模型 ,得到二维量子力学修正和沟道长度以及其他工艺参数的关系。与数值模拟结果的比较表明 ,该解析模型的精度令人满意 ,并且得出以下结论 :二维量子力学效应使阈电压下降 ,并且在亚 5 0 nm的 MOSFET中 ,这个修正不可忽略。     

短沟道无结柱状围栅MOSFET的解析模型

通过在柱坐标系下求解二维泊松方程,建立了短沟道无结柱状围栅金属氧化物半导体场效应管的电势模型,并推导了阈值电压、亚阈值区电流和亚阈值摆幅的解析模型。在此基础上,分析了沟道长度、沟道直径和栅氧化层厚度等参数对阈值电压、亚阈值区电流和亚阈值摆幅的影响。最后,利用Atlas软件对器件进行了模拟研究。结果表明,根据解析模型得到的计算值与模拟值一致,验证了模型的准确性。这些模型可为设计和应用新型的短沟道无结柱状围栅金属氧化物半导体场效应管提供理论基础。     

对称三材料双栅应变硅MOSFET亚阈值电流与亚阈值斜率解析模型

基于泊松方程和边界条件,推导了对称三材料双栅应变硅金属氧化物半导体场效应晶体管（MOSFET：metal oxide semiconductor field effect transistor）的表面势解析解.利用扩散-漂移理论,在亚阈值区电流密度方程的基础上,提出了亚阈值电流与亚阈值斜率二维解析模型.分析了沟道长度、功函数差、弛豫SiGe层的Ge组份、栅介质层的介电常数、应变硅沟道层厚度、栅介质高k层厚度和沟道掺杂浓度等参数对亚阈值性能的影响,并对亚阈值性能改进进行了分析研究.研究结果为优化器件参数提供了有意义的指导.模型解析结果与DESSIS仿真结果吻合较好.     

Capacitance and doping profiles of ion-implanted,buried-channel MOSFETs

Detailed capacitance measurements are presented of large-area, ion-implanted, buried-channel MOSFETs. The gate capacitance was measured as a function of gate-substrate voltage with drain (source)-substrate voltage as parameter. The MOSFETs were prepared on 10 Ω-cm, n-type, 〈111〉 Si. Boron ions with doses of 4 × 10¹¹ and 8 × 10¹¹/cm² were implanted through the gate oxide to a depth of 0.30–0.35 μ m in the Si. The devices were subjected to heat treatments of 900–1100°C.Calculated capacitances based on a one-dimensional, partial-ionization model are in good agreement with experiment. The model is used to assess the validity of C–V profiling technique based on the abrupt space-charge approximation. It is concluded that the impurity distribution can be measured quite accurately near the peak of the profile, for ion-implantation and heat-treatment conditions examined in this paper. However, the “tails” of the distribution cannot be measured with this technique. The limitations of the C–V profiling method are discussed quantitatively for a stepped profile.     

Analytical model and characterization of abnormally structured MOSFETs

Electrical characteristics of abnormally structured n-MOSFETs having uncontacted active regions are experimentally investigated using test devices with various gate widths. Linear resistance and saturation drain current of the devices are estimated by a simple schematic model, which consists of parallel-connected conventional devices having parasitic resistors. A comparison of experimental results of conventional and abnormal devices gives the parasitic resistance caused by abnormal active structure. The increment rate of the parasitic resistance depending on gate width shows two categories, which are logarithmic increment at narrow device and exponential increment at wider device. The performance degradation in the wider device is also explained by the reduction of effective channel area. The suggested model provides a physical analysis of the abnormal transistor and shows good agreement with the measured drain current in linear and saturation regions for both forward- and reverse-modes.     

Neural-Network-Based Charge Density Quantum Correction of Nanoscale MOSFETs

为了处理纳米MOSFET载流子分布的量子效应,提出了基于Levenberg-Marquardt BP神经网络的量子更正模型,通过载流子的经典密度计算其量子密度,并对拥有不同隐层数和隐层神经元数的神经网络的训练速度和精度进行了研究.结果表明:含有2个隐层的神经网络具有高的训练速度和精度,但隐层神经元数对速度和精度的影响并不明显;对于单栅和双栅纳米MOSFET,其载流子量子密度可以通过神经网络进行快速计算,其结果与Schrodinger-Poisson方程的吻合程度很高.     

基于神经网络的纳米MOSFET载流子密度量子更正

为了处理纳米MOSFET载流子分布的量子效应,提出了基于Levenberg-Marquardt BP神经网络的量子更正模型,通过载流子的经典密度计算其量子密度,并对拥有不同隐层数和隐层神经元数的神经网络的训练速度和精度进行了研究.结果表明:含有2个隐层的神经网络具有高的训练速度和精度,但隐层神经元数对速度和精度的影响并不明显;对于单栅和双栅纳米MOSFET,其载流子量子密度可以通过神经网络进行快速计算,其结果与Schrodinger-Poisson方程的吻合程度很高.     

双栅掺杂隔离肖特基MOSFET的解析模型

通过考虑肖特基势垒降低效应求解三段连续的二维泊松方程,建立了双栅掺杂隔离肖特基MOSFET亚阈值区全沟道连续的电势模型。在该电势模型的基础上,推导了阈值电压模型和漏致势垒降低效应的表达式;研究了掺杂隔离区域不同掺杂浓度下的沟道电势分布,分析了沟道长度和厚度对短沟道效应的影响。结果表明,掺杂隔离区域能改善肖特基MOSFET的电学特性;对于短沟道双栅掺杂隔离肖特基MOSFET,适当减小沟道宽度能有效抑制短沟道效应。     

Analytical modeling of MOSFETs channel noise and noise parameters

Simple analytical expressions for MOSFETs noise parameters are developed and experimentally verified. The expressions are based on analytical modeling of MOSFETs channel noise, are explicit functions of MOSFETs geometry and biasing conditions, and hence are useful for circuit design purposes. Good agreement between calculated and measured data is demonstrated. Moreover, it is shown that including induced gate noise in the modeling of MOSFETs noise parameters causes /spl sim/5% improvement in the accuracy of the simple expressions presented here, but at the expense of complicating the expressions.