On the two‐port network analysis of common amplifier topologies

Using two‐port network transmission parameters, we derive exact expressions for the voltage/current gains and the input/output impedances of common amplifier topologies. The derived expressions are valid both for BJT and MOS‐based amplifiers and are independent of any particular small signal transistor model. Copyright © 2009 John Wiley & Sons, Ltd.     

Minimal two‐transistor multifunction filter design

This paper presents a comprehensive method and analysis on the design of two‐transistor multi‐output filters where three possible functions are simultaneously available. Although two transistors are employed at its core, proper biasing does not require additional passive components. A total of thirteen valid second‐order filters are reported, and several of them are experimentally tested using discrete transistors as well as simulated using Spectre in a BiCMOS process. A fully differential realization of a MOS‐C band‐pass filter, based on one of the structures found, is designed and then used to realize a fourth‐order Chebyshev band‐pass filter. Copyright © 2017 John Wiley & Sons, Ltd.     

Realization of a transfer function as a passive two‐port RC ladder network with a specified gain

This paper is concerned with the realization problem for a class of high‐pass as well as low‐pass transfer functions as a two‐port RC ladder network with a specified gain, which requires that the actual gain of the realization configuration is equal to the gain of the given transfer function. From a cascade realization approach, it is shown that any transfer function belonging to the class under investigation can be realized as a two‐port RC ladder network with any specified gain in a continuous interval. Finally, a numerical example is presented to illustrate the result. Copyright © 2017 John Wiley & Sons, Ltd.     

Design of a robust PWM power amplifier using approximate two‐degree‐of‐freedom integral‐type control

A method is proposed for designing a robust controller for PWM power amplifiers, which are widely used as amplifiers and power supplies. The main technical requirements imposed on PWM power amplifiers are linearity in a wide frequency range and a well‐damped fast dynamic response in the presence of extensive load and DC power supply variations. Therefore, in order to satisfy the design specifications, namely, linearity in a wide frequency range and no overshoots during transients, an approximate two‐degree‐of‐freedom integral control structure is proposed and a design procedure for the robust controller is discussed. It is shown by some simulations and experiments that the designed controller shows especially good dynamic performance and effective disturbance rejection in the presence of external disturbances, that is, load and power‐supply variations. © 2003 Wiley Periodicals, Inc. Electr Eng Jpn, 144(1): 68–77, 2003; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.10102     

Optimal sizing and design of CMOS analogue amplifier circuits using craziness‐based particle swarm optimization

This paper presents the optimal designs of two analogue complementary metal–oxide–semiconductor (CMOS) amplifier circuits, namely differential amplifier with current mirror load and two‐stage operational amplifier. A modified Particle Swarm Optimization (PSO), called Craziness‐based Particle Swarm Optimization (CRPSO) technique is applied to minimize the total MOS area of the designed circuits. CRPSO is a highly modified version of conventional PSO, which adopts a number of random variables and has a better and faster exploration and exploitation capability in the multidimensional search space. Integration of craziness factor in the fundamental velocity term of PSO not only brings diversity in particles but also pledges convergence close to global best solution. The proposed CRPSO‐based circuit optimization technique is reassured to be free from the intrinsic disadvantages of premature convergence and stagnation, unlike Differential Evolution (DE), Harmony Search (HS), Artificial Bee Colony (ABC) and Particle Swarm Optimization (PSO). The simulation results achieved for the two analogue CMOS amplifier circuits establish the efficacy of the proposed CRPSO‐based approach over those of DE, HS, ABC and PSO in terms of convergence haste, design conditions and design goals. The optimally designed analogue CMOS amplifier circuits occupy the least MOS area and show the best performance parameters like gain and power dissipation, in compared with the other reported literature. Copyright © 2016 John Wiley & Sons, Ltd.     

A new false‐root identification method based on two‐terminal fault location algorithm for double‐circuit transmission lines

A fault location algorithm without synchronization for double‐circuit transmission lines does not require sampling synchronization, reduces the cost, and has a higher engineering value, but the algorithm still needs to be improved in the false‐root identification. This paper conducts further studies on this issue. First, the false‐root problem of the fault location algorithm without synchronization is analyzed, and then a new false‐root identification method is proposed, which is based on the difference of the existence of the false root in the calculation of the voltage amplitude along the line with different electrical moduli. It can solve the problem of the traditional method, which cannot distinguish between voltage amplitudes when they are close. Second, considering the shortcoming of the existing phase‐mode transformation matrix, a new phase‐mode transformation matrix applied to double‐circuit lines is deduced, which is based on the six‐sequence component method; it can be combined with the new false‐root identification method, thereby realizing false‐root identification under various types of faults. Finally, fault location is realized by using the moduli in the mold domain. The principle does not need to synchronize data in two terminals and is not affected by the fault types, fault resistances, and other factors. As is shown in a large number of Alternative Transients Program version of Electro‐Magnetic Transients Program (ATP‐EMTP) simulation results, the fault location has a higher accuracy © 2017 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Synthesis of n‐port resistive networks containing 2n terminals

This paper is concerned with the realizability problem of n‐port resistive networks that contain 2n terminals. A necessary and sufficient condition for any real symmetric matrix to be realizable as the admittance of an n‐port resistive network containing 2n terminals is obtained. This condition is based on the existence of a parameter matrix. Furthermore, the values of the elements are expressed in terms of the entries of the admittance matrix and the parameter matrix. Finally, a numerical example is used to illustrate the results. Copyright © 2013 John Wiley & Sons, Ltd.     

Calculating output impedance in linear networks without source nulling or load disconnect: the instantaneous output impedance

This paper derives exact expressions for the output impedance of a voltage‐excited (current‐excited) linear network without having to nullify (kill) the exciting source or disconnect the load. The derived expressions show that the instantaneous output impedance is both source and load dependent, but when the source is nullified, the output impedance becomes independent of the load, as expected. For some special networks, the output impedance is also independent of the load. The expressions are verified for a number of known circuit setups and experimentally on a gyrator‐based linear network, which has an output impedance that can switch between positive and negative values. Copyright © 2015 John Wiley & Sons, Ltd.     

Design of a 75‐nW, 0.5‐V subthreshold complementary metal–oxide–semiconductor operational amplifier

This work focuses on the subthreshold design of ultra low‐voltage low‐power operational amplifiers. A well‐defined procedure for the systematic design of subthreshold operational amplifiers (op‐amps) is introduced. The design of a 0.5‐V two‐stage Miller‐compensated amplifier fabricated with a 0.18‐µm complementary metal–oxide–semiconductor process is presented. The op‐amp operates with all transistors in subthreshold region and achieves a DC gain of 70 dB and a gain–bandwidth product of 18 kHz, dissipating just 75 nW. The active area of the chip is ≈0.057 mm². Experimental results demonstrate that well‐designed subthreshold op‐amps are a very attractive solution to implement sub‐1‐V energy‐efficient applications for modern portable electronic systems. A comparative analysis with low‐voltage, low‐power op‐amp designs available in the literature highlights that subthreshold op‐amps designed according to the proposed design procedure achieve a better trade‐off among speed, power, and load capacitance. Copyright © 2013 John Wiley & Sons, Ltd.     

Accurate design‐oriented simulation‐driven modeling of miniaturized microwave structures

One of the important prerequisites for efficient design optimization of microwave structures is availability of fast yet reliable replacement models (surrogates) so that multiple evaluations of the structure at hand can be executed in reasonable timeframe. Direct utilization of full‐wave electromagnetic (EM) simulations for handling optimization‐related tasks is often prohibitive. A popular approach to construction of fast surrogates is data‐driven modeling. Unfortunately, it normally requires a large number of training samples, and it is virtually infeasible for structures that exhibit highly nonlinear responses (e.g. filters or couplers). In this work, a design‐oriented modeling technique is proposed where good accuracy is achieved by careful non‐uniform design space sampling that accounts for nonlinear relationship between the operating frequency of the structure and its geometry parameters, as well as carrying out the modeling process only for selected characteristic points of the structure responses (those that determine satisfaction/violation of given design specifications). Our approach is demonstrated using a miniaturized microstrip rat‐race coupler modeled in a wide range of geometry parameters and compared to conventional data‐driven modeling using kriging interpolation. Design optimization examples are also provided. Copyright © 2016 John Wiley & Sons, Ltd.     

Higher‐order CN‐FETD method for analysis of microwave circuit structures

In this paper, the hierarchical high‐order basis functions on tetrahedrons are introduced to the Crank–Nicolson (CN) finite‐element time‐domain (FETD) with the 3D Maxwell equations for analysis of the microwave circuit structures. Whitney 1‐form high‐order hierarchical basis functions are used to expand the electric field and Whitney 2‐form high‐order hierarchical basis functions for the magnetic field. The CN scheme is employed in the FETD method to lead to an unconditionally stable algorithm. Numerical results were presented to demonstrate the accuracy and efficiency of the proposed high‐order CN‐FETD method. Copyright © 2012 John Wiley & Sons, Ltd.     

Design equations for fractional‐order sinusoidal oscillators: Four practical circuit examples

Four practical sinusoidal oscillators are studied in the general form where fractional‐order energy storage elements are considered. A fractional‐order element is one whose complex impedance is given by Z = a(jω)^±α, where a is a constant and α is not necessarily an integer. As a result, these oscillators are described by sets of fractional‐order differential equations. The integer‐order oscillation condition and oscillation frequency formulae are verified as special cases. Numerical and PSpice simulation results are given. Experimental results are also reported for a selected Wien‐bridge oscillator. Copyright © 2007 John Wiley & Sons, Ltd.     

A closed‐form equation approach to multi‐port/multi‐zone behavioral modeling of GaN FET Amplifiers

In this paper, a systematic method for the simulation of weakly and mildly nonlinear GaN FET amplifiers is reported. The core of the proposal is a third‐order Volterra‐based behavioral model with multi‐spectral and multi‐node capabilities that is formally derived from a circuit‐level representation. Starting with the equivalent circuit of a typical FET device with thermal power feedback and fading memory, described in terms of its large‐signal functions, closed‐form expressions for the kernels at the gate, drain and thermal nodes are developed up to the third order. The use of these kernels allows the calculation of the responses in the dc, first‐, second‐ and third‐harmonic zones, which are shown to be dependent on the frequency response of the amplifier circuit terminating impedances and thermal filter. The simulation approach has been applied to calculate the nonlinear response of a typical power amplifier circuit, showing the ability of the proposed approach to provide an accurate prediction of multi‐spectral, multi‐node, multi‐bias characteristics, including AM/AM‐AM/PM conversion, spectral regrowth, intermodulation, and temperature rise, under diverse input signal waveforms and bandwidths. These results have been successfully compared with commercial CAD tools based on harmonic balance or envelope simulation. Copyright © 2014 John Wiley & Sons, Ltd.     

Transformer‐coupled π‐network differential CMOS oscillator circuit topology

This paper reports a novel oscillator circuit topology based on a transformer‐coupled π‐network. As a case study, the proposed oscillator topology has been designed and studied for 60 GHz applications in the frame of the emerging fifth generation wireless communications. The analytical expression of the oscillation frequency is derived and validated through circuit simulations. The root‐locus analysis shows that oscillations occur only at that resonant frequency of the LC tank. Moreover, a closed‐form expression for the quality factor (Q) of the LC tank is derived which shows the enhancement of the equivalent quality factor of the LC tank due to the transformer‐coupling. Last, a phase noise analysis is reported and the analytical expressions of phase noise due to flicker and thermal noise sources are derived and validated by the results obtained through SpectreRF simulations in the Cadence design environment with a 28 nm CMOS process design kit commercially available. Copyright © 2016 John Wiley & Sons, Ltd.     

A study on the tie‐set graph theory and network flow optimization problems

Aiming at establishing a firm basic theory to ring‐based information network management systems, our paper proposes a tie‐set graph theory. We define a binary vector representing a tie‐set in a biconnected undirected graph G=(V,E) as a tie‐set vector. The set of tie‐set vectors forms a vector space over the proposed law of composition, then a basis of the vector space, μ linear independent tie‐set vectors, is defined as a tie‐set basis. The essential key concept in our theory is a tie‐set graph, which has a one‐to‐one correspondence to a tie‐set basis and represents a relation between two tie‐set vectors of the basis. Some important properties of tie‐set graphs and their application to survivable mesh networks in modern high‐speed backbone networks are also presented. Furthermore, as a general approach to network flow optimization problems, tie‐set flow vector space is proposed based on the tie‐set graph theory. A distributed algorithm for the network flow optimization problems and its application are also presented in this paper. Copyright © 2004 John Wiley & Sons, Ltd.     

A new two‐step single slope A/D converter for using in CMOS image sensors

This paper presents a high‐speed, high‐resolution column parallel analog‐to‐digital converter (ADC) with global digital error correction. Proposed A/D converter is suitable for using in high‐frame‐rate complementary metal–oxide–semiconductor (CMOS) image sensors. This new method has more advantages than conventional ramp ADC from viewpoint of speed and resolution. A prototype 11‐bit ADC is designed in 0.25‐µm CMOS technology. Moreover, an overall signal‐to‐noise ratio of 63.8 dB can be achieved at 0.5Msample/s. The power dissipation of all 320 column‐parallel ADCs with the peripheral circuits consume 76 mW at 2.5‐V supplies. Copyright © 2012 John Wiley & Sons, Ltd.     

Circuit implementation and model of a new multi‐scroll chaotic system

In this paper, a multi‐scroll chaotic system from the improved Chua's system is proposed. Moreover, non‐linear dynamics are analyzed including phase‐space trajectories, bifurcation diagrams, Poincaré maps and so on. The most important thing is that we discovered phase‐space trajectories, bifurcation diagrams and Poincaré maps are unified and closely related, which can describe different aspects of the multi‐scroll chaotic system. Furthermore, the corresponding improved module‐based circuits are designed for realizing two to four‐scroll chaotic attractors, and the experimental results are also obtained, which are consistent with the numerical simulations. Copyright © 2012 John Wiley & Sons, Ltd.     

Investigation of multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) sub‐50 nm MOSFET: A novel design

In this paper, a two‐dimensional (2D) analytical sub‐threshold model for a novel sub‐50 nm multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) MOSFET is presented and investigated using ATLAS device simulator to counteract the large gate leakage current and increased standby power consumption that arise due to continued scaling of SiO₂‐based gate dielectrics. The model includes the evaluation of surface potential, electric field along the channel, threshold voltage, drain‐induced barrier lowering, sub‐threshold drain current and sub‐threshold swing. Results reveal that MLGEWE‐RC MOSFET design exhibits significant enhancement in terms of improved hot carrier effect immunity, carrier transport efficiency and reduced short channel effects proving its efficacy for high‐speed integration circuits and analog design. Copyright © 2008 John Wiley & Sons, Ltd.     

A study of decoupling with skeleton matrix in two‐degree‐of‐freedom generalized minimum variance control

There are many multi‐input multi‐output (MIMO) systems in chemical plants, and they have multiple time delays of different length in each input and output pair. This paper explains a two‐degree‐of‐freedom (2DOF) control system based on generalized minimum variance control (GMVC) for MIMO systems. It can improve the tracking performance with respect to the reference signals and the response properties for the disturbance. The states between the sampling period can be expressed by using the modified z transform to take account of multiple time delays. Additionally, a tracking controller is designed to decouple the plant. © 2011 Wiley Periodicals, Inc. Electr Eng Jpn, 176(1): 28–36, 2011; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.21046     

Reliability evaluation of power systems with high short‐circuit current reduction

Similar to other cities worldwide, the increasing amounts of short‐circuit current in Bangkok (Thailand) and the vicinity areas are becoming higher than the interrupting capacity (IC) of circuit breakers. To cope with the problem, the Electricity Generating Authority of Thailand (EGAT) has come up with the solutions of network reconfiguration, e.g. bus splitting and transmission line disconnecting. These solutions help reduce effectively the amounts of short‐circuit currents by increasing the equivalent system impedance. However, bus splitting and transmission line disconnecting tend to decrease the system reliability. One of the alternative approaches, the installation of high‐voltage direct current (HVDC) can help reduce the amounts of short‐circuit currents, while the system reliability is maintained. Therefore, this paper mainly presents the reliability evaluation method of the systems with HVDC installation, which requires AC/DC power flow calculation. To avoid system constraint violation, generation redispatch, load shedding, and DC power flow control are executed. The Monte Carlo simulation is used to repeatedly evaluate the system reliability until convergence. The proposed method is tested in (i) the IEEE Reliability Test System 79 (RTS79) to confirm the correctness of reliability evaluation and (ii) the system of EGAT Bangkok including its vicinity areas to show the readiness for real implementation. Comparison of reliability indices among all solutions of short‐circuit current reduction is presented and discussed. The results show that the proposed method is effective and the HVDC installation can increase the system reliability, depending on its installation location and capacity. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.