Design and analysis of a millimeter‐wave injection locked frequency divider with transconductance boosting technique

This paper presents a degenerated injector (mixer) with transconductance boosted by biasing the mixer transistor in the knee region of its I‐V curve, without increasing the transistor size and its parasitics. This mixer can enhance the locking range of millimeter‐wave injection‐locked frequency dividers. To compensate the degradation of mixer transconductance (conversion‐gain) due to the degeneration effect, a neutralization technique is employed. Analyses are given for locking‐range and induced phase‐noise of the proposed divider for arbitrary injection strength. It is shown that the locking‐range, as a function of injection strength, is improved by increasing the fundamental component of transconductance. Using 180‐nm CMOS technology, a 1.78‐mW divider‐by‐two is designed with free‐running frequency of 27.92 GHz, locking‐range of 51 to 59.6 GHz, and figure‐of‐merit of 4.83 (GHz/mW). EM simulation results of the proposed and conventional structure are compared, which illustrates 56% improvement in locking‐range.     

Divide‐by‐2 LC injection‐locked frequency divider with wide locking range at low and high injection powers

A wide locking range nMOS divide‐by‐2 RLC injection‐locked frequency divider (ILFD) was designed and implemented in the TSMC 0.18‐µm BiCMOS process. The ILFD is based on a cross‐coupled oscillator with one direct injection MOSFET and a RLC resonator. The RLC resonator is used to extend the locking range so that dual‐band locking ranges can be merged in one locking range at both low and high injection powers. At the drain‐source bias of 0.9 V for switching transistors, and at the incident power of 0 dBm the locking range of the divide‐by‐2 ILFD is 7.24 GHz, from the incident frequency 2.65 to 9.89 GHz, the locking range percentage is 115.47%. The power consumption of ILFD core is 8.685 mW. The die area is 0.726 × 0.930 mm². Copyright © 2016 John Wiley & Sons, Ltd.     

Wide‐locking range divide‐by‐4 injection‐locked frequency divider using injection MOSFET DC‐biased above threshold region

A novel wide locking range divide‐by‐4 injection‐locked frequency divider (ILFD) is proposed in the paper and was implemented in the TSMC 0.18 µm 1P6M CMOS process. The divide‐by‐4 ILFD uses two injection transistors in series and DC‐biased above threshold voltage and a frequency doubler to enhance the function of linear mixers. At the drain‐source bias of 0.9 V and at the incident power of 0 dBm, the locking range of the divide‐by‐4 is 2.6 GHz; from the incident frequency 12.2 to 14.8 GHz, the percentage is 19.26%. The core power consumption is 10.35 mW. The die area of ILFD is 1.026 × 0.943 mm². Copyright © 2015 John Wiley & Sons, Ltd.     

Wide‐band dual‐resonance capacitive cross‐coupled divide‐by‐5 injection‐locked frequency divider

A wide locking range divide‐by‐5 injection‐locked frequency divider (ILFD) is proposed and was implemented in the TSMC 0.18‐μm 1P6M CMOS process. Conventional divide‐by‐5 ILFD has limited locking range. The proposed divide‐by‐5 ILFD is based on a capacitive cross‐coupled voltage‐controlled oscillator (VCO) with a dual‐resonance resonator, which is implemented in the divide‐by‐5 ILFD to obtain a wide overlapped locking range. At the drain‐source bias V_DD of 0.9 V and at the incident power of 0 dBm, the measured locking range of the divide‐by‐5 ILFD is 3.2 GHz, from the incident frequency 9.4 to 12.6 GHz, the percentage is 29.09%. The core power consumption is 2.98 mW. The die area is 0.987 × 1.096 mm².     

Wide‐band divide‐by‐2 injection‐locked frequency divider using MOSFET mixers DC‐biased in subthreshold region

A novel wide locking range divide‐by‐2 injection‐locked frequency divider (ILFD) is proposed in the paper and was implemented in the TSMC 0.18‐µm 1P6M CMOS process. The divide‐by‐2 ILFD is based on a cross‐coupled voltage‐controlled oscillator (VCO) with an LC resonator and injection MOSFETs with source voltage coupled from ILFD output, and the injection MOSFET mixer is biased in subthreshold region. At the drain–source bias of 0.9 V, and at the incident power of 0 dBm the locking range of the divide‐by‐2 ILFD is 6.4 GHz; from the incident frequency 3.7 GHz to 10.1 GHz, the percentage is 92.75%. The core power consumption is 16.56 mW. The die area is 0.839 × 0.566 mm². Copyright © 2015 John Wiley & Sons, Ltd.     

A study of superharmonic injection locking in multiband frequency dividers

A superharmonic voltage‐controlled injection‐locked frequency divider, implemented using a modified Colpitts oscillator operating at 2.5, 5 and 10 GHz and a cross‐coupled LC oscillator operating at 1.25, 2.5 and 5 GHz, is demonstrated. The proposed triple‐band operation is achieved by employing a novel technique that uses pin‐diodes and negative power supply. The discrete dividers, built with low noise hetero‐junction FETs and high‐frequency SiGe BJTs, are described theoretically while their functionality is proven experimentally. Additionally, a short phase noise analysis, which is missing in the literature, is given. Phase noise, frequency range of operation, and locking range measurement results are presented. Finally, post‐layout simulation results of a 5 GHz fully differential injection‐locked frequency divider, implemented in a 0.25µm SiGe process are provided. Copyright © 2010 John Wiley & Sons, Ltd.     

Evaluating the spectrum of periodic pulling in subharmonic resonant LC circuits

We analyze the features of the oscillations arising in forced inductor–capacitor (LC) oscillators when they operate in the periodic pulling mode, under the action of a weak injection signal. In radio frequency integrated circuits, both voltage‐controlled oscillators subject to undesired couplings and injection‐locked frequency dividers behave like forced LC oscillators. These are modeled as second‐order driven oscillators working in the subharmonic (secondary) resonance regime. The analysis is based on the generalized Adler's equation, which we introduce to describe the phase dynamics of dividers of any division ratio and to derive closed‐form expressions for the spectrum components of the system's oscillatory response. We show that the spectrum is double‐sided and asymmetric, unlike the single‐sided spectrum of systems with primary resonance. Numerical and experimental results are given to validate the presented results, which significantly generalize those available in the literature. Copyright © 2014 John Wiley & Sons, Ltd.     

A wideband low‐spur 0.18‐µm CMOS phase‐locked loop with bandwidth calibration

This paper presents a 0.18‐µm complementary metal‐oxide‐semiconductor wideband phase‐locked loop with low reference spurs. The dual‐level charge‐pump current calibration technique is proposed to maintain a constant loop bandwidth for wide operation frequency range and achieve low reference spurs. The first level charge‐pump current calibration is seamlessly incorporated in the automatic frequency band hopping control and the mechanism also ensures enough negative transconductance for the voltage‐controlled oscillator to function throughout the whole frequency range. The charge‐pump current mismatch is calibrated by the second level charge‐pump current calibration combined with the pulse‐width scaling technique. The operation frequency range of the phase‐locked loop covers from 4.7 GHz to 6.1 GHz. The measured phase noise is?116 dBc/Hz at 1‐MHz offset and the reference spurs are below?66.8 dBc. Copyright © 2015 John Wiley & Sons, Ltd.     

A quad‐band W‐CDMA transceiver IC–direct conversion architecture with fractional frequency divider

A quad‐band (0.8, 1.7, 2, and 1.4 GHz) wideband code division multiple access (W‐CDMA) transceiver, which uses a divide‐by‐2.5 frequency divider in local parts of a direct‐conversion architecture, has been developed. Using the fractional‐2.5 frequency divider reduces the fractional bandwidth of the voltage‐controlled oscillator and avoids injection locking of the local RF synthesizer perfectly. This transceiver achieved 3% error‐vector magnitude and—46 dB ACLR, which satisfy the margin given in standard specifications. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Performance characterization of a non‐linear system as both an adaptive notch filter and a phase‐locked loop

The behaviour of a non‐linear dynamical system is described. The system may be characterized as an adaptive notch filter, or alternatively, as a phase‐locked loop. Either way, the system has the inherent capability of directly providing estimates of the parameters of the extracted sinusoidal component of its input signal, namely its amplitude, phase and frequency. The structure and mathematical properties of the system are presented for two cases of fixed‐frequency and varying‐frequency operation. The effects of parameter setting of the system on its performance are studied in detail using computer simulations. Transient and steady‐state behaviour of the system are studied in the presence of noise. Simplicity of structure, high noise immunity and robustness and the capability of direct estimation of amplitude, phase and frequency are the salient features of the system when envisaged as an adaptive notch filter or a phase‐locked loop. Copyright © 2004 John Wiley & Sons, Ltd.     

Dynamics of charge‐pump phase‐locked loops

Certain problems in the existing treatment of the stability of charge‐pump phase‐locked loops are identified and addressed in this work. New results concerning the instability, stability, and asymptotic stability of charge‐pump phase‐locked loops are obtained by means of Lyapunov's direct and indirect methods. Closer consideration of the local dynamics provides further insight into the system's patterns of behavior. In particular, the influence of circuit parameters on the nature of the steady‐state orbits is investigated. Copyright © 2012 John Wiley & Sons, Ltd.     

A wide range delay locked loop for low power and low jitter applications

In this paper, a design of analog delay locked loop is introduced in which new techniques are applied to eventually increase operating frequency range and reduce jitter considerably. In this design, all blocks of a delay locked loop including a voltage controlled delay line, charge pump, and loop filter are accurately designed. A new delay cell is proposed with wide delay range, in which increase of delay range results in using fewer cells, and consequently the power consumption will decrease. Current mirror techniques and feedback in the proposed charge pump also cause higher current matching and better jitter performance. This delay locked loop, which is designed with TSMC 0.18‐μm CMOS technology, has a wide frequency range from 217 to 800 MHz. It consumes maximum 3.4‐mW and minimum 2.6‐mW power dissipation in source voltage of 1.8 V, which is suitable for low power applications. It also has an appropriate lock time that is at least equal to 3 clock cycles at 217 MHz and at most 25 clock cycles at 800 MHz. Jitter performance in this delay locked loop is improved significantly: RMS jitter is 0.65 ps at 800 MHz and 2.54 ps at 217 MHz. Moreover, its maximum peak‐to‐peak jitter is equal to 5.17 ps, and its minimum peak‐to‐peak jitter is equal to 1.39 ps at 217 and 800 MHz, respectively.     

Robust stability analysis and improved design of phase‐locked loops with non‐monotonic nonlinearities: LMI‐based approach

Due to nonlinear nature of several phase detectors, linear approximation method often leads to performance degradation in many phase‐locked loops (PLLs), particularly when the phase errors are sufficiently large. A third or higher order PLL, in spite of the ability to track a wider variety of inputs and having higher operating‐frequency range, requires more design attention in order to ensure stable tracking. In this work, with the nonlinearities inserted into the system's model, suitable criteria that take into account the nonlinearities' non‐monotonicity, sector and slope bounds are employed to establish robust stability conditions. The result is applicable to any PLLs without order and type restrictions. For Type‐1 PLLs, the resulting condition can be used to search for the maximum stable loop gain, which is also linked to the lock‐in range of the system. In the later part of this work, the focus is devoted towards designing PLLs with high lock‐in range, which is performed via mixing the proposed method with H _∞ synthesis. The searches for the parameters in both PLL analysis and design are expressed in terms of convex linear matrix inequalities, which are computationally tractable. To illustrate the improvement introduced via this approach, several numerical examples and simulations are included with comparisons over conventional methods. Copyright © 2017John Wiley & Sons, Ltd.     

A 120–420 MHz delay‐locked loop with multi‐band voltage‐controlled delay unit

A low‐jitter and low‐power dissipation delay‐locked loop (DLL) is presented. A proposed multi‐band voltage control delay unit (MVCDU) is employed to extend the operation frequency of the DLL by controlling the delay cell within the MVCDU. The jitter of DLL is reduced due to MVCDU's low sensitivity. The delay cell in the MVCDU employs a differential configuration to further reduce the noise impact from the fluctuation in the supply and ground voltage. The operating frequency of the proposed DLL ranges from 120 to 420 MHz. The proposed design has been fabricated in a TSMC 0.18µm CMOS process. The measured RMS and peak‐to‐peak jitters are 4.86 and 34.55 ps, respectively, at an operating frequency of 300 MHz. The power dissipation is below 14.85 mW at an operating frequency of 420 MHz. Copyright © 2010 John Wiley & Sons, Ltd.     

Modelling of impedance‐loaded wire frequency‐selective surfaces with tunable reflection and transmission characteristics

In this paper an efficient means to control the reflection and transmission characteristics of wire‐based frequency‐selective surfaces (FSS) using linear‐lumped impedance loading is presented. We show that by varying the topology of the RLC loading circuits and the component values it is possible to control the resonance frequency of the array as well as its angular characteristics. We discuss several examples, particularly a switchable dual band bandpass filter and enhancement of FSS angle‐of‐arrival properties. The analysis is based on the self‐consistent solution of thin wire Hallen's type integral equation solved by Galerkin's method. The periodic Green's function in the kernel of integral equation has been accelerated using the Ewald transformation, which leads to a highly accurate and efficient numerical procedure. Copyright © 2008 John Wiley & Sons, Ltd.     

Numerical analysis of optical feedback phenomenon and intensity noise of fibre‐grating semiconductor lasers

This paper demonstrates numerical analysis of the dynamics and intensity noise of fibre‐grating semiconductor lasers (FGSLs). The induced phenomenon of strong optical feedback (OFB) is analysed. The simulations are based on an improved time‐delay rate equations model of a single‐mode laser that takes into account the multiple round‐trips of the lasing field in the fibre cavity. The analyses are performed in terms of the temporal trajectory of the laser intensity, bifurcation diagram and relative intensity noise (RIN). We explore influence of the fibre‐cavity length on the dynamics and RIN. The results show that when the fibre cavity is short, the regime of strong OFB is characterized by either continuous‐wave (CW) operation or periodic pulsation. The pulsation frequency is locked at the frequency separation of either the compound‐cavity modes or the external fibre‐cavity modes. The corresponding RIN level is close to or higher than the level of the solitary laser depending on pulse symmetry. When the fibre cavity is long, the laser exhibits unstable dynamics over wider range of OFB. Moreover, the strong‐OFB pulsation becomes beating quasi‐periodic at the relaxation oscillation frequency and the fibre‐cavity mode‐separation frequency. Copyright © 2007 John Wiley & Sons, Ltd.     

Optimal frequency tracking method for phase‐shift PWM inverter

This paper proposes a new resonant frequency tracking control method for full‐bridge‐type high‐frequency inverters. Whereas the ordinary phase‐locked loop (PLL) based frequency control method uses a current sensor and a voltage sensor, the proposed technique can achieve the same purpose with a single current sensor. In high‐frequency power supply systems using a PLL, it is impossible to perform power control with an inverter. Therefore, an active converter must be used for power control, and the system grows larger. On the other hand, high‐frequency inverters using the proposed control system simultaneously enable power control and achieve the same resonant frequency tracking as a PLL, and thus high‐frequency power supply systems become extremely simple. This paper explains in detail the principle underlying the control method, and presents an example of a circuit to realize it. The theory is backed up by using a prototype high‐frequency power supply system which actually employs the proposed control system, thereby demonstrating its practical utility in industry. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Design and performance study of phase‐locked loop using fractional‐order loop filter

The present work reports the realization of an analog fractional‐order phase‐locked loop (FPLL) using a fractional capacitor. The expressions for bandwidth, capture range, and lock range of the FPLL have been derived analytically and then compared with the experimental observations using LM565 IC. It has been observed that bandwidth and capture range can be extended by using FPLL. It has also been found that FPLL can provide faster response and lower phase error at the time of switching compared to its integer‐order counterpart. Copyright © 2014 John Wiley & Sons, Ltd.     

A reduced reference spur multiplying delay‐locked loop

This letter presents a reduced reference spur multiplying delay‐locked loop (MDLL). The static phase offset (SPO) between the reference edge and its counterpart of MDLL output is the dominant mechanism causing reference spur in the spectrum of MDLL output. SPO is mainly caused by the non‐idealities on charge pump (e.g., sink and source current mismatch) and control line (e.g., gate leakage of loop filter and voltage‐controlled delay line control circuit). With a high‐gain stage inserting between phase detector/phase frequency detector and charge pump, the equivalent SPO has been decreased by a factor equal to the gain of the gain stage. To validate the effectiveness of the proposed technique, an MDLL is implemented in TSMC CMOS 0.18 µm process. The simulation result shows that ?60.1 dBc reference spur was achieved at center frequency of 1.8 GHz. Copyright © 2015 John Wiley & Sons, Ltd.     

Fast settling frequency synthesizer with two‐point channel control paths

A frequency synthesizer with low‐power and very short settling time is introduced, which utilizes two‐point channel control paths. While the main‐path is the same as normal channel controls, a digital‐to‐analog converter (DAC) with tunable gain is used for the compensation‐path to form a feed‐forward direct voltage‐controlled oscillator (VCO) control path. When the two paths are ideally matched, the two‐point control can show zero settling time regardless of the amount of frequency change. However, the settling time performance can be significantly degraded if there exists any mismatch between the two paths. In order to remove the mismatch, a simple compensation method combining a linearized VCO with a resistor‐loaded tunable DAC is presented. We show that the overall mismatch can be effectively tuned out by controlling the DAC load resistor, since the mismatch caused by process–voltage–temperature variations is dominated by the resistor variation. We have achieved near‐zero settling time for 75thinspaceMHz frequency jumping from 2.4 GHz even with the use of narrow phase‐locked loop (PLL) bandwidth of 20 kHz. When the phase noise at 1 MHz offset from 2.4 GHz is ? 116.6dBc/ Hz, the total PLL power consumption using 0.18 µm CMOS technology is only 4.2 mW. Copyright © 2011 John Wiley & Sons, Ltd.