Single‐Inductor Dual‐Output DC–DC Converter Design Using RC Ripple Regulator Method

In this paper, we have proposed Single‐Inductor Dual‐Output (SIDO) buck–buck and boost–boost dc–dc converter using improved RC ripple regulator control. The proposed SIDO buck–buck converter has the characteristics of low‐ripple and high control frequency. RC ripple regulator control cannot be applied to SIDO boost–boost converter because RC ripple regulator undergoes self‐excited oscillation and two self‐excited oscillating controllers make the SIDO converter unstable. Thus we proposed the priority circuit for RC ripple regulator control. The proposed control circuit improves response characteristic and simplicity of the control circuit. Simulations are performed to verify the validity of the proposed SIDO converter. Simulation results indicate good performance of the proposed SIDO converter.     

A single‐phase buck‐boost PFC converter with output‐voltage,ripple‐reducing operation

This paper describes a new single‐phase buck‐boost power‐factor‐correction (PFC) converter with output‐voltage, ripple reducing operation. The converter consists of a conventional buck‐boost PFC converter and an additional switch to obtain a freewheeling mode of the dc inductor current, and is operated by two modulators. The first modulator controls the buck‐boost switch to obtain PFC. The other modulator controls the square value of the instantaneous dc inductor current to perform the output‐voltage‐ripple‐reducing operation. In the two modulations, the time integral value of the input and output currents in each modulation period are controlled directly and indirectly, respectively. Thus, modulation errors or undesirable distortions of the input current and output voltage ripple are eliminated even if the dc inductor current produces large ripple in a low‐frequency range. The theories and combination techniques for the two modulators, implementation, and experimental results are described. © 1998 Scripta Technica, Electr Eng Jpn, 126(2): 56–70, 1999     

A new single‐phase high‐power‐factor converter with buck and buck–boost hybrid operation

In recent years, a wide variety of high‐power‐factor converter schemes have been proposed to solve the harmonic problem. The schemes are based on conventional boost, buck, or buck–boost topology, and their performance, such as output voltage control range in the boost and buck topology or efficiency in the buck–boost topology, is limited. To solve this, the authors propose a single‐phase high‐power‐factor converter with a new topology obtained from a combination of buck and buck–boost topology. The power stage performs the buck and buck–boost operations by a compact single‐stage converter circuit while the simple controller/modulator appropriately controls the alternation of the buck and buck–boost operation and maintains a high‐quality input current during both the buck and buck–boost operations. The proposed scheme results in a high‐performance rectifier with no limitation of output voltage control range and a high efficiency. In this paper, the principle and operation of the proposed converter scheme are described in detail and the theory is confirmed through experimental results obtained from 2‐kW prototype converter. © 2000 Scripta Technica, Electr Eng Jpn, 131(3): 91–100, 2000     

A power efficient buck‐boost converter by reusing the coil inductor for wireless bio‐implants

In this paper, a buck‐boost converter circuit for wireless power transfer via inductive links in bio‐implantable systems is presented. The idea is based on reusing the power receiver coil to design a regulator. This method employs five switches to utilize the coil inductor in a frequency other than the power‐receiving signal frequency. Reusing the coil inductor decreases the on‐chip regulator area and makes it suitable for bio‐implants. Furthermore, in the proposed technique, the regulator efficiency becomes almost independent of the coil receiving voltage amplitude. The proposed concept is employed in a buck‐boost regulator, and simulation results are provided. For a 10 MHz received signal with the amplitude variation within 3 ~ 6 V and with the converter switching rate of 200 kHz, the achieved maximum efficiency is 78%. The proposed regulator can also deliver 10 μA to 4 mA to its load while its output voltage varies from 0.6 to 2.3 V. Simulations of the proposed converter are performed in Cadence‐Spectre using TSMC 0.18 μm CMOS technology. Copyright © 2017 John Wiley & Sons, Ltd.     

Single‐stage single‐switch PFC converter for wide‐input extreme step‐down voltage applications

This paper presents a new single‐stage single‐switch high power factor correction AC/DC converter suitable for low‐power applications (< 150 W) with a universal input voltage range (90–265 V_rms). The proposed topology integrates a buck–boost input current shaper followed by a buck and a buck–boost converter, respectively. As a result, the proposed converter can operate with larger duty cycles compared with the existing single‐stage single‐switch topologies, hence, making them suitable for extreme step‐down voltage conversion applications. Several desirable features are gained when the three integrated converter cells operate in discontinuous conduction mode. These features include low semiconductor voltage stress, zero‐current switch at turn‐on, and simple control with a fast well‐regulated output voltage. A detailed circuit analysis is performed to derive the design equations. The theoretical analysis and effectiveness of the proposed approach are confirmed by experimental results obtained from a 100‐W/24‐V_dc laboratory prototype. Copyright © 2011 John Wiley & Sons, Ltd.     

A novel active‐clamp zero‐voltage‐switching buck‐boost converter

An active‐clamp zero‐voltage‐switching (ZVS) buck‐boost converter is proposed in this paper to improve the performance of converter in light load condition. By employing a small resonant inductor, the ZVS range of switches could be adjusted to very light load condition. Moreover, 2 clamping capacitors are added in the converter to eliminate the voltage spike on the switches during transition. The operating principle of the proposed converter is analyzed, and the optimal design guide for full range ZVS is also provided. A 60‐W output prototype is experimentally built and tested in laboratory to verify the feasibility of proposed converter. The measured results show the critical ZVS operation of power switches at 1 and 0.7‐W output power for buck and boost mode, respectively. The peak conversion efficiency is up to 92.3%.     

Analysis and design of a two‐transformer active‐clamping ZVS isolated inverse‐SEPIC converter

This paper presents a two‐transformer active‐clamping zero‐voltage‐switching (ZVS) isolated inverse‐SEPIC converter, which is mainly composed of two active‐clamping ZVS isolated inverse‐SEPIC converters. The proposed converter allows a low‐profile design for liquid crystal display TVs and servers. The presented two‐transformer active‐clamping ZVS isolated inverse‐SEPIC converter can equally share the total load current between two secondaries. Therefore, the output inductor copper loss and the output diode conduction loss can be decreased. Detailed analysis and design of this new two‐transformer active‐clamping ZVS isolated inverse‐SEPIC converter are described. Experimental results are recorded for a prototype converter with an AC input voltage ranging from 85 to 135 V, an output voltage of 12 V and a rated output current of 13.5A, operating at a switching frequency of 65 kHz. Copyright © 2012 John Wiley & Sons, Ltd.     

A single‐switch cascaded high step‐up voltage converter with 95% maximum efficiency for renewable energy systems

This paper proposes a novel nonisolated single‐switch cascaded high step‐up converter. The converter consists of coupled inductors, a clamp circuit, and cascaded capacitors to achieve high step‐up voltage output. Only one switch is used in the proposed converter; the switch can reduce cost efficiently and simplify the control of the proposed converter. The converter also possesses an energy‐recycle mechanism for recycling the spike energy of a leakage inductor. In addition, a clamp circuit is used to reduce voltage‐stress across the switch, and a cascaded design is used to reduce voltage‐stress across diodes and output capacitor. Thus, the proposed converter can select a low‐voltage stress switch for reducing circuit loss and improving the efficiency of the converter. Finally, in this study, a 400‐W nonisolated cascaded high step‐up converter was implemented, of which the input and output voltages are 48 and 400 V, respectively. A microcontroller dsPIC30F4011 was used to control the converter and verify system effects and feasibility. The maximum efficiency of the proposed converter is 95% and the efficiency under a full load is 93%. Copyright © 2015 John Wiley & Sons, Ltd.     

Non‐isolated large step‐down voltage conversion ratio converter with non‐pulsating output current

A non‐isolated dual half‐bridge large step‐down voltage conversion ratio converter with non‐pulsating output current, utilizing one coupled inductor, one energy‐transferring capacitor, and one output inductor, is presented herein. The coupled inductor is connected between the input voltage and the output inductor and plays a role to step down the input voltage. Furthermore, the output inductor is used not only to further step down the voltage but also to provide a non‐pulsating output current. Moreover, the proposed converter can achieve zero‐voltage switching. In this study, detailed theoretical deductions and some experimental results of a prototype with 48 V input voltage, 3.3 V output voltage, and 10 A output current are provided to demonstrate the feasibility and effectiveness of the proposed converter. Copyright © 2015 John Wiley & Sons, Ltd.     

High‐power‐factor single‐switch AC to DC converter for LED lighting

In this paper, we report a novel single‐switch AC to DC step‐down converter suitable for light emitting diodes. The proposed topology has a buck and a buck–boost converter. The circuit is designed to operate in the discontinuous conduction mode in order to improve the power factor. In this topology, a part of the input power is connected to the load directly. This feature of the proposed topology increases the efficiency of power conversion, improves the input power factor, produces less voltage stress on intermediate stages, and reduces the output voltage in the absence of a step‐down transformer. The theoretical analysis, design procedure, and performance of the proposed converter are verified by simulation and experiment. A 36 V, 60 W prototype has been built to demonstrate the merits of this circuit. © 2017 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Dynamic model development and control for multiple‐output flyback converters in DCM and CCM

Multiple‐output flyback converters are widely used in switching power supplies due to their low component count and cost‐effective structure. The main problem of this structure is how to balance output voltages in different load conditions. This paper proposes a new approach for single‐input multiple‐output flyback converters operating in DCM and CCM by a small‐signal averaged model. The averaged model is derived by presenting the piecewise‐linear waveform for the inductor currents inside the converter. In DCM, the magnetizing current and currents through the output windings reach zero when the switch is turned off. In CCM, the magnetizing current of the converter is continuous over a switching interval and this possibility exists that only some of the output diodes completely conduct when the switch is off. The proposed model of the converter can be used in a wide range of operations within identical and non‐identical loading conditions. Using a laboratory prototype, several case studies and input‐to‐output transfer functions are considered to verify the proposed model. The controller design is performed for the both CCM and DCM, and then dynamic characteristics of the overall system are evaluated.     

Unified Pulse‐Width Modulation Scheme for Improved Digital‐Peak‐Voltage Control of Switching DC‐DC Converters

Contrast to conventional dependent double‐edge (DDE) pulse‐width modulation (PWM), independent double‐edge (IDE) PWM is investigated and applied to the control of switching dc‐dc converters, with improved digital‐peak‐voltage (IDPV) controlled buck converter in this paper. IDE modulation unifies all the PWM schemes reported up to now and is thus called as unified PWM. It is revealed that conventional trailing‐edge, leading‐edge, trailing‐triangle, and leading‐triangle modulations are special cases of IDE modulation. The control laws of IDPV controlled buck converter with IDE modulation are investigated and compared with those of IDPV with DDE modulation. Their stabilities and robustness are analyzed subsequently. Digital implementation of the unified PWM is also carried out. Steady‐state and transient performances of IDPV controlled buck converters with IDE modulation and DDE modulation are compared and verified by experimental results. It is concluded that steady‐state and transient performances of IDPV with IDE are better than those of IDPV with DDE modulation. Copyright © 2012 John Wiley & Sons, Ltd.     

A new fast‐response buck converter using accelerated pulse‐width‐modulation techniques

A new fast‐response buck converter using accelerated pulse‐width‐modulation techniques is proposed in this article. The benefits of the accelerated pulse‐width‐modulation technique is fast‐transient response, simple‐compensation design, and no requirement for slope compensation; furthermore, some power management problems are minimized, such as EMI (Electro Magnetic Interference), size, design complexity, and cost. The traditional voltage‐mode speed is slower with the transient response, so an accelerated pulse‐width‐modulation technique is used to solve the problem of slowed transient response in this article. The proposed buck converter has excellent conversion efficiency with a wide load conditions. The proposed buck converter has been fabricated with TSMC 0.35 µm CMOS 2P4M processes, and the total chip area is 1.32 × 1.22 mm². Maximum output current is 300 mA when the output voltage equals 1.8 V. When the supply voltage is 3.6 V, the output voltage can be 1–2.6 V. Maximum transient response is less than 5 µs. The simulation and experimental results are presented in this article. Copyright © 2011 John Wiley & Sons, Ltd.     

Analysis and implementation of a high step‐up converter for fuel cell power‐generation systems

This paper presents a high step‐up converter, which utilizes a three‐winding coupled inductor and a rectified voltage‐doubler circuit to obtain high step‐up gain for fuel cells. The proposed converter functions as an active‐clamp circuit, which relieves large voltage spikes across the power switches. Thus, power switches with low‐voltage‐rated can be utilized to reduce conduction losses and circuit cost. Energy stored in leakage inductances of the coupled inductor is recycled to the output terminal, resulting in efficiency improvements. In addition, the coupled inductor in the presented converter can also have extra windings in order to achieve higher voltage gain. Finally, a prototype circuit with an input voltage of 60 V and an output voltage of 380 V is developed for a 1000 W‐rated fuel cell power‐generation system to validate its performance, and experimental waveforms and measured efficiency under different input voltages and output power level are demonstrated. Copyright © 2016 John Wiley & Sons, Ltd.     

A single‐stage phase‐shifted full‐bridge AC/DC converter with variable frequency control

This letter presents a single‐stage soft‐switched full‐bridge AC/DC converter for low‐voltage/high‐current output applications. A phase‐shifted method with a variable frequency control is used to regulate the DC bus voltage and the output voltage of the single‐stage AC/DC converter. The proposed circuit topology and control scheme exhibit superior performances (i.e. high power factor, high‐efficiency, and ring‐free features). Correspondingly, a laboratory prototype, 500 W 5V/100A AC/DC converter, is implemented to verify the feasibility of the proposed design. Copyright © 2009 John Wiley & Sons, Ltd.     

Improved control‐to‐output characteristics of a PWM buck‐boost converter

An indirect control variable for improving the control‐to‐output characteristics of a Pulse Width Modulation (PWM) buck‐boost converter is introduced in this letter. The voltage gain and the small‐signal model of the buck‐boost converter are reviewed. The actual voltage command at one input of the PWM comparator is from the proposed indirect control variable and the peak value of the high‐frequency PWM carrier. The resulted voltage gain function appears proportional to this indirect control command. Also the dependence of the DC gain of the control‐to‐output transfer function on the duty cycle is eliminated. Experimental results conform well to the theoretical analysis. Copyright © 2010 John Wiley & Sons, Ltd.     

Global hybrid modeling and control of a buck converter: A novel concept

Several attempts have been made to design suitable controllers for DC–DC converters. However, these designs suffer from model inaccuracy or their inability to desirably function in both continuous and discontinuous current modes. This paper presents a novel switching scheme based on hybrid modeling to control a buck converter using mixed logical dynamical (MLD) methodologies. The proposed method is capable of globally controlling the converter in both continuous and discontinuous current modes of operation by considering all constraints in the physical plant such as maximum inductor current and capacitor voltage limits. Different loads and input voltage disturbances are simulated in MATLAB and results are presented to demonstrate the suitability of the controller. The transient and steady‐state performance of the closed‐loop control over a wide range of operating points shows satisfactory operation of the proposed controller. Copyright © 2008 John Wiley & Sons, Ltd.     

Analysis of the ZVS two‐switch forward converter with synchronous current doubler rectifier

A soft switching two‐switch forward converter is presented to achieve zero voltage switching (ZVS) turn‐on of switching devices. In the adopted converter, a buck‐boost type of active clamp is connected in parallel with the primary winding of transformer. The energy stored in the transformer leakage inductance and magnetizing inductance can be recovered so that the peak voltage stress of switching devices is limited. The resonance between the transient interval of two main and auxiliary switches is used to achieve ZVS turn‐on of all switches. The current doubler synchronous rectifier is used in the secondary side of transformer for reducing the root mean square value of output inductor current, transformer secondary winding current and output voltage ripple by cancelling the current ripple of two output inductors. First, the circuit configuration and the principles of operation are analyzed in detail. The steady‐state analysis and design consideration are also presented. Finally, experimental results with a laboratory prototype based on a 380 V input and 12 V/30 A output were provided to verify the effectiveness of the proposed converter. Copyright © 2007 John Wiley & Sons, Ltd.     

An all‐digital DLL with duty‐cycle correction using reusable TDC

This paper presents the design of an all‐digital delay‐locked loop (ADDLL) with duty‐cycle correction using reusable time‐to‐digital converter (TDC). The proposed ADDLL uses a reusable TDC for achieving a wide‐operating frequency range. In addition, it achieves the frequency doubling output clock easily by changing the quantization interval. It is implemented in a 0.18‐µm complementary metal‐oxide semiconductor technology. This circuit corrects the duty cycle and synchronizes the input and output clocks in 10 clock cycles. The output duty cycle is corrected to 50 ± 1.5% as the input duty cycle ranges from 25% to 75%. The acceptable input frequency range is from 300 to 900 MHz without frequency doubling. The acceptable input frequency range is from 150 to 450 MHz when using frequency doubling. It dissipates 6.2 mW from a 1.8‐V supply at 900 MHz. The peak‐to‐peak and RMS jitters at 900 MHz are 14 and 1.8 ps, respectively. Copyright © 2015 John Wiley & Sons, Ltd.     

Design considerations for low power time‐mode SAR ADC

This paper describes circuit design considerations for realization of low power dissipation successive approximation register (SAR) analog‐to‐digital converter (ADC) with a time‐mode comparator. A number of design issues related to time‐mode SAR ADC are discussed. Also, noise and offset models describing the impact of the noise and offset on the timing error of time‐domain comparator are presented. The results are verified by comparison to simulations. The design considerations mentioned in this paper are useful for the initial design and the improvements of time‐mode SAR ADC. Then, a number of practical design aspects are illustrated with discussion of an experimental 12‐bit SAR ADC that incorporates a highly dynamic voltage‐to‐time converter and a symmetrical input time‐to‐digital converter. Prototyped in a 0.18‐µm six‐metal one‐polysilicon Complementary Metal‐Oxide‐Semiconductor (CMOS) process, the ADC, at 12 bit, 500 kS/s, achieves a Nyquist signal‐to‐noise‐and‐distortion ratio of 53.24 dB (8.55 effective number of bits) and a spurious‐free dynamic range of 70.73 dB, while dissipating 27.17 μW from a 1.3‐V supply, giving a figure of merit of 145 fJ/conversion‐step. Copyright © 2013 John Wiley & Sons, Ltd.