Realization of log‐domain high‐order transfer functions using first‐order building blocks and complementary operators

High‐order log‐domain filters could be easily designed by using the functional block diagram (FBD) representation of the corresponding linear prototype and a set of complementary operators. For this purpose, lossy and lossless integrator blocks have been already introduced in the literature. Novel first‐order log‐domain highpass and allpass filter configurations, which are fully compatible with the already published integrator blocks, are introduced in this paper. These are realized using integration and subtraction blocks or a novel differentiation configuration. As a result, a complete set of first‐order building blocks would be available for synthesizing any arbitrary high‐order transfer function. In order to verify the correct operation of the proposed structures, the performance of the introduced highpass filters was evaluated through simulation results. In addition, a fifth‐order log‐domain bandpass filter was designed and simulated using one of the introduced first‐order highpass filter configurations. Copyright © 2006 John Wiley & Sons, Ltd.     

Design of Sinh‐Domain filters using complementary operators

A new systematic method for designing Sinh‐Domain filters is introduced in this paper. This is achieved by employing an appropriate set of complementary operators, in order to transpose the conventional functional block diagram representation of each linear operation to the corresponding one into the Sinh‐Domain. The proposed method offers the benefits of facilitating the design procedure of high‐order Sinh‐Domain filters and of the absence of any restriction concerning the type and/or the order of the realized filter function. As an example, a third‐order Sinh‐Domain leapfrog filter is designed by employing the proposed set of operators. Two possible realizations are given and their performance has been evaluated and compared through simulation results. Copyright © 2011 John Wiley & Sons, Ltd.     

MOS‐only reduced‐order ELIN cochlear channels: comparative performance evaluation

This paper introduces and applies practical area‐reduction techniques on the analogue, externally linear‐internally nonlinear, complementary metal‐oxide semiconductor (CMOS) implementation of a cochlear channel. This channel is constructed on the basis of the biomimetic auditory filter called One‐Zero Gammatone Filter, and it has been synthesised using ultra‐low power Class‐AB biquadratic filters, which employ MOS transistors that operate in their weak inversion regime. The realisation of linear capacitors with appropriately configured MOS transistors, the order reduction of the One‐Zero Gammatone Filter transfer function and the employment of hyperbolic sine companding filters can lead to area reductions that range from 61.8% up to 91.9% of the original size. Comparative simulation results highlight the trade‐offs between performance, linearity, noise and power consumption of the designs. Copyright © 2016 John Wiley & Sons, Ltd.     

1.5 V square‐root domain universal biquad filters

Square‐root domain universal biquad topologies are introduced in this paper. One of them is single input multiple output, while the other one is multiple input single output biquad. Important benefits offered by the proposed topologies are the electronic adjustment of the resonant frequency and the capability for operating in a low‐voltage environment; also, the resonant frequency could be adjusted without disturbing the Q factor and vice‐versa. Simulation results using the Spectre simulator of the Analog Design Environment of Cadence software validate the correct operation of the proposed topologies and provide important performance characteristics. Copyright © 2011 John Wiley & Sons, Ltd.     

On the transposition of Gm–C filters to DC stabilized log‐domain filters

High‐order log‐domain filters could be designed by transposing the already known linear‐domain G_m–C filter topologies to the corresponding topologies in the log‐domain. This is achieved by using a non‐linear transconductor configuration, where the output current is exponentially related to its input and output voltages. A drawback of the non‐linear transconductor configuration already introduced in the literature is that a number of the transposed log‐domain filter topologies suffer from DC instability, while in some others a DC offset current appears at their output. In order to eliminate the aforementioned problems a modified non‐linear transconductor configuration for transposing G_m–C filter topologies to log‐domain filter topologies is introduced in this paper. The achieved improvements are demonstrated through a number of log‐domain filter configurations derived using the already introduced and the proposed transposition schemes. Copyright © 2006 John Wiley & Sons, Ltd.     

Square‐root domain linear transformation filters

A new systematic method for designing square‐root domain (SRD) linear transformation (LT) filter is introduced in this paper. For this purpose, a substitution table containing the SRD LT equivalent of each passive element has been introduced. The proposed equivalents have been realized by employing appropriate SRD building blocks with low‐voltage operation capability. As a design example, a 3rd‐order SRD LT filter has been realized and its performance has been evaluated through simulation results. In addition, the most important performance factors of the SRD filter have been compared with those achieved by the SRD filters derived according to the leapfrog, wave, and topological emulation methods. Copyright © 2010 John Wiley & Sons, Ltd.     

Log‐domain linear transformation filters revised: improved building blocks and comparison results

A method for designing high‐order log‐domain filters has already been proposed in the literature based on the concept of the classical linear transformation (LT) filters. For this purpose, a substitution table containing the log‐domain LT equivalent of each passive element has been introduced. Drawbacks of the log‐domain filter topologies derived according to this table are the following: (a) a dc offset current appears at the output of all pole filters and (b) dc instability is observed in the case of the substitution of LC resonators. In addition, an alternative technique already proposed for simulating filters with LC resonators is valid only under small‐signal conditions. In order to overcome the aforementioned problems, new log‐domain LT equivalents of a number of passive elements are introduced in this paper. The correct operation of the novel blocks has been verified through simulation results. Also, a comparison concerning the behaviour of the log‐domain LT filters and that of the filters derived according to the leapfrog and the wave methods has also been performed. Copyright © 2007 John Wiley & Sons, Ltd.     

Efficient optimization‐oriented design methodology of high‐order 3‐D filters using 2‐D and 3‐D electromagnetic simulators

This paper proposes a computationally highly efficient interface between two‐dimensional (2‐D) and three‐dimensional (3‐D) electromagnetic (EM) simulators for the optimization‐oriented design of high‐order 3‐D filters. In a first step, the novel optimization‐oriented design methodology aligns the 3‐D EM simulator response with the 2‐D EM simulator response of a low‐order 3‐D filter by using an inverse linear space mapping optimization technique. Then, a second mapping performs a calibration with the optimal 2‐D and 3‐D design parameters obtained from the first mapping. The optimization of high‐order filters is carried out using only the efficient 2‐D EM simulator, and the calibration equations directly give the design parameters of the 3‐D filter. The potential and the effectiveness of the proposed optimization‐oriented design methodology are demonstrated through the design of C‐band 3‐D evanescent rectangular waveguide bandpass filters with increasing orders from three to eight. Copyright © 2014 John Wiley & Sons, Ltd.     

A DC stabilized log‐domain nth‐order multifunction filter based on the decomposition of nth‐order HP filter function to FLF topology

The design of high‐order log‐domain filters can be easily accomplished by transposing already known linear‐domain G_m‐C filter topologies to their counterparts in the log‐domain through the employment of a set of complementary operators. To achieve the G_m‐C filter topologies, the multiple feedback approach is widely used due to its accrued advantages. In this paper a synthesis approach for the development of an nth‐order multifunction log‐domain filter comprising lowpass (LP), highpass (HP) and bandpass (BP) filter functions is proposed. The approach is based on the decomposition of nth‐order HP filter function to follow‐the‐leader‐feedback (FLF) topology. The design is simple and simultaneously achieves nearly all of the chief advantages. The design offers superior performance factors vis‐à‐vis the ones recently reported. To verify the high‐order behavior of the topology, a 5th‐order multifunction filter was designed and the achieved simulated results verify the theory. Copyright © 2008 John Wiley & Sons, Ltd.     

Analytical synthesis and comparison of voltage‐mode Nth‐order OTA‐C universal filter structures

Complementary single‐ended‐input operational transconductance amplifier (OTA)‐based filter structures are introduced in this paper. Through two analytical synthesis methods and two transformations, one of which is to convert a differential‐input OTA to two complementary single‐ended‐input OTAs, and the other to convert a single‐ended‐input OTA and grounded capacitor‐based one to a fully differential OTA‐based one, four distinct kinds of voltage‐mode nth‐order OTA‐C universal filter structures are proposed. TSMC H‐Spice simulations with 0.35µm process validate that the new complementary single‐ended‐input OTA‐based one holds the superiority in output precision, dynamic and linear ranges than other kinds of filter structures. Moreover, the new voltage‐mode band‐pass, band‐reject and all‐pass (except the fully differential one) biquad structures, all enjoy very low sensitivities. Both direct sixth‐order universal filter structures and their equivalent three biquad stage ones are also simulated and validated that the former is not absolutely larger in sensitivity than the latter. Finally, a very sharp increment of the transconductance of an OTA is discovered as the operating frequency is very high and leads to a modified frequency‐dependent transconductance. Copyright © 2010 John Wiley & Sons, Ltd.     

Analytical synthesis of odd/even‐nth‐order elliptic Cauer filter structures using OTRAs

The operational transresistance amplifier (OTRA), the dual of the well‐known operational transconductance amplifier, is an attractive element for use in circuit design. One odd‐nth‐order and two even‐nth‐order OTRA‐R‐C or OTRA‐MOS‐C elliptic Cauer filter structures are presented using new analytical synthesis methods (ASMs). Because it is assumed in the synthesis procedure that the transresistance R_m → ∞, but in view of the fact that R_m is finite in practice, the more the number of OTRAs employed, the worse the precision of the output signals. By studying the sensitivity of the output to component variations, more precise output may be obtained by selecting one or two appropriate capacitance(s)/resistance(s) and adjusting their values suitably. H‐spice simulations are given to validate and demonstrate the theoretical predictions. Copyright © 2012 John Wiley & Sons, Ltd.     

Analysis and implementation of a fourth‐order bandpass filter for R‐wave detection of an implantable cardiac microstimulator

This paper presents an ultra‐low‐power fourth‐order bandpass operational transconductance amplifier‐C (OTA‐C) filter for an implantable cardiac microstimulator used to detect the R‐wave of intracardiac electrograms. The OTA‐C filter fabricated by TSMC 0.35‐µm complementary metal–oxide–semiconductor (CMOS) technology is operated in the subthreshold region to save power under a supply voltage of 1 V. The current cancellation technique is adopted to reduce the transconductance of the amplifier. Through this, the low‐frequency OTA‐C filter can be realized by ultra‐low transconductance with on‐chip capacitors. Direct comparison to conventional RLC ladders replaced by OTA‐C circuits shows that the method of reducing the number of OTAs further diminishes power consumption. Design issues, including ultra‐low transconductance, linearity, and noise, are also discussed. Measurement results show that the low‐voltage, low‐power filter has a bandwidth between 10 and 50 Hz, third inter‐modulation distortion of ?40 dB, dynamic range of 43 dB, and power consumption of only 12 nW. The real electrocardiography signal is fed into the bandpass filter to verify the function of signal processing with the distribution of the R‐wave. Copyright © 2012 John Wiley & Sons, Ltd.     

A novel low‐spur DDFS utilizing the twice second‐order high‐pass error feedback architecture

In this paper, the twice second‐order high‐pass error feedback (EF) (twice second‐order high‐pass EF (HPEF)) utilizing re‐feedback process and phase‐bit splitting technique in the second‐order HPEF to design a simplified low‐spur direct digital frequency synthesizer is proposed. The proposed method performs phase‐bit splitting technique and re‐feedback process in order to make the phase change tremendously and scramble the periodicity of the phase sequences violently in the original feedback path. In addition, the noise spectrum power is spread more uniformly in order to effectively suppress the spurs due to phase‐truncated error effect. Thus, the twice second‐order HPEF is implemented on a field programmable gate array development board, the Altera Stratix II EP2S60. The simulation and experimental results show that the proposed method can effectively achieve better spectrum performance, such as spurious‐free dynamic range, as compared to basic phase truncation, first‐order HPEF and second‐order HPEF architectures. Copyright © 2012 John Wiley & Sons, Ltd.     

MTL‐based implementation of current‐mode CMOS RMS‐to‐DC converters

In this paper, systematic implementation of current‐mode RMS‐to‐DC converters based upon MOS translinear (MTL) principle, utilizing symmetric cascoded MTL cell (SCMC) is proposed. Theory of operation and mathematical analysis of both explicit (direct) and implicit (indirect) techniques for realization of SCMC‐based RMS‐to‐DC converters are discussed. The SCMC includes a folded MTL loop and realizes an MTL equation. MTL principle utilizes the square law characteristics of saturated MOS transistors to realize square‐root domain (SRD) functions. The SCMC is constructed by two connected cascoded current mirrors and has a compact, symmetric, and multi‐purpose structure, with capability of implementing the circuits into the programmable and configurable structures. The proposed RMS‐to‐DC converters utilize the SCMC along with a configurable current mirror array. The required squaring and square‐rooting functions are realized using the SCMC, after proper configuration of the current mirror array. The proposed circuits have been implemented using a reconfigurable architecture fabricated in a 0.5 µm CMOS technology. Copyright © 2014 John Wiley & Sons, Ltd.     

On the simulation of fast settling charge pump PLLs up to fourth order

In this paper, we discuss three different models for the simulation of integer‐N charge‐pump phase‐locked loops (PLLs), namely the continuous‐time s‐domain and discrete time z‐domain approximations and the exact semi‐analytical time‐domain model. The limitations of the two approximated models are analyzed in terms of error in the computed settling time as a function of loop parameters, deriving practical conditions under which the different models are reliable for fast settling PLLs up to fourth order. Besides, output spectral purity analysis methods based upon the time‐domain model are introduced and the results are compared with those obtained by means of the s‐domain model in terms of phase noise and reference spur estimation. As a case study, we use the three models to analyze a fast switching PLL to be integrated in a frequency synthesizer for WiMedia MB‐OFDM UWB systems. Copyright © 2010 John Wiley & Sons, Ltd.     

A 1‐Gbps reference‐less burst‐mode CDR with embedded TDC in a 65‐nm CMOS process

A reference‐less all‐digital burst‐mode clock and data recovery circuit (CDR) is proposed in the paper. The burst‐mode CDR includes a coarse and a fine time‐to‐digital converter (TDC) with embedded phase generator. A low‐power current‐starved inverter is employed as the delay unit of the fine TDC to acquire the high measurement resolution. A calibration method to diminish the inherent delay is used to reduce the quantization error of the recovery clock. The proposed CDR is fabricated in a 65‐nm CMOS process. Experiment results show that the CDR operates from 0.9 to 1.1 Gbps and have a 13‐bit consecutive identical digits (CIDs) tolerance.     

A sub‐1V supply CMOS voltage reference generator

An integrated sub‐1V voltage reference generator, designed in standard 90‐nm CMOS technology, is presented in this paper. The proposed voltage reference circuit consists of a conventional bandgap core based on the use of p‐n‐p substrate vertical bipolar devices and a voltage‐to‐current converter. The former produces a current with a positive temperature coefficient (TC), whereas the latter translates the emitter‐base voltage of the core p‐n‐p bipolar device to a current with a negative TC. The circuit includes two operational amplifiers with a rail‐to‐rail output stage for enabling stable and robust operation overall process and supply voltage variations while it employs a total resistance of less than 600 K Ω. Detailed analysis is presented to demonstrate that the proposed circuit technique enables die area reduction. The presented voltage reference generator exhibits a PSRR of 52.78 dB and a TC of 23.66ppm/^°C in the range of ? 40 and 125^°C at the typical corner case at 1 V. The output reference voltage of 510 mV achieves a total absolute variation of ± 3.3% overall process and supply voltage variations and a total standard deviation, σ, of 4.5 mV, respectively, in the temperature range of ? 36 and 125^°C. Copyright © 2011 John Wiley & Sons, Ltd.     

Modeling of ultra‐wideband indoor channels with the modified leapfrog ADI‐FDTD method

Full‐wave time‐domain electromagnetic methods are usually effective in rigorously modeling and evaluating ultra‐wideband (UWB) wireless channels. However, their computational expenditures are expensive, when they are used to deal with electrically large‐size problems consisting of fine structures. In order to reduce computational time, the unconditionally stable leapfrog alternating‐direction implicit finite‐difference time‐domain (leapfrog ADI‐FDTD) method has been proposed recently. In this paper, the leapfrog ADI‐FDTD algorithm is developed for simulating lossy objects, such as office walls, floors, and ceilings, for UWB communication channel characterization. It leads to effective UWB channel characterization with power‐decay time constant, path loss exponent, and probability distribution of power gain. In comparison with the conventional FDTD, the proposed method can achieve 60% saving in computational time while retaining good accuracy. Copyright © 2014 John Wiley & Sons, Ltd.     

A TLM‐Based Surge Analysis of Grounding Electrodes

In this paper, representations of a perfectly conducting thin wire and an imperfectly conducting medium in the transmission line modeling (TLM) calculation are briefly explained. Then, the method is applied to analyzing surge responses of a vertical parallelepiped grounding electrode and a square‐loop grounding electrode. Surge responses calculated using the TLM method agree reasonably well with the corresponding responses measured and calculated using the finite‐difference time‐domain method. It is probably the first time that surge responses of grounding electrodes have been analyzed reasonably accurately using the TLM method.     

A single‐bit continuous‐time delta‐sigma modulator using clock‐jitter and inter‐symbol‐interference suppression technique

This paper presents a technique for mitigating two well‐known DAC non‐idealities in continuous‐time delta‐sigma modulators (CTDSMs), particularly in wide‐band and low over‐sampling‐ratio (OSR) cases. This technique employs a special digital‐to‐analog convertor (DAC) waveform, called modified return‐to‐zero (MRZ), to reduce the time uncertainty effect because of the jittered clock at the sampling time instances and eliminate the effect of inter‐symbol‐interference (ISI) which degrades the modulator performance, especially when non‐return‐to‐zero (NRZ) DAC waveform is chosen in the modulator design. A third‐order single‐bit CTDSM is designed based on the proposed technique and step‐by‐step design procedure at circuit and system levels, considering clock jitter and ISI, is explained. Circuit simulations in 180‐nm CMOS technology show that in the presence of circuit non‐idealities which generate jitter and asymmetrical rise and fall times in the DAC current pulse, signal‐to‐noise‐distortion‐ratio (SNDR) of the proposed modulator is higher than the conventional modulator with NRZ waveform by about 10 dB. In these simulations, clock jitter standard deviation is 0.3% of the sampling period (T_S) and the difference between fall/rise times in the DAC current pulse is 4%T_S. Simulated at 600‐MHz sampling frequency (f_S) with an oversampling ratio (OSR) of 24, SNDR figure of merit (FOM_SNDR) of the proposed modulator in 180‐nm CMOS is 300 fj/conversion. Copyright © 2016 John Wiley & Sons, Ltd.