Noise‐immune dual‐rail dynamic circuit for wide fan‐in gates in asynchronous designs

Dual‐rail dynamic logic circuits can provide inverting and noninverting outputs, especially for asynchronous designs, to implement complicated gates at the cost of approximately doubling the area and power consumption. In this paper, a new dual‐rail dynamic circuit is proposed which has lower die area consumption and higher noise immunity without dramatic speed degradation for even wide fan‐in gates for asynchronous circuits. The main idea in the proposed circuit is that voltage due to the current of the pulldown network (PDN) is compared with the reference voltage to provide two complementary outputs. The reference voltage almost corresponds to the leakage current of the PDN with all transistors being off. The proposed circuit is compared with conventional dual‐rail circuits such as differential domino logic and differential cross‐coupled domino logic. Simulation results for 32‐bit‐wide OR gates designed using high‐performance 16‐nm predictive technology model demonstrate significant performance advantages such as 66% power reduction and at least 2.86× noise‐immunity improvement at the same delay compared to the differential domino circuits. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Automating the sizing of transistors in CMOS gates for low‐power and high‐noise margin operation

This paper presents an automatic method for sizing the transistors in CMOS gates. The method utilizes a feedback control system to efficiently optimize the transistor sizes in small and large fan‐in gates, with the primary goal of enhancing noise robustness (as characterized by the static noise margin). The gates retain their robustness under threshold‐voltage variations over a range of supply voltages. The optimized gates not only expend reduced power and energy, but also take up less area than the conventional ones. These multi‐faceted gains, however, do incur some performance loss. Copyright © 2014 John Wiley & Sons, Ltd.     

Power‐delay optimization of D‐latch/MUX source coupled logic gates

In this paper a design strategy for MUX, XOR and D‐latch source coupled logic (SCL) gates is proposed. To this end, an analytical model of the delay and the noise margin as a function of the transistors' aspect ratio and bias current is first introduced. Successively, analytical equations of the transistors' aspect ratio to meet a given noise margin specification are derived as a function of the bias current, and are then used along with the delay model to express the delay as an explicit function of the bias current and noise margin. The simplified delay expression explicitly relates speed performance to power dissipation and the noise margin, thereby providing the designer with the required understanding of the trade‐offs involved in the design. Therefore, the criteria proposed allow the designer to consciously manage the power‐delay trade‐off. The delay dependence on the logic swing is also investigated with results showing that this delay is not necessarily reduced by reducing the logic swing, in contrast with the usual assumption. Since the results obtained are valid for all SCL gates and are independent of the CMOS process used, the guidelines provided afford a deeper understanding of SCL gates from a design point of view. Copyright © 2005 John Wiley & Sons, Ltd.     

Gate‐level body biasing for subthreshold logic circuits: analytical modeling and design guidelines

Gate‐level body biasing provides an attractive solution to increase speed and robustness against process and temperature variations while maintaining energy efficiency. In this paper, the behavior of basic logic gates, designed according to the proposed design technique, is analytically examined with the main purpose of furnishing important guidelines to design efficient subthreshold digital circuits. Our modeling has been fully validated by comparing the predicted results with SPICE simulations performed for a commercial 45‐nm complementary metal oxide semiconductor technology. Considering process, temperature and loading capacitance variations, the delay of an inverter is predicted with a maximum error lower than 16.5%. Even better results are obtained when our modeling is applied to more complex logic gates. Under process, loading capacitance and temperature variations, the delay of NAND2 and NOR2 logic gates is always predicted with an error below 10%. Good agreement between the predicted and simulated results makes our modeling a valuable support during the circuit design phase. Copyright © 2014 John Wiley & Sons, Ltd.     

Modelling of source‐coupled logic gates

In this paper, the modelling of CMOS SCL gates is addressed. The topology both with and without output buffer is treated, and the noise margin as well as propagation delay performance are analytically derived, using standard BSIM3v3 model parameters. The propagation delay model of a single SCL gate is based on proper linearization of the circuit and the assumption of a single‐pole behaviour. To generalize the results obtained to cascaded gates, the effect of the input rise time and the loading effect of an SCL gate are discussed. The expressions obtained are simple enough to be used for pencil‐and‐paper evaluations and are helpful from the early design phases, as they relate SCL gates performance to design and process parameters, allowing the designer to gain an intuitive understanding of performance dependence on design parameters and technology. The model has been validated by comparison with extensive simulations using a 0.35‐µm CMOS process. The model agrees well with the simulated results, since in realistic cases the difference is less than 20% both for noise margin and delay. Therefore, the model proposed can be profitably used for pencil‐and‐paper evaluations and for computer‐based timing analysis of complex SCL circuits. Copyright © 2002 John Wiley & Sons, Ltd.     

A general SPICE compatible circuit model for single‐electron devices and application to bit‐error‐rate calculations

The main purpose of this paper is study of the single‐electron devices (SEDs) behavior, having metal islands, in the time domain. On this basis, some new conceptions, such as division of islands in independent type and dependent type and introduction of multi‐dimensional state space for a SED, have been presented. Then, a new circuit model is introduced for SEDs in general N‐dimensional case. This model is based on the orthodox theory and the solution of the time‐dependent master equation with the capability of installation in the HSPICE software. Hence, one can simulate behavior of the compound circuits including SEDs and other circuit elements by help of this model. Another interesting characteristic of the introduced circuit model is the possibility of using it in calculation of bit error rate in single‐electron logical gates considering both the time and the temperature effects. The behavior of various SEDs in low frequencies is studied, and the results are compared with the results of SIMON, often used as a reference. Furthermore, the time‐dependent results of these devices in high frequencies are calculated and compared with the analytic results for step inputs. These comparisons indicate accuracy and validity of the model. Finally, the model is used for simulating time‐dependent behavior of some single‐electron logic gates, and their total error rate are calculated. Copyright © 2013 John Wiley & Sons, Ltd.     

Static and dynamic characteristics of dual gate organic TFT based NAND and NOR circuits

This research paper analyzes the static and dynamic behavior of dual-gate organic thin film transistors (DG-OTFTs) based universal logic gates using the Atlas 2-D numerical device simulator. The electrical characteristics and performance parameters of pentacene based DG-OTFT is evaluated and verified with respect to the reported experimental results. The NAND and NOR logic gate circuits are realized using \(p\) -type designs in diode-load logic (DLL) and zero- \(V_{gs}\) -load logic (ZVLL). The results show that the logic functions in ZVLL configuration outperforms the DLL ones mainly in terms of noise margin, gain and voltage swing; however, there is a trade-off in terms of speed. The ZVLL NAND gate demonstrates an increment of 16 and 32 % in voltage swing and noise margin, respectively in comparison to the DLL one. Besides this, the gain also increases by 1.5 times in ZVLL mode. On the contrary, the DLL configuration demonstrates a significant reduction of 64 % in the propagation delay in comparison to the ZVLL. Similarly, NOR gate shows an increment of 24 and 30 % in voltage swing and noise margin, respectively under ZVLL configuration. However, the propagation delay for DLL NOR configuration is one-fourth of that of its ZVLL counterpart.     

Modelling and design considerations on CML gates under high‐current effects

In this paper, the effect of the transit time degradation of bipolar transistors on the power‐delay trade‐off in CML gates and their design is dealt with. A delay model which accounts for the transit time increase due to the high bias current values used in high‐speed applications is derived by generalizing an approach previously proposed by the same authors (IEEE Trans. CAD 1999; 18 (9):1369–1375; Model and Design of Bipolar and MOS Current—Mode Logic (CML, ECL and SCL Digital Circuits), Kluwer Academic Publisher: Dordrecht, 2005). The resulting closed‐form delay expression is achieved by properly simplifying the SPICE model, and has an explicit dependence on the bias current which determines the power consumption of CML gates. Accordingly, the delay model is used to gain insight into the power‐delay trade‐off by considering the effect of the transit time degradation in high‐speed designs. In particular, the cases where such effects can be neglected are identified, to better understand how the transit time degradation affects the performance of CML gates for current bipolar technologies. The proposed model has a simple and compact expression, thus it turns out to be suitable for pencil‐and‐paper evaluations, as well as fast timing analysis. Simulations of CML circuits with a 20‐GHz bipolar process show that the model has a very good accuracy in a wide range of current and loading conditions. Copyright © 2005 John Wiley & Sons, Ltd.     

Analytic transient solution of SCFL logic gates

In this paper we propose the analytical solution of switching transients for SCFL logic gates. The analysis of an SCFL logic gate is carried out without linearization and can be brought back to multiple analyses of a basic cell, given by a differential pair with switching input voltages and a variable tail current, to take the effect of series‐gating into account. The differential equation for this cell is a Riccati equation, if a quadratic current–voltage relationship is used for the transistors, and it can be solved by the infinite power series method, in case of polynomial input signals. An algorithm is proposed to analyse the full transient of a complex SCFL gate. This provides a closed form expression for transient signals in terms of circuit and device parameters, that can be used for symbolic analysis or fast time‐domain numerical simulation. Some case studies are presented for SCFL gates using OMMIC ED02AH technology, and a good agreement between the proposed model and SPICE simulations using complex device models is obtained. Copyright © 2005 John Wiley & Sons, Ltd.     

基于KM和AC-BFA模糊逻辑的土石坝压实质量实时评价

针对常用的压实质量评价存在未能够实现压实质量的实时评价，且模型的精度与鲁棒性有待提高等问题，建立一种新的压实质量实时评价模型。该模型由提出的基于核方法（kernel method，KM）与自适应混沌细菌觅食算法（adaptive chaotic bacteria foraging algorithm，AC-BFA）的模糊逻辑构建，同时将被碾材料的物理参数、料源特性参数、施工过程碾压参数作为模型的输入参数，其中被碾压材料的物理参数由振动信号分解后得到的基波与一次谐波的振幅表征。工程应用表明，该模型与常用压实质量评价模型相比，不仅在精度上具有一致性与优越性，而且在加噪数据与异常数据测试中显示出更强的鲁棒性，在进一步嵌入到碾压质量实时监控系统后能够实现压实质量的实时评价。     

A power‐performance tunable logic with adjustable threshold pseudo‐dynamic building blocks and CMOS compatibility

The continued downscaling of CMOS technology has resulted in very high performance devices, but power dissipation is a limiting factor on this way. Power and performance of a device are dependent on process, temperature, and workload variation that makes it impossible to find a single power optimal design. As a result, adaptive power and performance adjustment techniques emerged as attractive methods to improve the effective power efficiency of a device in modern design approaches. Focusing on this issue, in this paper, a novel logic family is proposed that enables tuning the transistor's effective threshold voltage after fabrication for higher speed or lower power. This method along with dynamic voltage scaling allows simultaneous optimization of static and dynamic power based on the workload requirement. The externally static topology of the proposed logic makes it possible to replace static circuits without requiring significant changes in the system. Experimental results obtained using 90‐nm CMOS standard technology show that the proposed logic improves the average power‐delay product by about 40% for the attempted benchmarks.     

预测控制在同步电动机传动系统中的应用研究

根据同步电动机传动的矿井主扇通风系统的实际工况,研究了通风网络的风网特征的数学模型。在此基础上,建立了主扇同步机预测控制模型。仿真研究表明,采用预测控制方法控制同步电动机,矿井通风系统的动态性能得到明显改善,并且具有较强的抗干扰能力和鲁棒性。     

FDSTDL: Low-power technique for FinFET domino circuits

Major issues in designing low-power high-speed VLSI circuits are propagation delay, power consumption, and noise tolerance. This paper describes fin field-effect transistor (FinFET) technology for the design of low-power VLSI circuits. FinFET uses two gates (front and back) in place of a single gate as in complementary metal-oxide–semiconductor (CMOS) technology for better control of the channel. A new technique foot driven stack transistor domino logic (FDSTDL) is proposed for designing domino logic circuits in order to reduce leakage power and propagation delay. In this paper, 2-, 4-, 8-, and 16-input domino OR gates are designed and simulated using existing and proposed techniques in CMOS and FinFET technology. Simulation is done on the 32 nm predictive technology model (PTM) node using HSPICE on a direct current (DC) supply voltage of 0.9 V. The proposed circuit is simulated in two modes of FinFET, short gate (SG) mode, and low power (LP) mode. The proposed technique shows maximum power reduction of 43.45% in SG mode in comparison with conditional stacked keeper domino logic (CSK-DL) technique and maximum delay reduction of 38.66% in LP mode in comparison with coarse-mesh finite difference (CMFD) technique at a frequency of 200 MHz.     

A 1-bit full adder using CNFET based dual chirality high speed domino logic

CNFET devices are preferred over CMOS devices for designing high-speed digital circuits. This paper introduces a new technique Dual Chirality High-speed Domino Logic (DCHSDL) for implementing low power and high-speed domino circuits in CNFET technology. Simulations are carried out for 32 nm Stanford CNFET model in HSPICE for 2, 4, 8 and 16 input domino OR gates at a clock frequency of 200 MHz on a DC supply voltage of 0.9 V. The proposed domino technique shows maximum power reduction of 82.55% and maximum delay reduction of 57.97% compared to CPVT technique in CNFET technology at a frequency of 200 MHz. The proposed circuit shows maximum power reduction of 97.90% compared to its analogous circuit in CMOS technology for a 2-input domino OR gate. The proposed technique shows maximum improvement of 1.05× to 1.63× in unity noise gain (UNG) compared to various existing techniques in CNFET technology at a frequency of 200 MHz. The 1-bit Full Adder designed using the proposed technique shows a power reduction of 16.91% and a delay reduction of 23.64% compared to standard FDL 1-bit Full Adder.     

A numerical model for the oscillation frequency,the amplitude and the phase‐noise of MOS‐current‐mode‐logic ring oscillators

This paper presents a new model for the frequency of oscillation, the oscillation amplitude and the phase‐noise of ring oscillators consisting of MOS‐current‐mode‐logic delay cells. The numerical model has been validated through circuit simulations of oscillators designed with a typical 130 nm CMOS technology. A design flow based on the proposed model and on circuit simulations is presented and applied to cells with active loads. The choice of the cell parameters that minimize phase‐noise and power consumption is addressed. Copyright © 2009 John Wiley & Sons, Ltd.     

Noise‐tolerant dynamic CMOS circuits design by using true single‐phase clock latching technique

In this paper, a true‐single‐phase clock latching based noise‐tolerant (TSPCL‐NT) design for dynamic CMOS circuits is proposed. A TSPCL‐NT dynamic circuit can isolate and filter noise before the noise enters into the dynamic circuit. Therefore, it cannot only greatly enhance the noise tolerance of dynamic circuits but also release the signal contention between the feedback keeper and the pull‐down network effectively. As a result, noise tolerance of dynamic circuits can be improved with lower sacrifice in power consumption and operating speed. In the 16‐bit TSPCL‐NT Manchester adder, the average noise threshold energy can be enhanced by 3.41 times. In the meanwhile, the power‐delay product can be improved by 5.92% as compared with the state‐of‐the art 16‐bit XOR‐NT Manchester adder design under TSMC 90 nm CMOS process. Copyright © 2014 John Wiley & Sons, Ltd.     

An improved charge-sharing elimination pseudo-domino logic

In low-power digital circuit, the deviation of node voltage from nominal value due to charge-sharing leads to erroneous output. This problem is more prominent in domino logic when the device is scaled down. The scaling of the device involves scaling of threshold voltage, resulting in high leakage, less robustness and degradation in noise margin. The paper proposes an improved domino approach in terms of reduced leakage, low power dissipation and better noise margin. The stacking effect and pseudo buffer are used in precharge phase to control the gate-to-source voltage of pull-down network for less power consumption and increase in performance in terms of speed of operation. A modified keeper is introduced to reduce the charge-sharing problem. The proposed domino approach is tested against area overhead, ageing and process, voltage and temperature variation. The circuit is simulated using Cadence Virtuoso Spectre for 90 nm technology. The results obtained from the simulation represent the usefulness of the proposed circuit in terms of power dissipation, stability due to temperature variation, leakage due to temperature variation and delay. The result also shows that the circuit is less prone to charge redistribution problem that exist in domino circuit.     

基于细胞神经网络的逻辑函数设计

基于细胞神经网络构造动态逻辑门是近年来一个全新的研究方向。由于非线性系统状态演化具有很强的非线性特征和丰富的动态模式,细胞神经网络在构建灵活、可重构的逻辑门电路中具有独特的优势。本文提出基于细胞神经网络的逻辑函数设计,首先设计了两输入线性可分布尔函数“与”门和“或”门的标准非耦合细胞神经网络的模板参数的求解过程,然后给出了使用运放实现的细胞电路设计以及功能之间转换的时序仿真结果。同时以此方式设计了另外12种两输入线性可分布尔函数的模板参数,实现了在电路结构不变的情况下,改变参数即能动态调整布尔逻辑的功能。     

Error probability independent delay analysis of single electronics circuits

This study based on Poisson process and orthodox theory of single electron tunneling for the first time proposes an error probability independent delay model for delay calculation of single electronics circuits, involving multiple tunneling events. The Poisson process assumes that the tunneling events are independent of each other, but in real single electronics circuits they are correlated through space and time, so this effect has been considered and included in the proposed model. The dependence of tunneling rates on the logic transition is thoroughly investigated. Finally, the model is applied to different logic gates, and the result is compared with the well known Monte Carlo approach to prove the accuracy of the proposed model.