Impact of high‐κ gate dielectric and other physical parameters on the electrostatics and threshold voltage of long channel gate‐all‐around nanowire transistor

High‐κ gate‐all‐around structure counters the Short Channel Effect (SCEs) mostly providing excellent off‐state performance, whereas high mobility III–V channel ensures better on‐state performance, rendering III–V nanowire GAAFET a potential candidate for replacing the current FinFETs in microchips. In this paper, a 2D simulator for the III–V GAAFET based on self‐consistent solution of Schrodinger–Poisson equation is proposed. Using this simulator, capacitance–voltage profile and threshold voltage are characterized, which reveal that gate dielectric constant (κ) and oxide thickness do not affect threshold voltage significantly at lower channel doping. Moreover, change in alloy composition of In_xGa_1‐xAs, channel doping, and cross‐sectional area has trivial effects on the inversion capacitance although threshold voltage can be shifted by the former two. Although, channel material also affects the threshold voltage, most sharp change in threshold voltage is observed with change in fin width of the channel (0.005 V/nm for above 10 nm fin width and 0.064 V/nm for sub‐10 nm fin width). Simulation suggests that for lower channel doping below 10²³ m⁻³, fin width variation affects the threshold voltage most. Whereas when the doping is higher than 10²³ m⁻³, both the thickness and dielectric constant of the oxide material have strong effects on threshold voltage (0.05 V/nm oxide thickness and 0.01 V/per unit change in κ). Copyright © 2014 John Wiley & Sons, Ltd.     

Degradation of direct‐tunneling gate oxide under hot hole injection

The degradation of ultrathin SiO₂ films accompanied by the hole direct tunneling is investigated using a substrate hot hole (SHH) injection technique. Hot holes from the substrate as well as cold holes in the inversion layer are injected into the gate oxides in p‐channel MOSFETs with p⁺ poly‐Si gates, while the gate bias is kept low enough to avoid simultaneous electron injection from the gate. During the SHH stress, in contrast to the case of thicker oxide films, a strong correlation is observed between the oxide film degradation and the injected hole energy, whereas no degradation occurs due to the hole direct tunneling from the inversion layer. These experimental findings indicate the existence of threshold energy for trap creation process, which has been predicted by the theoretical study of hole‐injection‐induced structural transformation of oxygen vacancy in SiO₂. © 2002 Wiley Periodicals, Inc. Electr Eng Jpn, 140(4): 54–61, 2002; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.2008     

A 1.9‐GHz silicon‐on‐insulator CMOS stacked‐FET power amplifier with uniformly distributed voltage stresses

A 1.9‐GHz single‐stage differential stacked‐FET power amplifier with uniformly distributed voltage stresses was implemented using 0.32‐μm 2.8‐V thick‐oxide MOSFETs in a 0.18‐μm silicon‐on‐insulator CMOS process. The input cross‐coupled stacked‐FET topology was proposed to evenly distribute the voltage stresses among the stacked transistors, alleviating the breakdown and reliability issues of the stacked‐FET power amplifier in sub‐micrometer CMOS technology. With a 4‐V supply voltage, the proposed power amplifier with an integrated output coupled‐resonator balun showed a small‐signal gain of 17 dB, a saturated output power of 26.1 dBm, and a maximum power‐added efficiency of 41.5% at the operating frequency. Copyright © 2017 John Wiley & Sons, Ltd.     

Low‐power,low‐area preamplifier for ultra high‐speed multi‐channel optical communication system

A novel circuit technique was applied to the design of a preamplifier for ultra high‐speed short‐distance parallel optical communication system in standard 180‐nm CMOS technology. This circuit is featured by low power, low area as well as high gain bandwidth product, and suited for applications in low‐cost process. The restraint on voltage headroom as bottleneck in traditionally adopted regulated cascode configuration has been fundamentally analyzed and lifted by feed‐forward common gate stage to achieve high gain bandwidth product under limited f_T and strict power restriction. Complex poles were carefully assigned to further attain bandwidth extension without sacrifice on power, noise, and chip area. No additional peaking techniques and subsequent gain‐boosting stages are adopted, which makes the design simple and favorable in low‐cost high‐density multi‐channel optical communication system. The preamplifier provides a trans‐impedance gain of up to 52 dBΩ and a 3‐dB bandwidth of 8.4 GHz. Operating under a 1.8‐V supply, the power dissipation is 8 mW, and the chip area is only 0.075×0.08 mm. The measured average input‐referred noise–current spectral density is . Copyright © 2011 John Wiley & Sons, Ltd.     

A physically based,accurate compact model of direct tunneling gate current considering quantum mechanical effects in nanoscale metal‐oxide‐semiconductor field‐effect transistors

We present a physically based, accurate model of the direct tunneling gate current of nanoscale metal‐oxide‐semiconductor field‐effect transistors considering quantum mechanical effects. Effect of wave function penetration into the gate dielectric is also incorporated. When electrons tunnel from the metal oxide semiconductor inversion layer to the gate, the eigenenergies of the quasi‐bound states turn out to be complex quantities. The imaginary part of these complex eigenenergies, Γ_ij, are required to estimate the finite lifetimes of these states. We present an empirical equation of Γ_ij as a function of surface potential. Inversion layer electron concentration is determined using eigenenergies, calculated by modified Airy function approximation. Hence, a compact model of direct tunneling gate current is proposed using a novel approach. Good agreement of the proposed compact model with self‐consistent numerical simulator and published experimental data for a wide range of substrate doping densities and oxide thicknesses states the accuracy and robustness of the proposed model. The proposed model can well be extended for devices with high‐κ/stack gate dielectrics introducing necessary modifications. Copyright © 2011 John Wiley & Sons, Ltd.     

A low‐voltage band‐gap reference circuit with second‐order analyses

A new band‐gap reference (BGR) circuit employing sub‐threshold current is proposed for low‐voltage operations. By employing the fraction of V_BE and the sub‐threshold current source, the proposed BGR circuit with chip area of 0.029mm² was fabricated in the standard 0.18µm CMOS triple‐well technology. It generates reference voltage of 170 mV with power consumption of 2.4µW at supply voltage of 1 V. The agreement between simulation and measurement shows that the variations of reference voltage are 1.3 mV for temperatures from ?20 to 100^°C, and 1.1 mV per volt for supply voltage from 0.95 to 2.5 V, respectively. Copyright © 2010 John Wiley & Sons, Ltd.     

A high‐order curvature‐corrected CMOS bandgap voltage reference with constant current technique

A high‐order curvature‐corrected complementary metal–oxide–semiconductor (CMOS) bandgap voltage reference (BGR), utilizing the temperature‐dependent resistor and constant current technique, is presented. Considering the process variation, a resistor trimming network is introduced in this work. The circuit is implemented in a standard 0.35‐µm CMOS process. The measurement results have confirmed that the proposed BGR operates with a supply voltage of 1.8 V, consuming 45 μW at room temperature (25 °C), and the temperature coefficient of the output voltage reference is about 5.5 ppm/°C from −40 °C to 125 °C. The measured power supply rejection ratio is −38.8 dB at 1 kHz. The BGR is compatible with low‐voltage and low‐power circuit design when the structure of operational amplifiers and all the devices in the proposed bandgap reference are properly designed. Copyright © 2012 John Wiley & Sons, Ltd.     

An analytical study of undoped symmetric double gate MOSFET (SDG)

In the present paper, compact analytical models for the threshold voltage, threshold voltage roll‐off and subthreshold swing of undoped symmetrical double‐gate MOSFET have been developed based on analytical solution of two‐dimensional Poisson's equation for potential distribution. The developed models include drain‐induced barrier lowering (DIBL) through the V_ds‐dependent parameter. The calculated threshold voltage value, obtained from the proposed model, shows a good agreement with the experimental and published results. The simulation results for potential show that the conduction is highly confined to the surfaces. The threshold voltage sensitivity to the thickness is found to be approximately 0.2%. Model prediction indicates that subthreshold slope is not linearly related to DIBL parameter for thick silicon film. The proposed analytical models not only provide useful insight into behavior of symmetrical DG MOSFETs but also serve as the basis for compact modeling. Copyright © 2010 John Wiley & Sons, Ltd.     

0.3‐V bulk‐driven programmable gain amplifier in 0.18‐µm CMOS

A new solution for an ultra low voltage bulk‐driven programmable gain amplifier (PGA) is described in the paper. While implemented in a standard n‐well 0.18‐µm complementary metal–oxide–semiconductor (CMOS) process, the circuit operates from 0.3 V supply, and its voltage gain can be regulated from 0 to 18 dB with 6‐dB steps. At minimum gain, the PGA offers nearly rail‐to‐rail input/output swing and the input referred thermal noise of 2.37 μV/Hz^1/2, which results in a 63‐dB dynamic range (DR). Besides, the total power consumption is 96 nW, the signal bandwidth is 2.95 kHz at 5‐pF load capacitance and the third‐order input intercept point (IIP₃) is 1.62 V. The circuit performance was simulated with LTspice. Copyright © 2016 John Wiley & Sons, Ltd.     

A 5.25‐V‐tolerant bidirectional I/O circuit in a 28‐nm CMOS process

A 5.25‐V‐tolerant bidirectional I/O circuit has been developed in a 28‐nm standard complementary metal‐oxide‐semiconductor (CMOS) process with only 0.9 and 1.8 V transistors. The transistors of the I/O circuit are protected from over‐voltage stress by cascode transistors whose gate bias level is adaptively controlled according to the voltage level of the I/O pad. The n‐well bias level of the p‐type metal‐oxide‐semiconductor transistors of the I/O circuit is also adapted to the voltage level of the I/O pad to prevent any junction leakage. The 5.25‐V‐tolerant bidirectional I/O circuit occupies 40 µm × 170 µm of silicon area. Copyright © 2014 John Wiley & Sons, Ltd.     

Threshold voltage extraction techniques adaptable from sub‐micron CMOS to large‐area oxide TFT technologies

This paper proposed simple and accurate threshold voltage (V _TH ) extraction techniques, which can be directly adaptable to various semiconductor technologies ranging from deep sub‐micron complementary metal–oxide–semiconductor to large‐area thin‐film transistor devices. These techniques are developed using multiple circuits, namely, a dynamic source follower, an inverter with a diode‐connected load and a current mirror topology, which allow a direct determination of V _TH . As the proposed techniques are experimented with large‐area emerging technologies, which have a stable single type (n‐type) transistor, all the designs employed in this work are confined to only n‐type transistors for a fair comparison. The semiconductor technologies under consideration are standard complementary metal–oxide–semiconductor (65 and 130 nm) and oxide (indium–gallium–zinc–oxide and zinc–tin–oxide) thin‐film transistors. In order to validate the accuracy of the proposed techniques, extracted V _TH from these methods are compared against the value from linear transfer characteristics. The resulting relative error is within 5%, reinforcing proposed techniques suitability to different semiconductor technologies ranging from deep sub‐micron to large‐area transistors. Copyright © 2017 John Wiley & Sons, Ltd.     

Ultra‐low voltage fractional‐order circuits using current mirrors

Fractional‐order blocks, including differentiators, lossy and lossless integrators as well as filters of order 1 + a (0 < a < 1), are presented in this paper. The proposed topologies offer the benefit of ultra low‐voltage operation; in addition, reduced circuit complexity is achieved compared to the corresponding companding schemes, which have been already introduced in the literature. The ultra‐low voltage operation is performed through the employment of metal oxide semiconductor transistors biased in the subthreshold region. The reduction of circuit complexity is achieved through the utilization of current mirrors as active elements for realizing the required building blocks. The performance of the proposed fractional‐order circuits has been evaluated through the Analog Design Environment of the Cadence software and the design kit provided by the Taiwan Semiconductor Manufacturing Company (TSMC) 180 nm complementary metal oxide semiconductor process. Copyright © 2015 John Wiley & Sons, Ltd.     

Enhancing the performances of recycling folded cascode OpAmp in nanoscale CMOS through voltage supply doubling and design for reliability

Current‐oriented operational amplifier (OpAmp) design has been common for its orderly current‐to‐speed tradeoff. However, for high‐precision or high‐linearity applications, increasing the current does not help much, as the supply voltage (V_DD) and intrinsic gain of the MOSFETs in ultra‐scaled CMOS technologies are very limited. This paper introduces voltage‐oriented circuit techniques to address such limitations. Specifically, a 2xV_DD‐enabled recycling folded cascade (RFC) OpAmp is proposed. It features: (1) current recycling to enhance the effective trans conductance by 4x with no extra power; (2) transistor stacking to boost the output resistance by one to two orders of magnitude; and (3) V_DD elevating to enlarge the linear output swing by 4x. Comparing with its 1xV_DD RFC and FC counterparts, the proposed solution achieves 20‐dB higher DC gain (i.e. 72.8 dB) in open loop and 20‐dB lower IM3 (i.e., –76.5 dB) in closed loop, under the same power budget of 0.6 mW in a 1‐V General Purpose 65‐nm CMOS process. In many applications, these joint improvements in a single stage are already adequate, being more power efficient (i.e. less current paths), stable (i.e. more phase margin), and compact (i.e. no frequency compensation) than multi‐stage OpAmps. Voltage‐conscious biasing and node‐voltage trajectory check ensure the device reliability in both transient and steady states. No specialized high‐voltage device is necessary. Copyright © 2012 John Wiley & Sons, Ltd.     

A 0.75‐V, 4‐μW, 15‐ppm/°C, 190 °C temperature range,voltage reference

A low‐voltage, low‐power, low‐area, wide‐temperature‐range CMOS voltage reference is presented. The proposed reference circuit achieves a measured temperature drift of 15 ppm/°C for an extremely wide temperature range of 190 °C (?60 to 130 °C) while consuming only 4 μW at 0.75 V. It performs a high‐order curvature correction of the reference voltage while consisting of only CMOS transistors operating in subthreshold and polysilicon resistors, without utilizing any diodes or external components such as compensating capacitors. A trade‐off of this circuit topology, in its current form, is the high line sensitivity. The design was fabricated using TowerJazz semiconductor's 0.18‐µm standard CMOS technology and occupies an area of 0.039 mm². The proposed reference circuit is suitable for high‐precision, low‐energy‐budget applications, such as mobile systems, wearable electronics, and energy harvesting systems. Copyright © 2015 John Wiley & Sons, Ltd.     

Analysis and design of a high‐compliance ultra‐high output resistance current mirror employing positive shunt feedback

This paper reports a novel high‐compliance, very accurate and ultra‐high output resistance current mirror. These features are achieved by employing a combination of negative and positive feedbacks in the proposed circuit. This makes the proposed current mirror unique in gathering ultra‐high output resistance, high compliance, and high accuracy ever demanded merits. The principle of operation of this structure is discussed, its main formulas are derived and its outstanding performance is verified by Cadence post‐layout simulations. Designed in the IBM 130‐nm standard CMOS process, the circuit consumes 230 × 110 µm² of silicon area. Post‐layout simulation results indicate that with a 3.3‐V power supply, output voltage compliance of 0.93V_Supply is achieved at a maximum output current of 96 μA. Moreover, an extremely ultra‐high output resistance of 320 GΩ is achieved, which is one of the highest reported values of output resistance for current mirrors implemented using regular CMOS technology. The ?3 dB upper cut‐off frequency of the proposed circuit is 100 MHz and the output/input current transfer error is 0.1%. The whole circuit, including bias circuitry, consumes 0.57 mW when delivering 96 μA to the load. Copyright © 2014 John Wiley & Sons, Ltd.     

Spin‐thermoelectric voltage in longitudinal SSE elements incorporating LPE YIG films and polycrystalline YIG slabs with an ultrathin Pt layer

A spin‐thermoelectric (STE) voltage is generated when a temperature gradient ?T is applied to an element having a thin Pt layer coated on a magnetic substance. In this study, yttrium iron garnet (YIG) ferrimagnetic films prepared by liquid phase epitaxy (LPE) were tested as magnetic insulators. In addition, polycrystalline YIG slabs were tested to compare the STE voltages of film and slab samples. In a Pt coating and YIG film bilayer structure made by an ultrathin Pt layer of 1‐4 nm thickness and an LPE film of approximately 10 µm thickness, a large STE voltage of 600 µV was observed at a probe distance of 5 mm with a temperature difference ?T of 30 K. On the other hand, the STE voltage of a Pt layer and YIG slab bilayer structure was 340 µV, which is roughly half of that of the Pt/YIG‐film element. The cause of the large voltage observed experimentally for the longitudinal spin Seebeck effect element incorporating an LPE YIG film was discussed mainly from the viewpoint of the Pt layer resistivity and the effects of YIG specimen surface conditions on crystallinity and the magnetization process.     

A sub‐1V supply CMOS voltage reference generator

An integrated sub‐1V voltage reference generator, designed in standard 90‐nm CMOS technology, is presented in this paper. The proposed voltage reference circuit consists of a conventional bandgap core based on the use of p‐n‐p substrate vertical bipolar devices and a voltage‐to‐current converter. The former produces a current with a positive temperature coefficient (TC), whereas the latter translates the emitter‐base voltage of the core p‐n‐p bipolar device to a current with a negative TC. The circuit includes two operational amplifiers with a rail‐to‐rail output stage for enabling stable and robust operation overall process and supply voltage variations while it employs a total resistance of less than 600 K Ω. Detailed analysis is presented to demonstrate that the proposed circuit technique enables die area reduction. The presented voltage reference generator exhibits a PSRR of 52.78 dB and a TC of 23.66ppm/^°C in the range of ? 40 and 125^°C at the typical corner case at 1 V. The output reference voltage of 510 mV achieves a total absolute variation of ± 3.3% overall process and supply voltage variations and a total standard deviation, σ, of 4.5 mV, respectively, in the temperature range of ? 36 and 125^°C. Copyright © 2011 John Wiley & Sons, Ltd.     

0.5‐V bulk‐driven differential amplifier

A new 0.5‐V fully differential amplifier is proposed in this article. The structure incorporates a differential bulk‐driven voltage follower with conventional gate‐driven amplification stages. The bulk‐driven voltage follower presents differential gain equal to unity while suppressing the input common‐mode voltage. The amplifier operates at a supply voltage of less than 0.5 V, performing input transconductance almost equal to a gate transconductance and relatively high voltage gain without the need for gain boosting. The circuit was designed and simulated using a standard 0.18‐µm CMOS n‐well process. The low‐frequency gain of the amplifier was 56 dB, the unity gain bandwidth was approximately 3.2 MHz, the spot noise was 100 nV/√Hz at 100 kHz and the current consumption was 90 μΑ. Copyright © 2012 John Wiley & Sons, Ltd.     

Threshold voltage modeling for dual‐metal quadruple‐gate (DMQG) MOSFETs

In this paper, a three‐dimensional (3D) model of threshold voltage is presented for dual‐metal quadruple‐gate metal‐oxide‐semiconductor field effect transistors. The 3D channel potential is obtained by solving 3D Laplace's equation using an isomorphic polynomial function. Threshold voltage is defined as the gate voltage, at which the integrated charge (Q_inv) at the ‘virtual‐cathode’ reaches to a critical charge Q_th. The potential distribution and the threshold voltage are studied with varying the device parameters like gate metal work functions, channel cross‐section, oxide thickness, and gate length ratio. Further, the drain‐induced barrier lowering has also been analyzed for different gate length ratios. The model results are compared with the numerical simulation results obtained from 3D ATLAS device simulation results. Copyright © 2015 John Wiley & Sons, Ltd.     

A 5‐MHz AT‐cut quartz crystal oscillating circuit functioning in 350 nA

An oscillating circuit functioning at ultra low power (350 nA) for a 5‐MHz AT‐cut quartz crystal oscillator was investigated. This circuit has a resistance between the power terminal of the CMOS‐IC and the power supply, and another between the earth terminal of the CMOS‐IC and the ground (GND). These resistances discourage an inrush of current, and set a gain (g_m) necessary for oscillating the circuit at minimum. The developed circuit is quite simple, but enables driving at once‐unthinkable, low power (below 1 µA). © 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.