Simple and accurate approaches to implement the complex trans‐conductance suited for time‐domain simulators for small‐signal and large‐signal table‐based models

This paper focuses on the implementation of table‐based models of high‐frequency transistors for time‐domain simulators at microwave and mm‐wave frequencies. In this frequency range, the channel is not capable of responding to the excitation instantaneously therefore, a delay‐time exists between the channel response and the channel excitation. This delay is represented by a complex trans‐conductance in terms of circuit elements. The high‐frequency models of transistors are required to have the implementation of complex trans‐conductance, where the complex part accounts mathematically for the delay‐time between the channel response and the channel excitation. This paper presents simple and accurate approaches to incorporate the complex trans‐conductance in both small‐signal and large‐signal table‐based models for time‐domain simulators (MOS‐AK International Meeting. Eindhoven, Netherlands, April 2008). Implementation approach for each model, small‐signal and large‐signal, is presented in separated sections. In the first step, the delay is realized by the introduction of an ideal transmission line between the channel excitation and the channel response. As transmission lines are not generally suitable for time‐domain simulations, a lumped element equivalent network is introduced in the second step. The latter approach is fully compatible with time‐domain simulators but frequency limitation, determined by the delay‐time value itself, is introduced. Then the implementation of the complex trans‐conductance in large‐signal model is introduced. In terms of large‐signal behavior, delay‐time is important to achieve a non‐quasi static model. Yet again there is limitation in terms of the frequency range that is determined by the delay value itself. The methodology is illustrated on the small‐signal and the large‐signal equivalent circuit of a Multi‐Fin MOSFET transistor. Simulations are carried out by Cadence Spectre and Agilent ADS simulators, and comparisons are carried out between the simulation results and the measurements. Copyright © 2010 John Wiley & Sons, Ltd.     

Analytical estimation of propagation delay and short‐circuit power dissipation in CMOS gates

An efficient analytical method for calculating the propagation delay and the short‐circuit power dissipation of CMOS gates is introduced in this paper. Key factors that determine the operation of a gate, such as the different modes of operation of serially connected transistors, the starting point of conduction, the parasitic behaviour of the short‐circuiting block of a gate and the behaviour of parallel transistor structures are analysed and properly modelled. The analysis is performed taking into account second‐order effects of short‐channel devices and for non‐zero transition time inputs. Analytical expressions for the output waveform, the propagation delay and the short‐circuit power dissipation are obtained by solving the differential equations that govern the operation of the gate. The calculated results are in excellent agreement with SPICE simulations. Copyright © 1999 John Wiley & Sons, Ltd.     

Higher‐order finite‐difference schemes with reduced dispersion errors for accurate time‐domain electromagnetic simulations

The potential for developing higher‐order finite‐difference time‐domain (FDTD) schemes with reduced phase errors is investigated in the present paper. Using the classic (2,4) FDTD method as the basis of this study, electromagnetic wave propagation is accurately reproduced in the discretized space by replacing isotropic materials with modified, anisotropic in general, ones. The use of such artificial materials improves the simulation's precision significantly around a specific frequency, yet the overall error remains small at a considerably wide bandwidth; therefore, this algorithm can be useful for wideband problems as well. Additionally, it is shown that an even better single‐frequency performance can be attained, when the modified materials are combined with systematically calculated spatial operators. Pursuing a more wideband enhancement of the (2,4) technique, a version realizing more accurate results at almost all frequencies that can be coupled in a staggered grid is derived. Furthermore, novel spatial operators are introduced, with the distinct feature of using extended stencils in more than one directions. It turns out that when such operators are incorporated, a scheme that combines the aforementioned features can be obtained. The theoretical findings of this investigation are verified in a sequence of numerical tests, involving free‐space and guided‐wave propagation, as well as the determination of a cavity's resonant frequencies. Copyright © 2004 John Wiley & Sons, Ltd.     

Noise‐immune dual‐rail dynamic circuit for wide fan‐in gates in asynchronous designs

Dual‐rail dynamic logic circuits can provide inverting and noninverting outputs, especially for asynchronous designs, to implement complicated gates at the cost of approximately doubling the area and power consumption. In this paper, a new dual‐rail dynamic circuit is proposed which has lower die area consumption and higher noise immunity without dramatic speed degradation for even wide fan‐in gates for asynchronous circuits. The main idea in the proposed circuit is that voltage due to the current of the pulldown network (PDN) is compared with the reference voltage to provide two complementary outputs. The reference voltage almost corresponds to the leakage current of the PDN with all transistors being off. The proposed circuit is compared with conventional dual‐rail circuits such as differential domino logic and differential cross‐coupled domino logic. Simulation results for 32‐bit‐wide OR gates designed using high‐performance 16‐nm predictive technology model demonstrate significant performance advantages such as 66% power reduction and at least 2.86× noise‐immunity improvement at the same delay compared to the differential domino circuits. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

The dynamic properties of a single‐phase transformer‐based inverter for ups systems

This paper presents two algorithms for the creation of an analytical model of a single‐phase transformer‐based inverter, using either the measurements of the control frequency‐dependent characteristics of the inverter or the initial in‐circuit frequency‐dependent measurements of the transformer. The paper discusses how the parameters of the line transformer influence the dynamic properties of the inverter and, as a consequence, the design of the instantaneous control feedback loop. Line transformers, widely used in industry, have not yet been analysed for use at higher than normal operating frequencies. The basic parameters of the transformer are the nonlinear functions of the primary voltage amplitude and frequency. The paper includes verification of both methods using the breadboard experimental model. In the final step, the inverter control transfer functions are calculated. To show the utility of both models, an exemplary discrete controller for the experimental inverter model has been designed and tested. Copyright © 2015 John Wiley & Sons, Ltd.     

Gate‐level body biasing for subthreshold logic circuits: analytical modeling and design guidelines

Gate‐level body biasing provides an attractive solution to increase speed and robustness against process and temperature variations while maintaining energy efficiency. In this paper, the behavior of basic logic gates, designed according to the proposed design technique, is analytically examined with the main purpose of furnishing important guidelines to design efficient subthreshold digital circuits. Our modeling has been fully validated by comparing the predicted results with SPICE simulations performed for a commercial 45‐nm complementary metal oxide semiconductor technology. Considering process, temperature and loading capacitance variations, the delay of an inverter is predicted with a maximum error lower than 16.5%. Even better results are obtained when our modeling is applied to more complex logic gates. Under process, loading capacitance and temperature variations, the delay of NAND2 and NOR2 logic gates is always predicted with an error below 10%. Good agreement between the predicted and simulated results makes our modeling a valuable support during the circuit design phase. Copyright © 2014 John Wiley & Sons, Ltd.     

Modelling of source‐coupled logic gates

In this paper, the modelling of CMOS SCL gates is addressed. The topology both with and without output buffer is treated, and the noise margin as well as propagation delay performance are analytically derived, using standard BSIM3v3 model parameters. The propagation delay model of a single SCL gate is based on proper linearization of the circuit and the assumption of a single‐pole behaviour. To generalize the results obtained to cascaded gates, the effect of the input rise time and the loading effect of an SCL gate are discussed. The expressions obtained are simple enough to be used for pencil‐and‐paper evaluations and are helpful from the early design phases, as they relate SCL gates performance to design and process parameters, allowing the designer to gain an intuitive understanding of performance dependence on design parameters and technology. The model has been validated by comparison with extensive simulations using a 0.35‐µm CMOS process. The model agrees well with the simulated results, since in realistic cases the difference is less than 20% both for noise margin and delay. Therefore, the model proposed can be profitably used for pencil‐and‐paper evaluations and for computer‐based timing analysis of complex SCL circuits. Copyright © 2002 John Wiley & Sons, Ltd.     

Potential‐based threshold voltage and subthreshold swing models for junctionless double‐gate metal‐oxide‐semiconductor field‐effect transistor with dual‐material gate

On the basis of quasi‐two‐dimensional solution of Poisson's equation, an analytical threshold voltage model for junctionless dual‐material double‐gate (JLDMDG) metal‐oxide‐semiconductor field‐effect transistor (MOSFET) is developed for the first time. The advantages of JLDMDG MOSFET are proved by comparing the central electrostatic potential and electric field distribution with those of junctionless single‐material double‐gate (JLSMDG) MOSFET. The proposed model explicitly shows how the device parameters (such as the silicon thickness, oxide thickness, and doping concentration) affect the threshold voltage. In addition, the variations of threshold voltage roll‐off, drain‐induced barrier lowering (DIBL), and subthreshold swing with the channel length are investigated. It is proved that the device performance for JLDMDG MOSFET can be changed flexibly by adjusting the length ratios of control gate and screen gate. The model is verified by comparing its calculated results with those obtained from three‐dimensional numerical device simulator ISE. Copyright © 2015 John Wiley & Sons, Ltd.     

Calculation of sudden three‐phase short‐circuit current of turbine generators by 3D magnetic field analysis

Sudden three‐phase short‐circuit current of a turbine generator was calculated by a three‐dimensional magnetic field analysis. That analysis takes into account the rotation, magnetic saturation, and eddy current at a rotor part. To compare test results and calculated results, a method was proposed for short‐circuit phase estimation at sudden three‐phase short‐circuit test by line voltage waveform of the test results. The calculated results of short‐circuit current waveform are in good agreement with the test results. © 2005 Wiley Periodicals, Inc. Electr Eng Jpn, 153(1): 54–62, 2005; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20110     

A wave‐front‐time dependent corona model for transmission‐line surge calculations

For transmission‐line surge studies, the inclusion of corona discharge due to high voltage surges is important as well as the inclusion of frequency‐dependent effects. Because the charge‐voltage (q‐v) curve of a lightning surge is different from that of a switching surge, a corona model should reproduce different q‐v curves for different wave‐front times. The present paper proposes a wave‐front time dependent corona model which can express the dependence by a simple calculation procedure as accurately as a rigorous finite‐difference method which requires an enormous calculation time. The simplicity enhances the incorporation of the corona model into a line model, because a large number of models are to be inserted into the line model by discretization. The q‐v curves calculated by the proposed method agrees well with field tests. This paper also proposes an efficient method to deal with nonlinear corona branches in distributed‐parameter line model using the trapezoidal rule of integration and the predictor‐corrector method. © 1999 Scripta Technica, Electr Eng Jpn, 129(1): 29–38, 1999     

Improved static and dynamic performances of a two‐cell DC–DC buck converter using a digital dynamic time‐delayed control

Multi‐cell converters have been developed to overcome shortcomings in usual switching devices. The control system in these circuits is twofold: first, to balance voltages of the switches and second to regulate the load current to a desired value. However, with a purely proportional controller, the system presents a static error. With a PI controller the static error is annihilated, but at the expense of shortening the stability region and increasing settling time. In this work, a zero static error dynamic controller for a two‐cell DC–DC buck converter is designed. To achieve zero current error, we propose a generalized scheme of a dynamic controller. Then, using nonlinear analysis and Lyapunov stability theory and bifurcation prediction tools, we prove that zero static error is achieved. The proposed controller outperforms the PI controller in terms of settling time in the presence of saturating effect during the start‐up transients. Numerical simulations in the form of time domain waveforms and bifurcation diagrams from switched circuit‐based model are presented to confirm our theoretical results. Copyright © 2010 John Wiley & Sons, Ltd.     

A wideband time‐based continuous‐time sigma‐delta modulator with 2nd order noise‐coupling based on passive elements

Embedding the time encoding approach inside the loop of the sigma‐delta modulators has been shown as a promising alternative to overcome the resolution problems of analog‐to‐digital converters in low‐voltage complementary metal‐oxide semiconductor (CMOS) circuits. In this paper, a wideband noise‐transfer‐function (NTF)‐enhanced time‐based continuous‐time sigma‐delta modulator (TCSDM) with a second‐order noise‐coupling is presented. The proposed structure benefits from the combination of an asynchronous pulse width modulator as the voltage‐to‐time converter and a time‐to‐digital converter as the sampler to realize the time quantization. By using a novel implementation of the analog‐based noise‐coupling technique, the modulator's noise‐shaping order is improved by two. The concept is elaborated for an NTF‐enhanced second‐order TCSDM, and the comparative analytical calculations and behavioral simulation results are presented to verify the performance of the proposed structure. To further confirm the effectiveness of the presented structure, the circuit‐level implementation of the modulator is provided in Taiwan Semiconductor Manufacturing Company (TSMC) 90 nm CMOS technology. The simulation results show that the proposed modulator achieves a dynamic range of 84 dB over 30 MHz bandwidth while consuming less than 25 mW power from a single 1 V power supply. With the proposed time‐based noise‐coupling structure, both the order and bandwidth requirements of the loop filter are relaxed, and as a result, the analog complexity of the modulator is significantly reduced. Copyright © 2015 John Wiley & Sons, Ltd.     

A 0.008‐mm2, 35‐μW, 8.87‐ps‐resolution CMOS time‐to‐digital converter using dual‐slope architecture

This paper presents a high resolution time‐to‐digital converter (TDC) for low‐area applications. To achieve both high resolution and low circuit area, we propose a dual‐slope voltage‐domain TDC, which is composed of a time‐to‐voltage converter (TVC) and an analog‐to‐digital converter (ADC). In the TVC, a current source and a capacitor are used to make the circuit as simple as possible. For the same reason, a single‐slope ADC, which is commonly used for compact area ADC applications, is adapted and optimized. Because the main non‐linearity occurs in the current source of the TVC and the ramp generator of the ADC, a double gain‐boosting current source is applied to overcome the low output impedance of the current source in the sub‐100‐nm CMOS process. The prototype TDC is implemented using a 65‐nm CMOS process, and occupies only 0.008 mm². The measurement result shows a dynamic range with an 8‐bit 8.86‐ps resolution and an integrated non‐linearity of ±1.25 LSB. Copyright © 2016 John Wiley & Sons, Ltd.     

Modeling of switching frequency instabilities in buck‐based DC–AC H‐bridge inverters

In this paper, the dynamical behavior of a full bridge DC–AC buck inverter controlled by fixed frequency and PWM is studied. After showing that the system can undergo both period‐doubling and Neimark–Sacker bifurcation at the fast scale (switching period) by using the exact switching model, an exact solution discrete‐time model able to predict both instability phenomena is derived. The model is obtained without making the quasi‐static approximation and it can be used to obtain the useful operation region in the multi‐dimensional design parameter space from time domain simulations in a very fast and accurate manner. Based on the study of the system, some design guidelines are provided. Copyright © 2010 John Wiley & Sons, Ltd.     

A 1‐Gbps reference‐less burst‐mode CDR with embedded TDC in a 65‐nm CMOS process

A reference‐less all‐digital burst‐mode clock and data recovery circuit (CDR) is proposed in the paper. The burst‐mode CDR includes a coarse and a fine time‐to‐digital converter (TDC) with embedded phase generator. A low‐power current‐starved inverter is employed as the delay unit of the fine TDC to acquire the high measurement resolution. A calibration method to diminish the inherent delay is used to reduce the quantization error of the recovery clock. The proposed CDR is fabricated in a 65‐nm CMOS process. Experiment results show that the CDR operates from 0.9 to 1.1 Gbps and have a 13‐bit consecutive identical digits (CIDs) tolerance.     

Selectivity and sensitivity enhancement methods for high‐data‐rate super‐regenerative receiver

This paper describes selectivity and sensitivity performance evaluations and improvement methods for an on–off keying super‐regenerative (SR) receiver. A slope‐controlled quasi‐exponential quench waveform, generated by a low‐complexity PVT‐tolerant quench generator circuit, is proposed to increase data rate and reduce the receiver 3‐dB bandwidth, thereby preventing oscillation caused by out‐of‐band injected signals and improving the receiver selectivity. The SR receiver sensitivity is also enhanced by a noise‐canceling front‐end topology with single‐ended to differential (S2D) signal converter. To exemplify these techniques, we designed an SR receiver with the proposed front‐end and quench waveform generator in a 0.18‐μm CMOS technology. Theoretical analyses and circuit simulations show 30% and 65% reduction in 3‐dB bandwidth of the SR receiver at 25 Mbps data rate by employing the proposed quench signal compared with piecewise‐linear and trapezoidal quench waveforms, respectively. Performance of the proposed front‐end is evaluated by a fast bit‐error‐rate estimation procedure, based on circuit noise simulations and statistical analyses, without the need for time‐consuming transient‐noise simulations. Accuracy of the procedure has been verified by comparing its results with transient‐noise simulations. According to the estimated bit‐error‐rate curves, the noise‐canceling topology with S2D converter enhances the SR receiver sensitivity by 9 dB. Copyright © 2017 John Wiley & Sons, Ltd.     

An oscillatory noise‐shaped quantizer for time‐based continuous‐time sigma‐delta modulators

In this paper, a new type of an oscillatory noise‐shaped quantizer (NSQ) for time‐based continuous‐time sigma‐delta modulators is presented. The proposed NSQ is composed of an oscillatory voltage‐to‐time converter and a polyphase sampler. Using Tustin's transformation method and through the approximation of the comparator gain, a linearized model of the NSQ is introduced. This way, a novel realization of the first‐ and second‐order NSQ is presented. Its implementation is based on fully passive continuous‐time filters without needing any amplifier or power consuming element. The ploy‐phase sampler inside the NSQ is based on the combination of a time‐to‐digital and a digital‐to‐time converter. The layout of the proposed NSQ is provided in Taiwan Semiconductor Manufacturing Company 0.18 μm complementary metal‐oxide‐semiconductor 1P6M technology. The verification of the proposed NSQ is done via investigating both the system level and postlayout simulation results. Leveraging the proposed NSQ in an Lth‐order time‐based continuous‐time sigma‐delta modulator enhances the noise‐shaping order up to L + 2, confirming its superior effectiveness. This makes it possible to design high performance and wideband continuous‐time SDMs with low power consumption and relaxed design complexity.     

Complete delay modeling of sub‐threshold CMOS logic gates for low‐power application

In this paper, the propagation delay of a complementary metal‐oxide semiconductor (CMOS) inverter circuit in sub‐threshold regime has been analyzed thoroughly with respect to variable loads, rise and fall time of input, device dimensions and temperature, without neglecting the significant drain induced barrier lowering (DIBL) and body bias effects. In particular, sub‐threshold slope factor and current strength have been modeled with respect to temperature, which would be efficacious for the analysis of sub‐threshold circuit as temperature plays an important role in propagation delay. Transistor stacking has also been modeled considering variation in threshold voltage, sub‐threshold slope factor and DIBL coefficient owing mainly to fluctuation in doping levels. The CMOS inverter delay model together with transistor stacking model has been incorporated in the analysis of propagation delays of NAND and NOR gates. Extensive simulations have been performed under 45 and 22 nm CMOS technology using simulation program with integrated circuit emphasis (SPICE) to ensure the correctness of the analysis. Simulation shows that this model is applicable for the analysis of digital sub‐threshold circuit in sub‐90 nm technology. Copyright © 2015 John Wiley & Sons, Ltd.     

Delay‐dependent model reduction for continuous‐time switched state‐delayed systems

This paper studies the problem of exponential H_∞ model reduction for continuous‐time switched delay system under average dwell time (ADT) switching signals. Time delay under consideration is interval time varying. Our attention is focused on the construction of the desired reduced order models, which guarantee that the resulting error systems under ADT switching signals are exponentially stable with an H_∞ norm bound. By introducing a block matrix and making use of the ADT approach, delay‐dependent sufficient conditions for the existence of reduced order models are derived and formulated in terms of strict linear matrix inequalities (LMIs). Owing to the absence of non‐convex constraints, it is tractable to construct an admissible reduced order model. The effectiveness of the proposed methods is illustrated via two numerical examples. Copyright © 2011 John Wiley & Sons, Ltd.     

A high‐order discontinuous Galerkin method with time‐accurate local time stepping for the Maxwell equations

We present an explicit numerical method to solve the time‐dependent Maxwell equations with arbitrary high order of accuracy in space and time on three‐dimensional unstructured tetrahedral meshes. The method is based on the discontinuous Galerkin finite element approach, which allows for discontinuities at grid cell interfaces. The computation of the flux between the grid cells is based on the solution of generalized Riemann problems, which provides simultaneously a high‐order accurate approximation in space and time. Within our approach, we expand the solution in a Taylor series in time, where subsequently the Cauchy–Kovalevskaya procedure is used to replace the time derivatives in this series by space derivatives. The numerical solution can thus be advanced in time in one single step with high order and does not need any intermediate stages, as needed, e.g. in classical Runge–Kutta‐type schemes. This locality in space and time allows the introduction of time‐accurate local time stepping (LTS) for unsteady wave propagation. Each grid cell is updated with its individual and optimal time step, as given by the local Courant stability criterion. On the basis of a numerical convergence study we show that the proposed LTS scheme provides high order of accuracy in space and time on unstructured tetrahedral meshes. The application to a well‐acknowledged test case and comparisons with analytical reference solutions confirm the performance of the proposed method. Copyright © 2008 John Wiley & Sons, Ltd.