An ultra low-voltage, low-power baseband-processor for UHF RFID tag

A novel ultra low-voltage, low-power baseband-processor for UHF radio frequency identification (RFID) tag is presented here. The baseband-processor is compatible with the EPC™ class-1 generation-2 (C1G2) UHF RFID protocol, and fits the requirements of ultra low-power of passive tags. Based on the analysis of the special power consumption of the tag, a new architecture is proposed. A novel scheme for generating pseudo-random numbers as well as a new method of partial-decoding is developed. Besides, other low-power techniques are also adopted for the special baseband-processor which implements complex functions, such as encoding/coding, anti-collision and authorization scheme, and reading/writing operation to EEPROM. The chip was fabricated in 0.35 μm 1P3M standard CMOS process. Experimental results show that it achieves low power operation of 3.15 μW @ 1.5 V with the core area of 1.1 mm × 0.8 mm. __________ Translated from Chinese Journal of Semiconductors, 2006, 27(10): 1866–1871 [译自: 半导体学报]     

基于无源RFID的混凝土湿度监测技术研究

湿度控制是混凝土早龄期控制开裂的重要措施,由于混凝土是有损多相复合材料,文中首先具体分析了电磁波在混凝土中的损耗,确定了标签可正常工作的基本条件,然后介绍了一种用于混凝土湿度监测的无源射频识别(RFID)传感器标签,该RFID传感器标签是基于超高频(UHF)的EPC-2通信协议,且工作于无源模式下,并具体介绍了传感器结构、接口电路和整流模块。后期实验对所设计的湿度传感器进行了性能测试,结果显示该湿度传感器具有良好的线性度和稳定性。与传统湿度测量的结构相比,所设计的无源RFID湿度传感标签具有低成本以及低功耗的特点。     

A power‐area‐efficient, 3‐band, 2‐RX MIMO,TD‐LTE receiver with direct‐coupled ADC

In this work, a power‐area‐efficient, 3‐band, 2‐RX MIMO, and TD‐LTE (backward compatible with the HSPA+, HSUPA, HSDPA, and TD‐SCDMA) CMOS receiver is presented and implemented in 0.13‐μm CMOS technology. The continuous‐time delta‐sigma A/D converters (CT ?Σ ADCs) are directly coupled to the outputs of the transimpedance amplifiers, eliminating the need of analog anti‐aliasing filters between RX front‐end and ADCs in conventional structures. The strong adjacent channel interference without low‐pass filter attenuation is handled by proper gain control. A low‐power small‐area solution for excess loop delay compensation is implemented in the CT ?Σ ADC. At 20 MHz bandwidth, the CT ?Σ ADC achieves 66 dB dynamic range and 3.5 dB RX chip noise figure is measured. A maximum of 2.4 dB signal‐to‐noise ratio degradation is measured in all the adjacent channel selectivity (ACS) and blocking tests, demonstrating the effectiveness of the strategy against the low‐pass filter removal from the conventional architecture. The receiver dissipates a maximum of 171 mW at 2‐RX MIMO mode. To our best knowledge, it is the first research paper on the design of fully integrated commercial TD‐LTE receiver. Copyright © 2014 John Wiley & Sons, Ltd.     

Adaptive impedance matching system for downlink of passive semi‐ultra wideband ultra‐high frequency radio frequency identification tag

The input impedance of ultra‐high frequency radio frequency identification tag varies with the received power on the chip. It will induce impedance mismatch between the receiver antenna and microchip, thus drastically affect the performance of communication. In this paper, a low cost and fully integrated automatic impedance matching system was presented to solve this problem. It consists of two control loops for independent control of the real and imaginary parts of impedance. The first control loop realizes resistance correction using a parallel LC tuning network, whereas the second control loop achieves reactance compensation using a series LC tuning network. In both loops, the mismatch information is detected for direct control of the variable elements, varactors, which are tuned in a sequential manner. For unambiguous control of the resistance correction, the sign of the intermediate reactance is used as a secondary control criterion to enforce operation into a stable region. The functionality of the proposed automatic matching system was verified for different input impedances of a specifically semi‐ultra wideband ultra‐high frequency radio frequency identification tag as the available input power varies. The results indicate that all matched impedances are clustered around the target impedance 50 + j0 Ω after acquisition of both loops. Copyright © 2012 John Wiley & Sons, Ltd.     

All digital folded low‐area,low‐power maximum power point tracking chip for photovoltaic energy conversion system

In this paper, we propose and implement a 12‐bit area‐efficient folded all‐digital maximum power point tracking (MPPT) chip based on gain‐adaptive perturb‐and‐observe algorithm for photovoltaic energy conversion system. Alternative to DSP or micro controller, realizing the MPPT algorithm by using ASIC can achieve higher energy conversion efficiency, lower power consumption and smaller chip area. By using gain‐adaptive perturb‐and‐observe MPPT algorithm, overall system power consumption can be reduced by overcoming the periodic perturbation issues that occur in conventional perturb‐and‐observe MPPT algorithm. The utilization of proportional integral controller allows fast and stable tracking of the maximum power point. Under high intensity sun illumination, the gain‐adaptive perturb‐and‐observe algorithm performs three times faster than the conventional perturb‐and‐observe MPPT algorithm. Under low intensity sun illumination, the gain‐adaptive perturb‐and‐observe algorithm can provide the same power conversion efficiency as the conventional perturb‐and‐observe MPPT algorithm. By using folding VLSI architecture, the MPPT algorithm can be realized with 74% chip area saving and 77% power consumption reduction. Finally, our proposed MPPT chip is implemented in TSMC0.18‐µm process, with 0.85 mm*0.79 mm chip area and 97.9% power conversion efficiency. Copyright © 2013 John Wiley & Sons, Ltd.     

满足链路时序的RFID低功耗基带处理器

提出了一种满足EPCglobal Gen2协议对链路时序规定的射频识别（RFID）标签芯片低功耗数字基带处理器的设计。该设计将全局时钟设定为反向散射频率（BLF）的二倍频率2BLF,建立基带数据处理时间和BLF的关系;并采用门控时钟、行波计数器及状态编码等技术降低基带处理器功耗。该芯片经TSMC 0.18μm RF工艺流片验证,实测结果表明,提出的基带处理器完全满足协议中关于链路时序的要求,功耗降低了22.46%,面积减少了18.03%,标签识别速率最高为96.3次/s,识别距离可达6.8 m。     

A 7.5‐μW 0.08‐mm2 single‐ended SC delta‐sigma ADC for acoustic sensor applications

This study presents an ultra‐low‐power, small‐size, 1‐bit, single‐ended, and switched‐capacitor (SC) delta‐sigma analog‐to‐digital converter (ADC) for wireless acoustic sensor nodes. This wireless sensor node has a delta‐sigma ADC that converts the sensed signal to a digital signal for convenient data processing and emphasizes the features of small size and low‐power consumption. The chip area of the delta‐sigma ADC is dominated by the capacitor; therefore, a novel common‐mode (CM) controlling technique with only transistors is proposed. This ADC achieves an extremely small size of 0.08 mm² in a 130‐nm CMOS process. The conventional operational transconductance amplifiers (OTAs) are replaced by inverters in the weak inversion region to achieve high power efficiency. At 4‐MHz sampling frequency and 0.7‐V power supply voltage, the delta‐sigma ADC achieves a 55.8‐dB signal‐to‐noise‐plus‐distortion ratio (SNDR) and a 298‐fJ/step figure‐of‐merit (FOM) in a signal bandwidth of 25 kHz, while consuming only 7.5 μW of power. Copyright © 2015 John Wiley & Sons, Ltd.     

基于RFID电子标签技术的电力监测系统

利用射频识别（radio frequency identification,RFID）技术和计算机数据管理技术,开发了一种采用射频标签识读技术的电力物资管理的新途径,并结合GPS,建立更智能化的电力监测系统,实现电力设备的智能管理模式,提升电网对重大灾情的应对能力。为此,介绍了RFID电子标签的工作原理,以及在电力系统实际应用中存在的问题和解决方法。     

基于LabVIEW的UHF RFID射频识别系统的设计

针对目前市场流行的超高频RFID识别系统成本高、制作方法复杂等问题,提出了一种基于射频读写专用芯片MagicRF M100的兼容国际标准ISO/IEC 18000-6C和EPC Class-1 Generation-2协议的UHF RFID读写器的设计方案,详细阐述了读写器的工作原理,并相应地介绍了系统软硬件设计中比较...     

900 MHZ radio‐frequency identification rectifier with optimization and reusing of electro‐static discharges protections in 180 nm digital CMOS technology

Sensitivity and electro‐static discharges (ESD) protection level are crucial parameters for any Ultra High‐Frequency (UHF) power rectifier–harvester designed for radio‐frequency identification (RFID) devices. While sensitivity limits the reading range of the interrogator‐to‐tag communication link, the requirement for an adequate protection against ESD is enforced in commercial devices connected to a printed antenna. Both resistive and capacitive parasitics of the protection circuits severely affect RF performance of the device. In the paper, a rectifier for UHF RFID embedding an ESD protection for 2 kV human‐body discharge model (HBM) level is proposed. The target of a low added parasitic capacitance is achieved by adapting the protection circuit to the RFID rectifier and reusing the ESD clamp for additional functions being mandatory in a UHF RFID front end. The layout of the ESD clamp has been optimized for minimum parasitic resistance without sacrificing the protection level. Two UHF harvesters were implemented in a 180 nm digital complementary metal‐oxide semiconductor (CMOS) technology, featuring a minimum sensitivity of ?15.5 dBm with an ESD protection level of 2 kV HBM. Copyright © 2014 John Wiley & Sons, Ltd.     

Microwave Surfing: Has your cat gone phishing?

A radio frequency identification (RFID) system has two parts: a (usually portable) reader and a tiny transponder (radio tag, RFID chip), which is embedded in or attached to the tracked object (such as a piece of baggage on an airport conveyor belt or a pet). Researchers from Vrije Universiteit in Amsterdam demonstrate in [3] how these tiny RFID tags can be used to spread malicious computer code. Since the tags have a very limited memory (typically less than 1,024 b), it had been generally assumed that they were unsuitable vectors for introducing viruses into computers connected to RFID readers [4].     

Bandwidth extension,linearity enhancement,and cost reduction techniques for continuous‐time channel‐select filters

Achieving a wide bandwidth in a conventional active‐RC filter requires large power consumption and is often accompanied by significant performance degradation. In this paper, a new structure to implement active‐RC continuous‐time filters and also a new frequency compensation scheme for the operational amplifiers that are the main building blocks of active‐RC filters are proposed. Exploiting these techniques increases the maximum possible bandwidth with lower power consumption in comparison with the conventional architectures, reduces die area, and enhances the dynamic range. The effectiveness of these methods has been verified by analysis and simulation of the conventional and proposed filters under identical conditions. Both the analytical investigations and extensive simulation results prove that the adopted techniques improve the performance of continuous‐time filters considerably in terms of bandwidth and linearity while reducing the die area. Simulations have been carried out in a standard 90‐nm CMOS process by using Advanced Design System (ADS), and the proposed filter features 11.08‐dB spurious‐free dynamic range improvement and 5.9 times bandwidth enhancement. Also, the total on‐chip capacitance is made 2.4 times smaller by using the new biquad structure. Copyright © 2016 John Wiley & Sons, Ltd.     

Power analysis for asynchronous network‐on‐chip

An asynchronous architecture is proposed to achieve a low‐power network‐on‐chip (NoC). The area of the asynchronous switch is increased by 25% as compared to the synchronous switch. However, the power dissipation of the asynchronous architecture could be decreased by up to 55%. Even though clock gating is used, the asynchronous design achieves significant power reduction of 28%. The total metal resource required to implement the asynchronous design is decreased by up to 12%. As technology advances and network density increases, the reduction in power dissipation reaches 22% for 256 IPs with the same chip size. The asynchronous butterfly fat tree (BFT) architecture dissipates the minimum power as compared to other NoC topologies. © 2013 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A CMOS voltage regulator for passive RFID tag ICs

A low‐power voltage regulator for passive RFID tag ICs is proposed in this paper. It consists of a self‐biased mutually compensated voltage reference, a low dropout (LDO) voltage regulation circuit and a power‐on‐reset (POR) circuit. It is fabricated in a commercial 0.18?µm CMOS technology and applied to a passive UHF RFID tag IC. The total quiescent current is 700 nA under a 1.8‐V supply. The output voltage of the regulator is 1.45 V with load capability of 50 µA. The temperature coefficients of the voltage reference and the output voltage are only 9 and 43 ppm/^°C, respectively. A POR signal with width pulse of 150 ns is generated for the digital part in the tag IC. Copyright © 2010 John Wiley & Sons, Ltd.     

Circuit and system design for an 860–960 MHz RFID reader front‐ends with Tx leakage suppression in 0.18 − µm CMOS technology

This paper presents an RF Front‐END for an 860–960thinspaceMHz passive RFID Reader. The direct conversion receiver architecture with the feedback structure in the RF front‐end circuit is used to give good immunity against the large transmitter leakage and to suppress leakage. The system design considerations for receiver on NF and IIP3 have been discussed in detail. The RF Front‐END contains a power amplifier (PA) in transmit chain and receive front‐end with low‐noise amplifier, up/down mixer, LP filter and variable‐gain amplifier. In the transmitter, a differential PA with a new power combiner is designed and fabricated in a 0.18‐µm technology. The chip area is 2.65 mm × 1.35 mm including the bonding pads. The PA delivers an output power of 29 dBm and a power‐added efficiency of 24% with a power gain of 20 dB, including the losses of the bond‐wires. Copyright © 2011 John Wiley & Sons, Ltd.     

Control of square-wave inverters in high-power hybrid active filtersystems

This paper presents a new control scheme for a hybrid parallel active filter (HPAF) system intended for high-power applications-up to 100 MW nonlinear loads-to meet IEEE 519 recommended harmonic standards. The active filter inverter is realized with small-rated (1%-2% of the load rating) square-wave inverters operating at the dominant harmonic frequencies. The proposed system achieves harmonic isolation at desired dominant harmonic frequencies, such as the fifth and seventh, even in the presence of supply voltage harmonic distortions. A novel method of active filter inverter DC-bus control, as proposed here, achieves power balancing by exchanging energy at the fundamental frequency and at the dominant harmonic frequency (such as the fifth). The proposed square-wave inverter-based HPAF system provides improved filtering characteristics as compared to the conventional passive filter and is expected to be cost effective for high-power nonlinear loads compared to the conventional passive filter or other active filtering solutions. The concept of harmonic isolation at dominant harmonic frequencies by square-wave inverters with the proposed control scheme is validated by simulation results     

Analysis and implementation of a fourth‐order bandpass filter for R‐wave detection of an implantable cardiac microstimulator

This paper presents an ultra‐low‐power fourth‐order bandpass operational transconductance amplifier‐C (OTA‐C) filter for an implantable cardiac microstimulator used to detect the R‐wave of intracardiac electrograms. The OTA‐C filter fabricated by TSMC 0.35‐µm complementary metal–oxide–semiconductor (CMOS) technology is operated in the subthreshold region to save power under a supply voltage of 1 V. The current cancellation technique is adopted to reduce the transconductance of the amplifier. Through this, the low‐frequency OTA‐C filter can be realized by ultra‐low transconductance with on‐chip capacitors. Direct comparison to conventional RLC ladders replaced by OTA‐C circuits shows that the method of reducing the number of OTAs further diminishes power consumption. Design issues, including ultra‐low transconductance, linearity, and noise, are also discussed. Measurement results show that the low‐voltage, low‐power filter has a bandwidth between 10 and 50 Hz, third inter‐modulation distortion of ?40 dB, dynamic range of 43 dB, and power consumption of only 12 nW. The real electrocardiography signal is fed into the bandpass filter to verify the function of signal processing with the distribution of the R‐wave. Copyright © 2012 John Wiley & Sons, Ltd.     

小型蓝牙标签天线的仿真设计

小型标签 RFID芯片的工作频率为13.56 MHz,本文主要设计了小型蓝牙标签的天线,该天线采用电感耦合的形式。用 ANSYS公司的电磁仿真软件 HFSS对小型标签天线的各种形状,厚度,层数,圈数的场强进行仿真分析和比较,做好线圈的电感匹配,并查看天线的 S参数使其频率在13.56 MHz时有较好的谐振,设计出了满足在小型标签中尺寸小,抗干扰性能强的天线,使其在13.56 MHz 时具有最好的传输性能。最后将天线安装在 RFID 芯片上后进行封装,得到成本低,实用性强,应用广泛的小型标签。结果测得标签的最远读取距离为35 cm。     

A 10 b 25 MS/s 4.8 mW 0.13 µm CMOS ADC with switched‐bias power‐reduction techniques

This paper proposes a 10 b 25 MS/s 4.8 mW 0.13 µm CMOS analog‐to‐digital converter (ADC) for high‐performance portable wireless communication systems, such as digital video broadcasting, digital audio broadcasting, and digital multimedia broadcasting (DMB) systems, simultaneously requiring a low‐voltage, low‐power, and small chip area. A two‐stage pipeline architecture optimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate, while switched‐bias power‐reduction techniques reduce the power consumption of the power‐hungry analog amplifiers. Low‐noise reference currents and voltages are implemented on chip with optional off‐chip voltage references for low‐power system‐on‐a‐chip applications. An optional down‐sampling clock signal selects a sampling rate of 25 or 10 MS/s depending on applications in order to further reduce the power dissipation. The prototype ADC fabricated in a 0.13 µm 1P8M CMOS technology demonstrates a measured peak differential non‐linearity and integral non‐linearity within 0.42 LSB and 0.91 LSB and shows a maximum signal‐to‐noise‐and‐distortion ratio and spurious‐free dynamic range of 56 and 65 dB at all sampling frequencies up to 25 MHz, respectively. The ADC with an active die area of 0.8 mm² consumes 4.8 and 2.4 mW at 25 and 10 MS/s, respectively, with a 1.2 V supply. Copyright © 2008 John Wiley & Sons, Ltd.     

电子标签的超低功耗应用设计

论文为解决RFID（无线射频识别）系统中电子标签的低功耗问题,采用了合理的硬件设计和优化的软件算法,并结合矿井下使用的人员定位系统对该设计进行了实际应用,测试结果的计算表明标签供电的两节7号电池可以使用372天的时间。该结果验证了理论设计的正确性,并为生产实践带来了经济实用性和效益性。