Optimum design of high power and high efficiency mm‐wave fundamental oscillators

A systematic method to design high power and high efficiency mm‐wave fundamental oscillators is presented. By using a linear time variant method, we first obtain the optimum conditions and show that these conditions can be significantly different for high power and high efficiency fundamental oscillation. Next, we propose a modified multistage ring oscillator with interstage passive networks to exploit the full capacity of the transistors in terms of output power or efficiency. Analytical expressions are also derived to determine the value of passive elements used in the oscillator. To verify the validity of the method, a 77‐GHz two‐stage (differential) VCO is designed in a 65‐nm CMOS process. Careful electromagnetic and circuit simulations demonstrate that the designed VCO has 2‐GHz tuning range, maximum output power of 10.5 dBm and maximum DC to RF efficiency of 24.1%. The designed VCO shows 54.8% and 108.7% improvement in terms of maximum output power and efficiency compared with a conventional cross‐coupled VCO with the same tuning range.     

1‐V continuous‐time equalizers for multi‐gigabit short‐haul optical fiber communications

Two new CMOS analog continuous‐time equalizers for high‐speed short‐haul optical fiber communications are presented in this paper. The proposed structures compensate the limited bandwidth‐length product of 1‐mm step‐index polymer optical fiber channels (45 MHz, 100 m) and have been designed in a standard 0.18‐µm CMOS process. The equalizers are aimed for multi‐gigabit short‐range applications, targeting up to 2 Gb/s through a 50‐m step‐index polymer optical fiber. The prototypes operate with a single supply voltage of only 1 V and overcome the severe limitations suffered by the widely used degenerated differential pair caused by the low supply voltage. Copyright © 2012 John Wiley & Sons, Ltd.     

A parametric convex meshfree formulation for approximating the Helmholtz solution in circular coaxial waveguide

The application of convex meshfree approximation to the time‐harmonic electromagnetic wave propagation analysis of a waveguide with non‐convex cross section such as the circular coaxial waveguide remains unsolved. This paper introduces a parametric convex meshfree formulation for the circular coaxial waveguide analysis. The present method reformulates the convex meshfree approximation on the basis of a special parametric space―an extended parametric domain. The new parametric domain ensures a one‐to‐one geometric mapping using the convex meshfree approximation and allows the convex meshfree method to be applied to the oscillatory type of Helmholtz equation for circular coaxial waveguide analysis. Both transverse electric and transverse magnetic mode studies are conducted using the present method, and results are compared with the standard bilinear finite element method. Copyright © 2014 John Wiley & Sons, Ltd.     

Low‐voltage low‐power CMOS receiver front‐end for gigabit short‐reach optical communications

This article presents a new CMOS receiver analog front‐end for short‐reach high‐speed optical communications, which compensates the limited product bandwidth length of 1‐mm step‐index plastic optical fiber (SI‐POF) channels (45 MHz · 100 m) and the required large‐diameter high‐capacitance Si PIN photodetector (0.8 mm–3 pF). The proposed architecture, formed by a transimpedance amplifier and a continuous‐time equalizer, has been designed in a standard 0.18‐µm CMOS process with a single supply voltage of only 1 V, targeting gigabit transmission for simple no‐return‐to‐zero modulation consuming less than 23 mW. Experimental results validate the approach for cost‐effective gigabit SI‐POF transmission. Comparative analysis with previously reported POF receivers has been carried out by introducing a useful figure of merit. Copyright © 2012 John Wiley & Sons, Ltd.     

Asynchronous cellular logic network as a co‐processor for a general‐purpose massively parallel array

This paper demonstrates an implementation of an asynchronous cellular processor array that facilitates binary trigger‐wave propagations, extensively used in various image‐processing algorithms. The circuit operates in a continuous‐time mode, achieving high operational performance and low‐power consumption. An integrated circuit with proof‐of‐concept array of 24×60 cells has been fabricated in a 0.35µm three‐metal CMOS process and tested. Occupying only 16×8µm² the binary wave‐propagation cell is designed to be used as a co‐processor in general‐purpose processor‐per‐pixel arrays intended for focal‐plane image processing. The results of global operations such as object reconstruction and hole filling are presented. Copyright © 2010 John Wiley & Sons, Ltd.     

A 40 M–1000 MHz 77.2‐dB spurious free dynamic range CMOS RF variable gain amplifier for digital TV tuner ICs

In this paper, a 40 M–1000 MHz 77.2‐dB spurious free dynamic range (SFDR) CMOS RF variable gain amplifier (VGA) has been presented for digital TV tuner applications. The proposed RFVGA adopts a wideband operational‐amplifier‐based VGA and a wideband buffer with differential multiple gated transistor linearization method for wideband operation and high linearity. The SFDR of the proposed RFVGA is also analyzed in detail. Fabricated in a 0.13‐µm CMOS process, the RFVGA provides 31‐dB gain range with 1‐dB gain step, a minimum noise figure of 7.5 dB at a maximum gain of 27 dB, and maximum in‐band output‐referred third‐order intercept point of 27.7 dBm, while drawing an average current of 27.8 mA with a supply voltage of 3.3 V. The chip core area is 0.54 mm × 0.4 mm. Copyright © 2014 John Wiley & Sons, Ltd.     

Preliminary results from an analog implementation of first‐order TDCNN dynamics

This work falls into the category of linear cellular neural network (CNN) implementations. We detail the first investigative attempt on the CMOS analog VLSI implementation of a recently proposed network formalism, which introduces time‐derivative ‘diffusion’ between CNN cells for nonseparable spatiotemporal filtering applications—the temporal‐derivative CNNs (TDCNNs). The reported circuit consists of an array of Gm‐C filters arranged in a regular pattern across space. We show that the state–space coupling between the Gm‐C‐based array elements realizes stable and linear first‐order (temporal) TDCNN dynamics. The implementation is based on linearized operational transconductance amplifiers and Class‐AB current mirrors. Measured results from the investigative prototype chip that confirms the stability and linearity of the realized TDCNN are provided. The prototype chip has been built in the AMS 0.35 µm CMOS technology and occupies a total area of 12.6 mm sq, while consuming 1.2 µW per processing cell. Copyright © 2010 John Wiley & Sons, Ltd.     

Low‐Noise Fully Differential Amplifiers Using JFET‐CMOS Integration Technology for Smart Sensors

In this paper, CMOS‐based low‐noise amplifiers with JFET‐CMOS technology for high‐resolution sensor interface circuits are presented. A differential difference amplifier (DDA) configuration is employed to realize differential signal amplification with very high input impedance, which is required for the front‐end circuit in many sensor applications. Low‐noise JFET devices are used as input pair of the input differential stages or source‐grounded output load devices, which are dominant in the total noise floor of DDA circuits. A fully differential amplifier circuit with pure CMOS DDA and three types of JFET‐CMOS DDAs were fabricated and their noise performances were compared. The results show that the total noise floor of the JFET‐CMOS amplifier was much lower compared to that of the pure CMOS configuration. The noise‐reduction effect of JFET replacement depends on the circuit configuration. The noise reduction effect by JFET device was maximum of about − 18 dB at 2.5 Hz. JFET‐CMOS technology is very effective in improving the signal‐to‐noise ratio (SNR) of a sensor interface circuit with CMOS‐based sensing systems. © 2008 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Function‐in‐layout: a demonstration with bio‐inspired hyperacuity chip

Below 100 nm a new scenario is emerging in VLSI design: floorplanning and function are inherently interrelated. Using mainly local connectivity, wire delay and crosstalk problems are eliminated. A new design methodology is proposed, called function‐in‐layout, that possesses: regular layout, mainly local connectivity, functional ‘parasitics’. A bio‐inspired demonstration is presented, a hyperacuity chip, with 30 ps time difference detection using 0.35 mm complementary metal‐oxide semiconductor (CMOS) technology. Copyright © 2006 John Wiley & Sons, Ltd.     

Parametric yield optimization of CMOS analogue circuits by quadratic statistical circuit performance models

A major bottleneck in the design and parametric yield optimization of CMOS integrated circuits lies in the high cost of the circuit simulations. One method that significantly reduces the simulation cost is to approximate the circuit performances by fitted quadratic models and then use these computationally inexpensive models to optimize the parametric yield. In this paper quadratic statistical circuit performance models are applied to maximize the parametric yield of CMOS analogue circuits. It is found that quadratic polynomials may not always model the circuit performances well. However, with engineering knowledge applied to identify and reduce the causes of the errors, accurate performance models and yield maximization can be achieved with a reasonably small number of circuit simulations, as illustrated through examples. Distinctions between the present method and previous applications of quadratic modelling to statistical circuit design are made.     

Design and analysis of a millimeter‐wave injection locked frequency divider with transconductance boosting technique

This paper presents a degenerated injector (mixer) with transconductance boosted by biasing the mixer transistor in the knee region of its I‐V curve, without increasing the transistor size and its parasitics. This mixer can enhance the locking range of millimeter‐wave injection‐locked frequency dividers. To compensate the degradation of mixer transconductance (conversion‐gain) due to the degeneration effect, a neutralization technique is employed. Analyses are given for locking‐range and induced phase‐noise of the proposed divider for arbitrary injection strength. It is shown that the locking‐range, as a function of injection strength, is improved by increasing the fundamental component of transconductance. Using 180‐nm CMOS technology, a 1.78‐mW divider‐by‐two is designed with free‐running frequency of 27.92 GHz, locking‐range of 51 to 59.6 GHz, and figure‐of‐merit of 4.83 (GHz/mW). EM simulation results of the proposed and conventional structure are compared, which illustrates 56% improvement in locking‐range.     

Analysis and implementation of a fourth‐order bandpass filter for R‐wave detection of an implantable cardiac microstimulator

This paper presents an ultra‐low‐power fourth‐order bandpass operational transconductance amplifier‐C (OTA‐C) filter for an implantable cardiac microstimulator used to detect the R‐wave of intracardiac electrograms. The OTA‐C filter fabricated by TSMC 0.35‐µm complementary metal–oxide–semiconductor (CMOS) technology is operated in the subthreshold region to save power under a supply voltage of 1 V. The current cancellation technique is adopted to reduce the transconductance of the amplifier. Through this, the low‐frequency OTA‐C filter can be realized by ultra‐low transconductance with on‐chip capacitors. Direct comparison to conventional RLC ladders replaced by OTA‐C circuits shows that the method of reducing the number of OTAs further diminishes power consumption. Design issues, including ultra‐low transconductance, linearity, and noise, are also discussed. Measurement results show that the low‐voltage, low‐power filter has a bandwidth between 10 and 50 Hz, third inter‐modulation distortion of ?40 dB, dynamic range of 43 dB, and power consumption of only 12 nW. The real electrocardiography signal is fed into the bandpass filter to verify the function of signal processing with the distribution of the R‐wave. Copyright © 2012 John Wiley & Sons, Ltd.     

Characteristics of a two‐dimensional integrated magnetic sensor for position sensing and motor control

Two‐dimensional integrated magnetic sensors for position sensing were designed and fabricated with the standard 0.35‐µm CMOS process on silicon. One such type is the n‐type Hall sensor that uses an inversion layer under the gate oxide of the MOSFET. The Hall sensors were arrayed (64 × 64), and the control digital circuits and output amplifier were also integrated into the same chip. ‘One pixel’ was 50 × 50 µm, and the entire chip was 4.9 × 4.9 mm. The sensitivity of one of these sensors was 2.7 mV/(mA·kG). The two‐dimensional magnetic flux distribution was measured from the 5‐mm diameter Nd–Fe–B rare‐earth permanent magnet. About 42 s was required to measure one frame. The position of the magnet could be detected with the fabricated sensors. Magnetic sensors using an inversion layer in MOSFETs are useful for position sensing systems, but their noise characteristics, such as poor sensitivity, should be improved. © 2006 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Global modeling of nonlinear circuits using the finite‐difference Laguerre time‐domain/alternative direction implicit finite‐difference time‐domain method with stability investigation

This paper describes a new unconditionally stable numerical method for the full‐wave physical modeling of semiconductor devices by a combination of the finite‐difference Laguerre time‐domain (FDLTD) and alternative direction implicit finite‐difference time‐domain (ADI‐FDTD) approaches. The unconditionally stable method by using FDLTD scheme for the electromagnetic model and semi‐implicit ADI‐FDTD approach for the active model leads to a significant decrease in the full‐wave simulation time. Numerical simulations of an example transistor and a power amplifier show the efficiency of presented method for the full‐wave simulation of mm‐wave active circuits. Copyright © 2012 John Wiley & Sons, Ltd.     

An analog cell and its applications in analog signal processing

This paper presents a straightforward current‐mode CMOS squarer circuit. The proposed circuit exploits the square‐law characteristic of MOS transistor in saturation region. The squarer circuit is then used to implement multiplier and exponential functions. To demonstrate the method, circuits are designed in 0.35 µm CMOS process, using single 3.3 V supply. HSPICE simulations, with level 49 model parameters, confirm the operation of the proposed CMOS circuits. Copyright © 2010 John Wiley & Sons, Ltd.     

A rail-to-rail ultra-wide bandwidth hybrid supply modulator for 5G applications with envelope tracking techniques

A rail-to-rail ultra-wide bandwidth hybrid supply modulator for 5G applications is presented in this paper. The proposed supply modulator has 600-MHz bandwidth, which is the widest available bandwidth today. The hybrid supply modulator uses envelope tracking (ET) technique to achieve optimal efficiency. This circuit achieves high efficiency with wide bandwidth by combining the linear amplifier (LA) and the switching converter. The optimal size of the LA output stage provides a good tracking ability. The proposed hysteresis window circuit uses the simplified number of MOSFET that reduces the chip area and increases the efficiency of the overall system. This chip has been fabricated in TSMC 90-nm CMOS processes, and the maximum tracking ability can reach to 600-MHz sine wave. The output voltage range of the sine wave is from 0.19 to 0.79 V. The maximum load current is 122 mA. The proposed supply modulator is suitable for 5G applications. The chip area is 0.87 mm × 0.87 mm.     

CMOS digitally programmable quadrature oscillators

CMOS digitally programmable quadrature oscillators based on digitally controlled current followers and voltage followers are proposed. The proposed designs provide the advantage of programmability similar to the operational transconductance amplifier‐based oscillators while offering improved linearity. In mixed analog/digital systems, the digital tuning feature allows direct interfacing with the digital signal processing part. Novel realizations that provide both voltage‐mode and current‐mode quadrature sinusoidal signals are presented. Employing only grounded capacitors the designs achieve independent control of the frequency and condition of oscillation that can be tuned digitally. Experimental results obtained from a 0.35 µm CMOS chip fabricated using standard CMOS process are given. Copyright © 2008 John Wiley & Sons, Ltd.     

Recent Progress in Neural Probes Using Silicon MEMS Technology

Extracellular recordings from the brain are the basis for the fundamental understanding of the complex interaction of electrical signals in neural information transfer. Going beyond wire electrodes and bundles of electrode wires such as tetrodes, multielectrode arrays based on silicon technologies are receiving growing attention, since they enable a pronounced increase in the number of recording sites per probe shaft. In this paper, recent innovations contributed by the authors to the development of probe arrays based on microelectromechanical system (MEMS) technologies within the EU‐funded research project NeuroProbes are described. The resulting structures include passive electrode arrays based on single‐shaft and four‐shaft probes comprising nine planar electrodes per shaft with lengths of up to 8 mm. Further, active probe arrays with complementary metal–oxide–semiconductor (CMOS) circuitry integrated on the probe shaft, enabling the arrangement of 188 electrodes in two columns along a 4‐mm‐long probe shaft with an electrode pitch of only 40 µm, are described. These active probes were developed for an electronic depth control. Further, the paper reports assembly technologies for combining the probe arrays with highly flexible ribbon cables. Applications of the probes in in vivo experiments are summarized. © 2010 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Analysis and optimization of a novel CMOS multiplier

A novel CMOS voltage multiplier is proposed which is based on MOS transistors in the saturation region and uses a resistor load. A pencil‐and‐paper optimized design procedure and a detailed analysis of second‐order non‐idealities which affect the multiplier core are given. The circuit has been designed with a 1.2 µm CMOS process setting a 3 V power supply and simulations have been performed to validate results. Copyright © 2001 John Wiley & Sons, Ltd.     

Development of radio frequency transmitters including on‐chip antenna for intelligent human sensing systems

This paper presents the essentials of the development of an integrated smart microsensor system that has been developed to monitor the motion and vital signs of humans in various environments. Integration of RF transmitter technology with complementary metal‐oxide‐semiconductor/micro electro mechanical systems (CMOS/MEMS) microsensors is required to realize wireless smart microsensors for the monitoring system. Sensors for the measurement of body temperature, perspiration, heart rate (pressure sensor), and motion (accelerometers) are candidates for integration on the wireless smart microsensor system. In this paper, the development of radio frequency transmitter (RF) that will be integrated on wireless smart microsensors is presented. A voltage controlled RF‐CMOS oscillator (VCO) has been fabricated for the 300‐MHz frequency band applications. Also, spiral inductors for an LC resonator and an integrated antenna have been realized with a CMOS‐compatible metallization process. The essential RF components have been fabricated and evaluated experimentally. The fabricated CMOS VCO showed a conversion factor from voltage to frequency of about 81 MHz/V. After matching the characteristic impedance (50 Ω) of the on‐chip integrated antenna and the VCO output, more than 5 m signal transmission from the microchip antenna has been observed. The transmitter showed remarkable improvement in transmission power efficiency by correct matching with the microchip antenna. Essential technologies of the RF transmitter for the wireless smart microsensors have been successfully developed. Also, for the 300‐MHz band application, the integrated RF transmitter, with the CMOS oscillator and the on‐chip antenna, has been successfully demonstrated for the first time. Copyright © 2007 Institute of Electrical Engineers of Japan© 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.