A 0.1 to 2.7‐GHz SOI SP8T antenna switch adopting body self‐adapting bias technique for low‐loss high‐power applications

A low‐loss high‐power single‐pole 8‐throw antenna switch adopting body self‐adapting bias technique in a 0.18‐μm thick‐film partially depleted silicon‐on‐insulator complementary metal‐oxide‐semiconductor process is implemented for multimode multiband cellular applications. A topology with symmetric port design is developed. We employ the body‐contacted field‐effect transistor to handle high power level and obtain low harmonic distortion. However, the conventional bias method for body‐contacted field‐effect transistor leads to poor insertion loss (IL), serious imbalanced voltage division, and large die size. Therefore, a new body self‐adapting bias scheme is adopted to improve the IL and power handling capability with die area reward by removing the employment of extra biasing resistor and voltage supply at the body. The presented silicon‐on‐insulator antenna switch utilizing the new body bias strategy reveals similar harmonic performance as a conventional switch version, thanks to the analogous DC bias to the gate and body, while it exhibits effectively lower IL, imbalanced voltage division, and die area. The measured IL and 0.1‐dB compression point (P_?0.1dB), at 1.9/2.7 GHz, are roughly 0.52/0.82 dB and 39.2/36.9 dBm, respectively. The overall IL and P_?0.1dB are apparently improved by approximately 0.05 to 0.13 dB and 0.5 to 0.8 dBm compared with the conventional version.     

A new efficient SC integrator scheme for high‐speed low‐power applications

A new solution to implement efficient switched‐capacitor (SC) integrators is presented. In the proposed scheme, voltage buffers are opportunely introduced in order to prevent direct connection between the output and the capacitive feedback network of the circuit that characterizes classical SC integrator topologies during the charge transfer phase. Design guidelines to optimize the settling performances of the proposed circuit are also given. To demonstrate the possible advantages of the new solution, the proposed integrator is designed in a commercial 0.35?µm CMOS technology. It is shown that compared with classical SC integrator topologies, the proposed configuration allows a significant improvement of the integrator speed to be achieved for a given power budget. Copyright © 2010 John Wiley & Sons, Ltd.     

Design criterion for high‐speed low‐power SC circuits

The settling behavior of switched‐capacitor (SC) circuits is investigated in this paper. The analysis is performed for typical SC circuits employing two‐stage Miller‐compensated operational amplifiers (op‐amps). It aims to evaluate the real effectiveness of the conventional design approach for the optimization of op‐amp settling performances. It is demonstrated that the classical strategy is quite inaccurate in typical situations in which the load capacitance to be driven by the SC circuit is small. The presented study allows a new settling optimization strategy based on an advanced circuit model to be defined. As shown by design examples in a commercial 0.35‐ µm CMOS technology, the proposed approach guarantees a significant settling time reduction with respect to the existing settling optimization strategy, especially in the presence of small capacitive loads to be driven by the SC circuit. Copyright © 2010 John Wiley & Sons, Ltd.     

A low‐power technique for high‐resolution dynamic comparators

A low‐power technique for high‐resolution comparators is introduced. In this technique, p‐type metal‐oxide‐semiconductor field‐effect transistors are employed as the input of the latch of the comparator just like the input of the preamplifier. The latch and preamplifier stages are activated in a special pattern using an inverter‐based controller. Unlike the conventional comparator, the preamplification delay can be set to an optimum low value even if after the preamplification, the output voltages is less than n‐channel metal‐oxide semiconductor voltage threshold. As a result, the proposed comparator reduces the power consumption significantly and enhances the speed. The speed and power benefits of the proposed comparator were verified using analytical derivations, PVT corners, and post layout simulations. The results confirm that the introduced technique reduces the power consumption by 60%, also, provides 57% better comparison speed for an input common mode voltage (V_cm) range of 0‐Vdd/2.     

Gate‐level body biasing technique for high‐speed sub‐threshold CMOS logic gates

An efficient technique for designing high‐performance logic circuits operating in sub‐threshold region is proposed. A simple gate‐level body biasing circuit is exploited to change dynamically the threshold voltage of transistors on the basis of the gate status. Such an auxiliary circuit prepares the logic gate for fast switching while maintaining energy efficiency. If 200 aJ is the target total energy per operation consumption, a two input NAND (NOR) gate designed as described here shows a delay reduction between 20% (16%) and 40% (48%), with respect to previously proposed sub‐threshold approaches. Copyright 2012 John Wiley & Sons, Ltd.     

Automating the sizing of transistors in CMOS gates for low‐power and high‐noise margin operation

This paper presents an automatic method for sizing the transistors in CMOS gates. The method utilizes a feedback control system to efficiently optimize the transistor sizes in small and large fan‐in gates, with the primary goal of enhancing noise robustness (as characterized by the static noise margin). The gates retain their robustness under threshold‐voltage variations over a range of supply voltages. The optimized gates not only expend reduced power and energy, but also take up less area than the conventional ones. These multi‐faceted gains, however, do incur some performance loss. Copyright © 2014 John Wiley & Sons, Ltd.     

Low‐power and low‐noise complementary metal oxide semiconductor distributed amplifier using the gain‐peaking technique

This paper presents an improved topology for ultra‐low‐power complementary metal oxide semiconductor (CMOS) distributed amplifier (DA) based on modified folded cascode gain cells. The proposed CMOS‐DA can be applicable in low‐supply‐voltage applications, because of the use of folded gain cell's structure. The proposed DA decreases power consumption by employing the forward body biasing network, while maintains high gain. By using a gain‐peaking inductor at the gate of the transistor, the proposed DA structure achieved to the gain flatness in high frequencies while the bandwidth is improved as well. In addition, employing RC network at the body terminal improves the noise performance of the proposed DA. The DA architecture consists of three amplification stages. Detailed analysis is provided for the proposed folded cascode DA. According to the post‐layout simulation results of the proposed amplifier using a 0.13‐µm CMOS process, DA achieves power gain of 17.3 ± 0.8 dB in bandwidth of 14.5 GHz, a good input third‐order intercept point (IIP3) of +5.5 dBm. The minimum noise figure is 1.8–5 dB, and input and output return losses are less than −11.5 dB and −10 dB, respectively, and the proposed structure consumes 12 mW from a 0.5 V voltage supply. Copyright © 2016 John Wiley & Sons, Ltd.     

Low‐leakage sub‐threshold 9 T‐SRAM cell in 14‐nm FinFET technology

A novel sub‐threshold 9 T Static Random Access Memory (SRAM) cell designed and simulated in 14‐nm FinFET technology is proposed in this paper. The proposed 9 T‐SRAM cell offers an improved access time in comparison to the 8 T‐SRAM cell. Furthermore, an assist circuit is proposed by which the leakage current of the proposed SRAM cell is reduced by 20% when holding ‘0’ and an equal leakage current during hold ‘1’ in comparison to the 8 T‐SRAM cell. The proposed circuit improves the access time by 40% in comparison to the 8 T‐SRAM cell without any degradation in write and read noise margins, as well. The maximum operating frequency of the proposed SRAM cell is 1.53 MHz at V_DD = 270 mV. Copyright © 2016 John Wiley & Sons, Ltd.     

Low‐power,low‐area preamplifier for ultra high‐speed multi‐channel optical communication system

A novel circuit technique was applied to the design of a preamplifier for ultra high‐speed short‐distance parallel optical communication system in standard 180‐nm CMOS technology. This circuit is featured by low power, low area as well as high gain bandwidth product, and suited for applications in low‐cost process. The restraint on voltage headroom as bottleneck in traditionally adopted regulated cascode configuration has been fundamentally analyzed and lifted by feed‐forward common gate stage to achieve high gain bandwidth product under limited f_T and strict power restriction. Complex poles were carefully assigned to further attain bandwidth extension without sacrifice on power, noise, and chip area. No additional peaking techniques and subsequent gain‐boosting stages are adopted, which makes the design simple and favorable in low‐cost high‐density multi‐channel optical communication system. The preamplifier provides a trans‐impedance gain of up to 52 dBΩ and a 3‐dB bandwidth of 8.4 GHz. Operating under a 1.8‐V supply, the power dissipation is 8 mW, and the chip area is only 0.075×0.08 mm. The measured average input‐referred noise–current spectral density is . Copyright © 2011 John Wiley & Sons, Ltd.     

An accurate power delivery system (PDS) design methodology for high‐speed digital systems

The trend in high‐speed digital circuits is to increase speed and density and to operate at lower voltage. This fast increase in the switching speed combined with the decrease of the operating voltage causes the allowable absolute voltage variations to decrease, which makes the PDS design a more challenging task than ever. Moreover, the complex 3D nature of the modern PDS causes it to be more sensitive to capacitors' placement as well as capacitance value. In this paper, we introduce an efficient complete solution for the design of high‐speed digital PDS. This solution (a) takes the effects of the decoupling capacitor placement into consideration through a 3D electromagnetic simulation of the PDS, (b) defines a more‐realistic PDS design target, and (c) presents a clear capacitor value selection methodology. Finally, we applied our methodology to an industrial test case, compared its results with that of industrial design, and showed its advantages. Copyright © 2010 John Wiley & Sons, Ltd.     

Optimum design approach for low‐speed,high‐torque permanent magnet motors

This paper presents an optimum design approach for low‐speed, high‐torque permanent magnet motors. The approach is divided into two steps: the first consists of the rough estimation of torque by linear analysis, and the second the optimization of the motor configuration by nonlinear FEM analysis. Under restricted dimensional specifications and electrical requirements, a 16‐pole, 18‐coil permanent magnet motor with a rating of 600 Nm and 300 rpm was designed and constructed. © 2001 Scripta Technica, Electr Eng Jpn, 135(4): 52–63, 2001     

A novel,low‐complexity,high‐speed envelope detector and its applications

A compact and effective transmission envelope detector (TED), which can detect whether the absolute amplitude of an input differential signal is larger than a threshold or not, is proposed. The TED has been demonstrated to be applicable for received signal strength indicator circuit in wireless communication receivers or power management systems, and mode‐control circuit in bidirectional optical transceivers. Implemented in a 0.18 µm CMOS technology, the TED has a response time of 210 ps at 5 Gbps, occupies an active area of 0.05 mm², and consumes 1 mA from 1.8 V supply. Copyright © 2011 John Wiley & Sons, Ltd.     

Charge‐sharing read port with bitline pre‐charging and sensing scheme for low‐power SRAMs

In this paper, we present our decoupled differential read (DDR) port and bitline (BL) pre‐charging scheme. The proposed scheme allows the charge sharing between bitlines during the read operation. DDR port isolates the internal nodes, thus improves the read static noise margin and allows the subthreshold operation. BLs are not pre‐charged to full V_DD. Read port is designed such that for the read ‘1’ operation, BL shares its charge with BLB, and for read ‘0’ operation, BL is charged toward V_DD and BLB is discharged to the ground. The proposed non‐V_DD BL pre‐charging and the charge‐sharing mechanism provide substantial read power savings. Virtual power rail is used to suppress the BL leakages. A dynamic voltage level shifting pre‐amplifier is used that shifts both BLs to the middle voltage and amplifies the voltage difference. Single‐ended write driver is also presented that only conditionally charges the write BL. The proposed 10‐transistor static random access memory cell using DDR provides more than 2 times read static noise margin, ~72% read power savings, and ~40% write power savings compared with the conventional six‐transistor static random access memory. Copyright © 2016 John Wiley & Sons, Ltd.     

Write-enhanced and radiation-hardened SRAM for multi-node upset tolerance in space-radiation environments

As transistor feature size is scaling down, the probability of charge sharing in a space-radiation environment increases because of the reduced distance between adjacent transistors. The single-event multiple-node upset (SEMNU) caused by charge sharing is a major source of data errors in high-density static random-access memory (SRAM). In this paper, a radiation-hardened SRAM using polarity hardening is proposed. Compared to other cells (RHPD-12T, RSP14T, SEA14T, We-Quatro, QUCCE12T, SARP12T, SIS10T, and 12T), the proposed RHC-14T cell saves 8.47%, 91.34%, 162.71%, -20.63%, −20.50%, 113.18%, 63.27%, and 20.60% of the read-delay time and 7.96%, 66.17%, 68.16%, 57.71%, 22.39%, 12.44%, 1,010.45%, and 13.43% of the write-delay time, respectively. Moreover, this excellent performance entails only minimal power consumption. The proposed cell can work well in the radiation-intensive space environment.     

Design of high‐speed low‐power parallel‐prefix adder trees in nanometer technologies

This paper presents a novel approach to design high‐speed low‐power parallel‐prefix adder trees. Sub‐circuits typically used in the design of parallel‐prefix trees are deeply analyzed and separately optimized. The modules used for computing the group propagate and generate signals have been designed to improve their energy‐delay behavior in an original way. When the ST 45 nm 1 V CMOS technology is used, in comparison with conventional implementations, the proposed approach exhibits computational delay with mean value and standard deviation up to 40% and 48% lower and achieves energy consumption with mean value and standard deviation up to 57% and 40% lower. A 32‐bit Brent‐Kung tree made as proposed here reaches a computational delay lower than 165 ps and dissipates 147.4fJ on average. Copyright © 2013 John Wiley & Sons, Ltd.     

A novel low‐power receiver topology for RF and microwave applications

A novel low‐power receiver topology for radio‐frequency and microwave applications is presented. The proposed solution exploits a simple connection between the low‐noise amplifier and the subsequent mixer, which is realized by means of a high‐value resistor and a current mirror, achieving low noise and high linearity performance with an extremely low power consumption. The criteria for its optimal design are derived in order to accomplish the main trade‐offs among noise figure (NF), linearity, and current consumption performance. As a case of study, the new topology has been designed in the case of I/Q direct conversion receiver for IEEE 802.15.4 standard (ZigBee) applications at 2.45 GHz. The receiver exhibits a NF of 8.7 dB, 50Ω input impedance, a voltage gain of 26 dB, an input‐referred third‐order intercept point of ?13 dBm, and a power consumption of 8.6 mW, which represent one of the best performance trade‐offs obtained in the literature. Copyright © 2008 John Wiley & Sons, Ltd.     

Digitally‐assisted constant‐on‐time dynamic‐biasing technique for bandwidth and slew‐rate enhancement in ultra‐low‐power low‐dropout regulator

A digitally‐assisted constant‐on‐time dynamic‐biasing (COT‐DB) technique has been proposed to enable significant enhancement in dynamic performances, while the average current consumption can be kept to ultralow level. This dynamic‐biasing technique has a predefined magnitude and duration on biasing current boost, which is beneficial to estimate power budget in systems with finite energy source. The proposed technique has been applied to a low‐dropout regulator (LDO) to demonstrate the effectiveness. Experimental results show that significant improvements in settling times during load‐transients and line‐transients are as much as 880×, while the current consumption is only 1.02 μA. In fact, for the same dynamic performances, the average current consumption of LDO with COT‐DB technique can be as low as 0.39% of the LDO with heavy static biasing. The digitally‐assisted implementation of the technique also allows robust augmentation of the technique onto almost all analog systems. Copyright © 2015 John Wiley & Sons, Ltd.     

Technologies and applications of Al‐free high‐power laser diodes

We report high‐power technologies in 0.8‐µm Al‐free InGaAsP/InGaP laser diodes. To realize the high‐power operation, the improvement of catastrophic optical mirror damage (COMD) power density level is required. In addition to the use of low surface recombination velocity of Al‐free materials, optimization of waveguide thickness in broad waveguide structure with tensile‐strained barriers and current blocking structure near facets has led to high COMD power density level. Highly stable operation of Al‐free laser diodes with these structures has been obtained over 2500 hours at 2 W from a stripe width of µm. Applications of high‐power laser diodes are also described. © 2006 Wiley Periodicals, Inc. Electr Eng Jpn, 158(1): 53–59, 2007; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20286     

Low‐power quadrature generators for body area network applications

This paper presents different alternatives for the implementation of low‐power monolithic oscillators for wireless body area networks and describes the design of two quadrature generators operating in the 2.4‐GHz frequency range. Both implementations have been designed in a 90‐nm Complementary Metal‐Oxide Semiconductor (CMOS) technology and operate at 1 V of supply voltage. The first architecture uses a voltage‐controlled oscillator (VCO) running at twice the desired output frequency followed by a divider‐by‐2 circuit. It experimentally consumes 335 μW and achieves a phase noise of ?110.2 dBc/Hz at 1 MHz. The second architecture is a quadrature VCO that uses reinforced concrete phase shifters in the coupling path for phase noise improvement. Its power consumption is only 210 μW, and it obtains a phase noise of ?111.9 dBc/Hz at 1 MHz. Copyright © 2011 John Wiley & Sons, Ltd.     

A battery charger with maximum power point tracking function for low‐power photovoltaic system applications

A battery charger with MPPT function for low‐power PV system applications is presented in this study. For effective miniaturization, the battery charger is designed with high‐frequency operation. Some current‐sensing techniques are studied, and their MPPT implementation is compared. A battery charging method is also designed to prolong battery lifetime without the use of battery current sensors. The operation principles and design considerations of the proposed PV charger are analyzed and discussed in detail. A laboratory prototype is implemented and tested to verify the feasibility of the proposed scheme. Experimental results show that high MPPT accuracy and conversion efficiency can be simultaneously achieved under high‐frequency operation. Copyright © 2010 John Wiley & Sons, Ltd.