Mobility profiles in short and narrow GaAs MESFET channels

Gate-voltage-dependent mobility profiles in long-, short-, wide-, and narrow-channel WN_x-BPLDD (buried p-type buffer lightly doped drain region) GaAs MESFETs have been determined (L_G =10, 4, 2, 1, 0.8, 0.5, 0.3 μm, W_G=20 μm; W_G-100, 40, 20, 10, 4, 2 μm, L _G=0.5 μm). The mobility mainly depends on the channel width, while the gate length has much less influence. Thus, using proper gate dimensions the channel mobility can be tuned. The highest drift mobility values agree quite well with the measured Hall mobilities. Mobility profiles of large-area MESFETs are probably degraded by the WN _x-gate fabrication process. Injected excess charges at gate length below 0.5 μm distorts the mobility evaluations     

On the pseudo-subthreshold characteristics ofpolycrystalline-silicon thin-film transistors with large grain size

A two-dimensional nonplanar device simulator for polycrystalline-silicon thin-film transistors (poly-Si TFTs) was developed, in which the influence of trapped charges and carrier scattering within the grain boundary region are incorporated into Poisson's equations and drift-diffusion current formulations, respectively. With this simulator, the I-V characteristics of poly-Si TFT devices can be characterized. TFTs in polycrystalline silicon were fabricated to test the simulator. Special attention was paid to the conduction mechanism in poly-Si TFTs with large grain size. A concept called the pseudo-subthreshold region is presented to explain the observed behavior. The key factors affecting the pseudosubthreshold slope were investigated and elucidated using the simulator     

Characteristics of field-induced-drain (FID) poly-Si TFTs with highon/off current ratio

The characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) with a field-induction-drain (FID) structure using an inversion layer as a drain are investigated. The FID structure not only reduces the anomalous leakage current, but also maintains a high on current. An off current of 1.5 pA/μm and an on/off current ratio of 10⁷ (V_d=10, V_g =-20 V) are successfully obtained. These characteristics result from good junction characteristics between the p channel and n⁺ inversion layer. Reducing the threshold voltage of the FID region allows a simple circuit configuration for the FID TFTs     

Comparison of shallow trench and LOCOS isolation for hot-carrierresistance

Hot-carrier stresses were performed on n-MOS transistors with LOCOS and shallow trench isolation. For transistors stressed under the different damage creation conditions, no discernible difference in lifetimes was found for devices down to W/L=3/0.45 μm. It is shown, however, that the edge of the trench isolation (0.1 μm wide) is more sensitive to hot carrier effects, having a lifetime up to four times less than the center of the channel. For devices with a W/L ratio of two or less, this could prove problematic. It could also have repercussions for transistors under high-gate-field (Fowler-Nordheim) conditions     

Dispersion-shifted dual-shape core fibers. Optimization based onspot size definitions

Design features, for very low bend and splice losses, in dispersion-shifted dual-shape core (DSC) single-mode fibers are obtained in terms of characteristic mode spot sizes W¯ responsible for splice loss, and W_∞ responsible for bend loss. Dual-shape core fiber designs are given with W¯_∞/W lying between 1.16 and 1.33 while maintaining the mode spot size between 4 and 5 μm at the operating wavelength of 1550 nm. With this design goal it is shown that bending loss would be lower in a step-index than in a graded-index DSC fiber. Further, conventional single clad step-index or triangular-index dispersion-shifted fibers are seen to have higher bending loss than well-designed DSC fibers     

High performance low-temperature poly-Si n-channel TFTs for LCD

High-performance poly-Si TFTs were fabricated by a low-temperature 600°C process utilizing hard glass substrates. To achieve low threshold voltage (V_TH) and high field-effect mobility (μ_FE), the conditions for low-pressure chemical vapor deposition of the active layer poly-Si were optimized. Effective hydrogenation was studied using a multigate (maximum ten divisions) and thin-poly-Si-gate TFTs. The crystallinity of poly-Si after thermal annealing at 600°C depended strongly on the poly-Si deposition temperature and was maximum at 550-560°C. The V_TH and μ_FE showed a minimum and a maximum, respectively, at that poly-Si deposition temperature. The TFTs with poly-Si deposited at 500°C and a 1000-Å gate had a V _TH of 6.2 V and μ_FE of 37 cm²/V-s. The high-speed operation of an enhancement-enhancement type ring oscillator showed its applicability to logic circuits. The TFTs were successfully applied to 3.3-in.-diagonal LCDs with integration of scan and data drive circuits     

Doubly strainedIn0.41Al0.59As/n+-In0.65Ga0.35As HFET with high breakdown voltage

An In_0.41Al_0.59As/n⁺-In_0.65 Ga_0.35As HFET on InP was designed and fabricated, using the following methodology to enhance device breakdown: a quantum-well channel to introduce electron quantization and increase the effective channel bandgap, a strained In_0.41Al_0.59As insulator, and the elimination of parasitic mesa-sidewall gate leakage. The In_0.65Ga_0.35As channel is optimally doped to N_D=6×10¹⁸ cm^-3. The resulting device (L_g=1.9 μm, W_g =200 μm) has f_t=14.9 GHz, f_max in the range of 85 to 101 GHz, MSG=17.6 dB at 12 GHz V_B=12.8 V, and I_D(max)=302 mA/mm. This structure offers the promise of high-voltage applications at high frequencies on InP     

A new polycrystalline silicon TFT with a single grain boundary inthe channel

A new excimer laser annealing method, which results in large lateral polysilicon grains exceeding 1.5 μm, has been proposed and polycrystalline silicon thin film transistors (poly-Si TFTs) with a single grain boundary in the channel have been successfully fabricated. The proposed method employs a lateral grain growth phenomenon obtained by excimer laser irradiation on an amorphous silicon layer with pre-patterned aluminum film. The aluminum patterns act as a masking layer of the incident laser beam for the selective melting of the amorphous silicon layer. Uniform and large grains are obtained near the edge of the aluminum patterns. When two aluminum patterns are separated by a 2 μm space, the solidified region (i.e., poly-Si channel) exhibits a single grain boundary. The n-channel poly-Si TPT fabricated by the proposed method shows considerably improved I-V characteristics, such as high field effect mobility exceeding 240 cm²/Vs     

A semi-empirical model for the field-effect mobility ofhydrogenated polycrystalline-silicon MOSFETs

The quantitative relationship between field-effect mobility (μ _FE) and grain-boundary trap-state density (N_t ) in hydrogenated polycrystalline-silicon (poly-Si) MOSFETs is investigated. The focus is on the field-effect mobility in MOSFETs with N_t 1×10² cm^-2. It is found that reducing N_t to as low as 5×10¹¹ cm^-2 has a great impact on μ_FE. MOSFETs with the N_t of 4.2×10¹¹ cm^-2 show an electron mobility of 185 cm²/V-s, despite a mean grain size of 0.5 μm. The three principal factors that determine μ_FE, namely, the low-field mobility, the mobility degradation factor, and the trap-state density N_t are clarified     

A new technique for measuring MOSFET inversion layer mobility

An experimental technique for accurately determining both the inversion charge and the channel mobility μ of a MOSFET is presented. With this new technique, the inversion charge is measured as a function of the gate and drain voltages. This improvement allows the channel mobility to be extracted independent of drain voltage V_DS over a wide range of voltages (V_DS=20-100 mV). The resulting μ(V_GS) curves for different V_DS show no drastic mobility roll-off at V _GS near V_TH. This suggests that the roll-off seen in the mobility data extracted using the split C- V method is probably due to inaccurate inversion charge measurements instead of Coulombic scattering     

Reduction of channel hot-electron-generated substrate current insub-150-nm channel length Si MOSFET's

Channel hot-electron-generated substrate currents were measured in MOSFET devices with channel lengths down to 0.09 μm, and a family of characteristic plots of substrate current, normalized to drain current, I_SUB/I_D, rather than (V _DS-V_DSAT)^-1 was obtained. For channel lengths greater than 0.5 μm, the characteristics are independent of channel length. For channel lengths in the range of 0.15 μm, the characteristics are independent of channel length. For channel lengths in the range of 0.15 μm, the normalized substrate current at constant V_DS increases with decreasing channel length. However, as the channel length is decreased below 0.15 μm, a decrease of the normalized substrate current is observed. The decrease is larger at 77 K than at 300 K. This decrease accompanies the onset of electron velocity overshoot over a large portion of the channel. It is suggested that the decrease is due either to a decrease of carrier energy because energy relaxation and transit times become comparable, to a relative decrease of the carrier population in the channel, or to both     

High-performance highly strainedGa0.23In0.77As/Al0.48In0.52As MODFET's obtained by selective and shallow etch guide recesstechniques

Record high f_TL_g products of 57 and 46 GHz-μm have been achieved in Ga_1-x In_x As/AlInAs MODFETs with a strain compensated channel of x=0.77 and a lattice-matched channel of x=0.53, respectively. Although g_m as high as 950 mS/mm has been obtained by conventional deep recess for the gate, these latter devices show a prominent kink effect which lowers f_T and the voltage gain. By limiting the depth of final nonselective recess etch to 3 nm with the help of selective step etches, f_T as high as 47 GHz and g_m as high as 843 mS/mm have been achieved for MODFETs with x=0.77 and L_g=1.1 μm     

High-performance devices for a 0.15-μm CMOS technology

Devices have been designed and fabricated in a CMOS technology with a nominal channel length of 0.15 μm and minimum channel length below 0.1 μm. In order to minimize short-channel effects (SCEs) down to channel lengths below 0.1 μm, highly nonuniform channel dopings (obtained by indium and antimony channel implants) and shallow source-drain extensions/halo (by In and Sb preamorphization and low-energy As and BF₂ implant were used. Maximum high V _DS threshold rolloff was 250 mV at effective channel length of 0.06 μm. For the minimum channel length of 0.1 μm, the loaded (FI=FO=3, C=240 fF) and unloaded delays were 150 and 25 ps, respectively     

DIBL in short-channel NMOS devices at 77 K

Detailed experimental and two-dimensional numerical simulation results on drain-induced barrier lowering (DIBL) versus channel length at 300 and 77 K in short-channel NMOS devices are presented. It is found that by decreasing the temperature from 300 to 77 K. DIBL in NMOS devices with effective channel lengths (L) from 0.5 to 2.0 μm is improved for the range of L<0.6 μm and L>1.2 μm, but is worse for L between 0.6 and 1.2 μm. The new version of the two-dimensional device numerical simulation program MINIMOS 4.0, which includes device modeling at cryogenic temperatures, was used to investigate this unique characteristic. The measured DIBL characteristics can be explained physically as the transition from surface DIBL through the subsurface DIBL to the bulk DIBL or punchthrough effect at 300 K, but almost a surface DIBL for the whole range of channel length variation at 77 K. Design considerations for the channel doping profile for low-temperature operation based on keeping the same DIBL and V_TH as required for room-temperature operation are briefly discussed     

Inverted thin-film transistors with a simple self-aligned lightlydoped drain structure

The I-V characteristics of inverted thin-film transistors (TFT) are studied. A simple lightly doped drain (LDD) structure is utilized to control the channel electric field at the drain junction and to improve the performance of the TFTs. The LDD region is self-aligned to the channel and the source/drain regions. It is created by a spacer around an oxide mask which exclusively defines the channel length L_ch. Experimental data show that the leakage current, subthreshold swing SS, saturation current, and on/off current ratio of the inverted TFTs are closed related to L_ch, L_LDD, the drain bias, gate voltage, and LDD dose. With a gate deposited at low temperature, a saturation current of ~1.25 μA at 5 V and a leakage current of ~0.03 pA per micrometer of channel width were achieved. The current ratio therefore exceeds seven orders of magnitude, with an SS of 380 mV/decade. At 3.3 V, the current ratio is ~7×10⁶     

AlGaAs and GaAsP high-power ultrafast p+-n-n+diodes based on heterojunctions and a graded-gap base

The authors present a theoretical model of power p⁺-n-n ⁺ diodes with a graded-gap base and either homojunctions (GB) or heterojunctions (HGB), and numerical calculations of static and dynamic characteristics of AlGaAs (GaAsP) based structures. It is shown that HGB diodes will exhibit characteristics and properties significantly better than those of simple (homojunctions plus uniform base) GaAs and Si diodes. For example, the forward voltage drop in a high-voltage (W/L_p=13) high-frequency (t_rr=25 ns) HGB diode will be 50% and 300% smaller than the drop in, respectively, simple GaAs and Si diodes with the same W/L_p and t_rr. Other significant projected improvements include operation up to 450°C, an order of magnitude reduction in the reverse current, and a 50% increase in the breakdown voltage     

Self-aligned bottom-gate submicrometer-channel-length a-Si-:Hthin-film transistors

Fully self-aligned bottom-gate thin-film transistors (TFTs) fabricated by using a back substrate exposure technique combined with a metal lift-off process are discussed. Ohmic contact to the sources and drains is accomplished by a 40-nm-thick layer of phosphorous-doped microcrystalline silicon. Devices with channel lengths ranging from 0.4 to 12 μm are processed with overlap dimensions between the gate and the source and the gate and the drain ranging from 0.0 to 1.0 μm. Analysis of the conductance data in the linear voltage regime reveals a parasitic drain-to-channel and source-to-channel resistance that is 14% of the channel resistance for a 10-μm device and 140% for a 1-μm device. Thus, increase in the device speed caused by reducing the channel length does not follow expected behavior. A similar situation exists in the nonlinear regime. The on-current of the devices starts to saturate below channel lengths of 2 μm. Current on/off ratios taken at V_d=5 V and V_G=15 V and 0 V, respectively, are approximately 1×10⁶ for the 1- and 12-μm-long devices. The on/off ratio is reduced to 1×10⁵ for the 0.4-μm device     

Consideration of feed-through voltage in amorphous-Si TFT's

Feedthrough voltage is an important factor in designing integrated data drive circuits and display area in thin-film-transistor liquid-crystal displays (TFT LCDs). With respect to feedthrough voltage, only the gate-source overlay capacitance has been considered in amorphous-Si (a-Si) TFTs, because of their staggered structure with overlap area. It is pointed out that, in a-Si TFTs designed as active elements, feedthrough voltage is mainly due to the carrier redistribution. The main reason is that, since the field-effect mobility is low (W/L>1), the leakage current must be kept low (L⩾10 μm), and an active layer is inserted in the overlap area (unlike the case with MOS device structures), the area of the active layer is large. Taking the carrier redistribution into account, the maximum difference between the voltage obtained using the modified model and the experimental voltage is within 20%. By comparison, the results obtained using the previous model for TFTs are approximately three times smaller than the experimental results     

Information rates for magnetic recording channels with peak- andslope-limited magnetization

A model for magnetic recording is proposed which uses two parameters to describe the limitations on the remanent magnetization in the medium: the dimensionless peak value A_m and the steepest slope B(s^-1). A low-pass bandwidth restriction W(s^-1) due to read circuits is also included. Lower and upper bounds on the achievable transmission rates are derived in terms of the signal-to-noise ratio. For the case of ideal low-pass restriction with B≪W, the bounds increase linearly, logarithmically, and as the cube root, with low, medium, and large ρ_B, respectively. With B≪ W the problem reduces to the one with no restriction on the slope     

High-mobility poly-Si thin-film transistors fabricated by a novelexcimer laser crystallization method

High-mobility poly-Si thin-film transistors (TFTs) were fabricated by a novel excimer laser crystallization method based on dual-beam irradiation. The new method can reduce the solidification velocity of the top Si layer by heating the bottom Si layer of the Si/SiO₂/Si/glass substrate structure by means of laser irradiation not only from the front side but also from the back side. The grain size of poly-Si film was enlarged up to 2 μm. The field-effect mobilities of the TFT exceeded 380 cm²/V-s for electrons and 100 cm²/V-s for holes