A high-efficiency CMOS image sensor with air gap in situ MicroLens (AGML) fabricated by 0.18-/spl mu/m CMOS technology

The air gap in situ microlens (AGML) above-pixel sensor with 0.18-/spl mu/m CMOS image sensor technology has been successfully developed to dramatically improve the optical crosstalk and pixel sensitivity. We demonstrated excellent crosstalk diminution with the structure on small pixels. Compared with conventional 2.8 /spl mu/m square pixel, adopting the AGML can reduce the optical crosstalk up to 64%, and provide 21% in enhancement of photosensitivity at 0/spl deg/ incident angle. Furthermore, under 20/spl deg/ incident angle the optical crosstalk reduction and sensitivity enhancement are increased to 89% and 122%, respectively. Therefore, the AGML structure makes pixel size be further scaled down to less than 2.8 /spl mu/m square and maintain good performance.     

A sensitivity and linearity improvement of a 100-dB dynamic range CMOS image sensor using a lateral overflow integration capacitor

In a CMOS image sensor featuring a lateral overflow integration capacitor in a pixel, which integrates the overflowed charges from a fully depleted photodiode during the same exposure, the sensitivity in nonsaturated signal and the linearity in saturated overflow signal have been improved by introducing a new pixel circuit and its operation. The floating diffusion capacitance of the CMOS image sensor is as small as that of a four transistors type CMOS image sensor because the lateral overflow integration capacitor is located next to the reset switch. A 1/3-inch VGA format (640/sup H//spl times/480/sup V/ pixels), 7.5/spl times/7.5 /spl mu/m/sup 2/ pixel color CMOS image sensor fabricated through 0.35-/spl mu/m two-poly three-metal CMOS process results in a 100 dB dynamic range characteristic, with improved sensitivity and linearity.     

CMOS image sensor with mixed-signal processor array

We present a single-chip integration of a CMOS image sensor with an embedded flexible processing array and dedicated analog-to-digital converter. The processor array is designed to perform convolution and transformation algorithms with arbitrary kernels. It has been designed to carry out the multiplication of analog image data with given digital kernel coefficients and to add up the results. The processor array is an analog implementation of a highly parallel architecture which is scalable to any desired sensor resolution while preserving video-rate operation. A prototype implementation has been realized in a 0.6-/spl mu/m CMOS technology. Switched current technique has been applied to obtain compact and robust circuits. The prototype's sensor resolution is 64 /spl times/ 128 pixels. The processor array occupies a small chip area and consumes only a small percentage of the power (250 /spl mu/W) of the whole image sensor.     

Crosstalk and microlens study in a color CMOS image sensor

The paper describes results of crosstalk investigations and microlens (/spl mu/-lens) scan experiments in a color CMOS image sensor with active pixel structure . The investigation of optical and electrical crosstalk was made on 7.8- and 5.6-/spl mu/m pixels by using samples with continuous shift of color filter (CF ) and /spl mu/-lens across the array. As a result of this investigation, the distribution of sensitivity inside a pixel has been determined. By using minimum crosstalk criteria, the optimum parameters of the /spl mu/-lens manufacturing process and optimum position of the /spl mu/-lens was determined. The paper presents color maps of pixel sensitivity and crosstalk criteria as well as snapshots illustrating sensitivity distribution and collection area. The paper presents spectral characteristics measured at different relative apertures (f-number) as well. The quantitative analysis of spectral responses allowed us to determine the contribution of each component to the overall crosstalk.     

Light guide for pixel crosstalk improvement in deep submicron CMOS image sensor

Light guide, a novel dielectric structure consisting of PE-Oxide and FSG-Oxide, has been developed to reduce crosstalk in 0.18-/spl mu/m CMOS image sensor technology. Due to the difference in refraction index (1.46 for PE-Oxide and 1.435 for FSG-Oxide), major part of the incident light can be totally reflected at the interface of PE-Oxide/FSG-Oxide, as the incidence angle is larger than total reflection angle. With this light guide, the pixel sensing capability can be enhanced and to reduce pixel crosstalk. Small pixels with pitch 3.0-/spl mu/m and 4.0-/spl mu/m have been characterized and examined. In 3.0-/spl mu/m pixel, optical crosstalk achieves 30% reduction for incidence angle of light at 10/spl deg/.     

A CMOS image sensor with a double-junction active pixel

A CMOS image sensor that employs a vertically integrated double-junction photodiode structure is presented. This allows color imaging with only two filters. The sensor uses a 184*154 (near-QCIF) 6-transistor pixel array at a 9.6-/spl mu/m pitch implemented in 0.35-/spl mu/m technology. Results of the device characterization are presented. The imaging performance of an integrated two-filter color sensor is also projected, using measurements and software processing of subsampled images from the monochrome sensor with two color filters.     

Pulse frequency modulation based CMOS image sensor for subretinal stimulation

We have developed a CMOS image sensor based on pulse frequency modulation for subretinal implantation. The sensor chip forms part of the proposed intraocular retinal prosthesis system where data and power transmission are provided wirelessly from an extraocular unit. Image sensing and electrical stimulus are integrated onto the same chip. Image of sufficient resolution has been demonstrated using 16/spl times/16 pixels. Biphasic current stimulus pulses at above threshold levels of the human retina (500 /spl mu/A) at varying frame rates (4 Hz to 8 kHz) have been achieved. The implant chip was fabricated using standard CMOS technology.     

Degradation-free MOS image sensor with photonic crystal color filter

This letter demonstrates a long-term reliable MOS image sensor equipped with a novel photonic crystal color filter (PC-CF). PCs are periodically structured dielectric media, generally possessing a photonic band gap. In the newly developed PC-CF, it is clarified that the desirable spectral property, i.e., peak wavelength and spectral passband, can be achieved by modifying the thicknesses of the defect layers, which act just like a "defect" in a PC. The spectral characteristics with the peak wavelengths at 450 (blue), at 530 (green), and at 610 nm (red) are realized in this letter. Moreover, the fabricated image sensor guarantees high reliability of longer than 200 000 h and heat resistance of above 300 /spl deg/C.     

A Color CMOS Imager With 4 $times$ 4 White-RGB Color Filter Array for Increased Low-Illumination Signal-to-Noise Ratio

A color CMOS image sensor with the 4 times 4 White-RGB color filter array (CFA) including 50% white pixels has been developed. A transparent layer has been fabricated on the white pixel to realize over 95% transmission for visible light with wavelengths of 400-700 nm. Pixel pitch and number of the pixels were 3.3 mum and 2 million, respectively. With the simple and low-noise color separation process, low-illumination signal-to-noise ratios of luminance signal have been increased by 6 dB, compared with those of the Bayer pattern. Moreover, by locating the pixels so that every color components can be detected in every column and line, color artifacts at the edge were suppressed. The edge detection process became unnecessary and the process time was reduced by 70%. The new CFA has the potential to significantly increase the sensitivity of CMOS/CCD image sensors.     

An ultra-low dark current CMOS image sensor cell using n/sup +/ ring reset

We present in this letter for the first time a new CMOS image sensor cell using n/sup +/-ring-reset structure, which can isolate the photon-sensing area from the defective field oxide edge. The experimental results demonstrate that the severe dark current degradation of the conventional CMOS active pixel image sensor fabricated by a standard CMOS logic process is significantly alleviated. Through optimizing the layout arrangement, as high as 45% fill factor can be obtained. The dynamic range of this new cell can thus be improved by more than 10/spl times/ compared to a conventional cell.     

A 9-V/Lux-s 5000-frames/s 512/spl times/512 CMOS sensor

A high-responsivity 9-V/Lux-s high-speed 5000-frames/s (at full 512/spl times/512 resolution) CMOS active pixel sensor (APS) is presented in this paper. The sensor was designed for a 0.35-/spl mu/m 2P3M CMOS sensor process and utilizes a five-transistor pixel to provide a true parallel shutter. Column-parallel analog-to-digital converter (ADC) architecture yields fast readout from pixels and digitization of the data simultaneously with acquiring a new frame. The chip has a two-row SRAM to store data from the ADC and read previous rows of data out of the chip. There are a total of 16 parallel ports operating up to 90 MHz delivering /spl sim/1.3 Gpixel/s or 13 Gb/s of data at the maximum rate. In conclusion, a comparison between two high-speed digital CMOS sensor architectures, which are a column-parallel APS and a digital pixel sensor (DPS), is conducted.     

超连续谱光源辐照可见光CMOS图像传感器的实验研究

研究了超连续谱光源对可见光CMOS图像传感器辐照的实验现象和规律。观察到随着入射激光功率的不断增大，CMOS图像传感器依次出现了像元饱和、局部饱和、局部过饱和以及全屏饱和等现象。与1 060 nm锁模光纤激光辐照同种图像传感器的实验相对比，从有效干扰面积、图像相关度及图像均方差等三个方面，对比了两种干扰源在影响CMOS图像传感器成像质量方面的异同，发现CMOS图像传感器的响应特性、激光的频谱特性和成像光学系统的色散是导致干扰效果差异的主要原因。     

A Wide DR and Linear Response CMOS Image Sensor With Three Photocurrent Integrations in Photodiodes, Lateral Overflow Capacitors, and Column Capacitors

A 1/3-inch, 800^H x 600^v pixels, 5.6 x 5.6 mum² color CMOS image sensor with three photocurrent integrations in pixel photodiodes, pixel lateral overflow capacitors and column capacitors fabricated in a 0.18 mum 2P3M CMOS technology has been reported. The image sensor operates using photodiode integrations and lateral overflow integrations in low light condition and achieves a wide dynamic range (DR) performance of around 100 dB in its one exposure. The wide DR performance in one exposure makes high S/N ratios at the signal switching points in the multiple exposures. The CMOS image sensor also operates using the column capacitor integration in very bright light condition. In the column capacitor integration, the photocurrents generated at the photodiodes are directly integrated at the column capacitors in each column line. The combination of two exposures using the photodiode integrations and the lateral overflow integrations and one exposure using the column capacitors leads to the whole linear photo-electric conversion responses from low light to very bright light region. The fabricated image sensor achieves a high S/N ratio, a fully linear response and over 180 dB DR in the incident light ranging from about 1.4 x 10^-2 lx to about 2.4 x 10⁷ lx.     

A time-to-digital-converter-based CMOS smart temperature sensor

A time-to-digital-converter-based CMOS smart temperature sensor without a voltage/current analog-to-digital converter (ADC) or bandgap reference is proposed for high-accuracy portable applications. Conventional smart temperature sensors rely on voltage/current ADCs for digital output code conversion. For the purpose of cost reduction and power savings, the proposed smart temperature sensor first generates a pulse with a width proportional to the measured temperature. Then, a cyclic time-to-digital converter is utilized to convert the pulse into a corresponding digital code. The test chips have an extremely small area of 0.175 mm/sup 2/ and were fabricated in the TSMC CMOS 0.35-/spl mu/m 2P4M process. Due to the excellent linearity of the digital output, the achieved measurement error is merely -0.7/spl sim/+0.9/spl deg/C after two point calibration, but without any curvature correction or dynamic offset cancellation. The effective resolution is better than 0.16/spl deg/C, and the power consumption is under 10 /spl mu/W at a sample rate of 2 samples/s.     

A signal-processing CMOS image sensor using a simple analog operation

We have developed a high-density CMOS image sensor with a normal mode and three signal-processing function modes: wide dynamic-range mode, motion-detection mode, and edge-extraction mode. Small pixel size and real-time operation are achieved by using a four-transistor and one-capacitor pixel scheme and column-parallel on-chip analog operation. The chip includes 512 (H) /spl times/384 (V) effective pixels. Each pixel has a sufficient fill factor of 24% in an area of 9.3/spl times/9.3 /spl mu/m/sup 2/. The dynamic range at the wide dynamic-range mode is a maximum 97 dB against 51 dB at the normal-readout mode. The chip consumes 79 mW, and the gain-control amplifier and 8-b analog-to-digital converter operate at 46 frames/s using a 3.3-V single power supply.     

Dramatic reduction of optical crosstalk in deep-submicrometer CMOS imager with air gap guard ring

A dielectric structure, air gap guard ring, has been successfully developed to reduce optical crosstalk thus improving pixel sensitivity of CMOS image sensor with 0.18-/spl mu/m technology. Based on refraction index (RI) differences between dielectric films (RI = 1.4 /spl sim/ 1.6) and air gap (RI = 1), total internal reflection occurred at dielectric-film/air-gap interface, thus the incident light is concentrated in selected pixel. Excellent optical performances have been demonstrated in 3.0 /spl times/ 3.0 /spl mu/m pixel. Optical spatial crosstalk achieves 80% reduction at 20/spl deg/ incidence angle and significantly alleviates the pixel sensitivity degradation with larger angle of incident light.     

A 1/3' VGA linear wide dynamic range CMOS image sensor implementing a predictive multiple sampling algorithm with overlapping integration intervals

Many tasks performed by machine vision systems involve processing of natural scenes with large intra-frame illumination ratios. Thus, wide dynamic range visible spectrum image sensors are required to achieve adequate processing performance and reliability. An image sensor implementing an algorithm that linearly increases the illumination dynamic range of solid-state pixels is presented. Optimal exposure is achieved with a predictive pixel saturation decision that allows for multiple integration intervals of different duration to run concurrently for different pixels while keeping the sensor frame rate constant. A proof-of-concept chip was fabricated in a 0.18-/spl mu/m CMOS process. Added functionality to standard imagers is mainly concentrated off-pixel so fill factor is not sacrificed. Measured data corroborates the algorithm functionality.     

In-pixel autoexposure CMOS APS

A CMOS active pixel sensor (APS) with in-pixel autoexposure and a wide dynamic-range linear output is described. The chip features a unique architecture enabling a customized number of additional bits per pixel per readout, with minimal effect on the sensor spatial or temporal resolution. By utilizing multiple readouts via real-time feedback, each pixel in the field of view can automatically set an independent exposure time, according to its illumination. A customized, large increase in the dynamic range can be achieved and a scene containing both bright and dark regions can be captured. A prototype of 64 /spl times/ 64 pixels has been fabricated using 1-poly 3-metal CMOS 0.5 /spl mu/m n-well process available through MOSIS. Power dissipation is 3.7 mW at V/sub DD/ = 5 V. The special functions have been verified experimentally, and an increase of 2 bits over the inherent dynamic range captured is shown.     

A fully parallel CMOS analog median filter

A fully integrated CMOS implementation of a continuous-time analog median filter is presented. The median filter uses two compact analog circuits as building blocks to implement the variable delay and median detection. Median detectors are based on current saturating transconductance comparators, while the time delay is implemented using first-order all-pass filters. Both circuits allow modular expansion for the implementation of large median filter array processors. Based on these blocks, a new fast technique for parallel image processing is presented. It is shown that an image of 91/spl times/80 pixels can be processed in less than 8 /spl mu/s using an array of median filter cells. Experimental results of a test chip prototype in 2-/spl mu/m CMOS MOSIS technology are presented.     

A quad CMOS single-supply op amp with rail-to-rail output swing

The realization of a commercially viable, general-purpose quad CMOS amplifier is presented, along with discussions of the tradeoffs involved in such a design. The amplifier features an output swing that extends to either supply rail, together with an input common-mode range that includes ground. The device is especially well suited for single-supply operation and is fully specified for operation from 5 to 15 V over a temperature range of -55 to +125/spl deg/C. In the areas of input offset voltage, offset voltage drift, input noise voltage, voltage gain, and load driving capability, this implementation offers performance that equals or exceeds that of popular general-purpose quads or bipolar of Bi-FET construction. On a 5-V supply the typical V/SUB os/ is 1 Mv, V/SUB os/ drift is 1.3 /spl mu/V//spl deg/C, 1-kHz noise is 36 nV//spl radic/Hz, and gain is one million into a 600-/spl Omega/ load. This device achieves its performance through circuit design and layout techniques as opposed to special analog CMOS processing, thus lending itself to use on system chips built with digital CMOS technology.