Measurement of emitter and collector series resistances

Emitter and collector series (extrinsic) resistances can be evaluated by measuring the open-circuited (floating) junction voltage as the other junction is forward biased. Evaluation can be carried out on either a point-by-point basis or with the aid of a curve tracer. Specific results are indicated for a 2N4400 transistor and an experimental transistor.     

Error minimisation in the measurement of bipolar collector and emitter resistances

An analysis of open-circuited collector and forced beta methods for emitter and collector resistance determination is presented. The analysis particularly focuses attention on high-injection effects and the influences of recombination within, and at the surface of, junction depletion layers. Semiquantitative criteria for minimisation of measurement error evolve and additionally, methods for extraction of certain inverse and nonideal diode parameters are suggested.     

Extraction of emitter and base series resistances of bipolartransistors from a single DC measurement

A new procedure for extracting the emitter and base series resistances of bipolar junction transistors is presented. The parameters are extracted from a single measurement in the forward active region on one transistor test structure with two separate base contacts, making it a simple and attractive tool for bipolar transistor characterization. The procedure comprises two methods for extracting the emitter resistance and two for extracting the base resistance. The choice of method is governed by the amount of current crowding or conductivity modulation present in the intrinsic base region. The new extraction procedure was successfully applied to transistors fabricated in an in-house double polysilicon bipolar transistor process and a commercial 0.8-μm single polysilicon BiCMOS process. We found that the simulated and measured Gummel characteristics are in excellent agreement and the extracted series resistances agree well with those obtained by means of HF measurements. By adding external resistors to the emitter and base and then extracting the series resistances, we verified that the two base contact test structure offers a simple means of separating the influence of emitter and base series resistances on the transistor characteristics     

New technique for determination of static emitter and collector series resistances of bipolar transistors

Starting with detailed investigations of the IC/VCE characteristics in the vicinity of the origin it is shown how the static emitter and collector series resistances of bipolar transistors can simply be determined using a curve tracer. Experimental results demonstrate the efficiency of this technique.     

Modeling hot-carrier effects in polysilicon emitter bipolartransistors

In self-aligned polysilicon emitter transistors a large electric field existing at the periphery of the emitter-base junction under reverse bias can create hot-carrier-induced degradation. The degradation of polysilicon emitter transistor gain under DC stress conditions can be modelled by ΔI_B∝I_R ^m+ntⁿ where n≈0.5 and m ≈0.5. The more complex relationships of Δβ(I _C, I_R, t) and β(I _C, I_R, t) result naturally from the simple ΔI_B model. Using these relationships the device lifetime can be extrapolated over a wide range of reverse stress currents for a given technology     

Measurement of the low-current base and emitter resistances of bipolar transistors

A new ac method is proposed to measure the emitter and base resistances of bipolar transistorsat low current levels at which the effective transistor geometry is given by the processing and is unaffected by the changes induced by high currents. The technique is based on a measurement of the input impedance at frequencies below about 50 MHz. It is particularly suited for the measurement of the physical emitter resistance of scaled transistors. The method is illustrated on microwave transistors with metal contacts and on self-aligned digital transistors with polysilicon contacts. A comparison of the results obtained using this method with those from dc methods operating at high currents can be used to explore the current dependencies of the resistances. The technique is applicable both for homojunction and heterojunction transistors.     

The benefits of fluorine in pnp polysilicon emitter bipolartransistors

BF₂ implantation into polysilicon and its subsequent rapid thermal diffusion into single crystal silicon is commonly used for the fabrication of pnp polysilicon emitter bipolar transistors. In this paper the effect of the fluorine, which is introduced into the polysilicon during the BF₂ implant, is investigated. Pnp polysilicon emitter bipolar transistors are fabricated in which the boron and fluorine are implanted separately, with the fluorine only going into one half of each wafer. Electrical results show that fluorine has two interrelated effects. In devices given a low thermal budget emitter drive-in, a drop in base current by a factor of approximately 3.2 is observed when the fluorine is present, together with an improvement in the ideality of the base characteristics. This is explained by the passivation of trapping states at the polysilicon/silicon interface by the fluorine. In contrast, in devices-given a higher thermal budget emitter drive-in, an increase in base current by a factor of approximately 2.5 is observed, when fluorine is present. This is explained by the action of the fluorine in accelerating the breakup of the interfacial layer. A model is proposed to explain this behavior     

Two-dimensional analysis of emitter resistance in the presence ofinterfacial oxide breakup in polysilicon emitter bipolartransistors

Two-dimensional computer simulations of the emitter resistance and majority carrier current flow in the presence of interfacial oxide breakup in polysilicon emitter bipolar transistors are shown and compared with published experimental results. The analysis reveals that the behavior of the emitter resistance with oxide layer breakup can be adequately predicted only if 2-D majority carrier current flow is taken into account. The interfacial layer plays an important role in determining the emitter resistivity only in very early stages of oxide layer breakup. Both the experimental data and the analysis reveal a much faster fall-off in emitter resistance with oxide layer breakup than previous 1-D dimensional theoretical analyses have suggested. The 2-D majority carrier modeling presented suggests that the emitter resistance decreases much more rapidly than the current gain in the early stages of oxide layer breakup. Physical mechanisms which explain the differences in the dependence of the emitter resistance and gain on oxide layer breakup are proposed     

A proposed collector design of double heterojunction bipolartransistors for power applications

A new collector design for the AlGaAs-GaAs double heterostructure bipolar transistor (DHBT) is proposed, analyzed, and simulated. The base-collector junction is linearly graded and terminated with a highly doped thin layer to offset the adverse alloy grading electric field. Simple analytical formulas are derived to facilitate the implementation of the design. A proof-of-principle simulation has been carried out for an X-band AlGaAs-GaAs power DHBT to confirm the design and the derived formula. The simulation shows the breakdown voltage can be increased from 30 V to about 45 V while the critical current density is about the same. It is also shown that, unlike other refined DHBT structures, the proposed structure does not require critical control in the fabrication of the base-collector junction     

Thermal stability analysis of AlGaAs/GaAs heterojunction bipolartransistors with multiple emitter fingers

A numerical electro-thermal model was developed for AlGaAs/GaAs heterojunction bipolar transistors (HBT's) to describe the base current, current gain and output power dependence on junction temperature. The model is applied to microwave HBT devices with multi-emitter fingers. The calculated results of the common-emitter, current-voltage characteristics in the linear active region show a “current crush” effect due to inherent nonuniform junction temperature, current density and current gain distribution in the device. The formation of highly localized high temperature regions, i.e., hot spots, occur when the device is operating beyond the current-crush point. This thermally induced current instability imposes an upper limit on the power capability of HBT's. The dependence of this effect on various factors is discussed. These factors include the intrinsic parameters such as the base current ideality factor, the “apparent” valence band discontinuity, and the temperature coefficient of the emitter-base turn-on voltage, as well as the extrinsic factors such as the emitter contact specific resistance, the substrate thermal conductivity and the heat source layout     

Extraction of collector resistances for device characterization and compact models

A methodology for the extraction of a bipolar transistor collector resistance from its output characteristics using the Forced-Beta Method has been demonstrated. The presented extraction methodology eliminates the need for additional measurements in the evaluation of collector resistances and allows reuse of the existing standard output characteristics data. The method is particularly suitable for compact modeling and technology characterization from high-frequency transistor test structures with no separate substrate contacts.     

Electron-optical-phonon scattering in the emitter and collector barriers of semiconductor-metal-semiconductor structures

A theoretical analysis is made of the effects on the emitter-collector current transfer ratio of optical-phonon scattering of electrons in the emitter and collector semiconductors of semiconductor-metal-semiconductor structures. The collector and emitter efficiencies are shown to increase appreciably with increasing collector and emitter electric fields respectively. At temperatures such that kT ≈ the optical-phonon energy, E₀, the collector efficiency varies only slightly with increasing emitter-collector barrier height difference, Δ, but the emitter efficiency is greatly decreased when Δ<E₀. The collector and emitter efficiencies increase substantially with decreasing temperature when Δ<E₀, but only slightly when Δ>E₀.

The current transfer ratios predicted by this theory for Si---Au---Si and GaAs---Au---Si structures are 0·68 and 0·55 respectively at 298°K and 0·85 and 0·61 respectively at 105°K with a collector field of 10⁵ V/cm. This calculation does not treat collisions in the metal or quantum-mechanical reflection of electrons at the collector barrier.     

Characterization and measurement of the base and emitter resistances of bipolar transistors

Most previously published methods of measuring transistor base resistance are surveyed and compared. The input impedance circle diagram method is examined in detail and correction factors due to parasitic capacitances are derived. Emitter series resistance is also estimated from this data. A new method of measuring base resistance requiring much less measurement effort is introduced and shown to give good agreement with the circle diagram method. This method is called the phase cancellation method and gives an estimate of base resistance from the common base input impedance at the collector current where its imaginary part is zero. Also an estimate of series emitter resistance is obtained from this measurement and shown to agree well with other methods.     

DC analysis of multiple collector and multiple emitter transistors in integrated structures

A generalized set of equations has been developed for the multiple collector and multiple emitter transistors. These equations are applicable to the lateral transistors, SCR's, and the T/SUP 2/L coupling transistors. The analysis shows how a nonuniform base layer (double-epitaxial structure) can increase the alpha of the lateral transistor and decrease the current drain to the substrate and decrease the current drain to the substrate. The analysis also shows that in a T/SUP 2/L gate the inverse alpha is nearly equal to the cross-coupling current ratio, and can be reduced by increasing the number of inputs.     

Method for determining the emitter and base series resistances of bipolar transistors

A simple method for determining both the emitter and the base series resistances of bipolar transistors from the measured I - V characteristics is described. The method is based on the observation that deviation of the base current from the idealexp (qV_{BE}/kT)behavior at high currents can be attributed solely and relatively simply to series resistances. Series resistances determined by this method are given for sample high-speed digital bipolar transistors.     

Extraction of the base and emitter resistances in bipolar transistors using an accurate base resistance model

A straightforward method for extracting the base and emitter resistances is presented. The method has the following properties: 1) only a standard forward Gummel measurement on one transistor is required; 2) current-crowding and conductivity-modulation in the base are accounted for through the use of an accurate base resistance model; and 3) the resistance parameters are extracted using a nonlinear optimization step. Furthermore, a technique for extraction of the high-injection parameters of a modified collector current model is also presented.     

Monte Carlo studies of the effect of emitter junction grading onthe electron transport in InAlAs/InGaAs heterojunction bipolartransistors

InAlAs/InGaAs HBTs with various emitter junction gradings are simulated using a self-consistent Monte Carlo simulator. The effects of the emitter junction grading and the shift of the emitter-base p-n junction into the emitter depletion region due to diffusion of the base dopant are investigated. A minimum transit time of 1.18 ps is predicted for an In(Ga_1-xAl_x)As grading with x=0.6 at the E-B interface and J_C=0.7×10⁵ A/cm². Graded-base designs do not offer any transit time performance improvement compared with the graded E-B approach. For transient performance, the device switching time is found to remain constant at about 2.2 ps up to x₀~0.7 but increases for larger values. A cutoff frequency as high as 270 GHz was observed for x₀=0.7, indicating that the best transport can be achieved from intermediately graded rather than abrupt E-B junction designs