Next-generation lithography for 22 and 16 nm technology nodes and beyond

In this paper, next-generation lithography (NGL) for the 22 and 16 nm technology nodes and beyond is reviewed. A broad range of topics, including history, technologies, critical challenges, and the most plausible candidates are discussed. The 22 and 16 nm technology nodes rely on NGL. NGLs have been extensively studied. Because of technological issues, the semiconductor industry has stopped pursuing several NGLs, such as X-ray proximity lithography, ion projection lithography, and scattering with angular li...     

Fully depleted SOI (FDSOI) technology

Fully depleted SOI (FDSOI) has become a viable technology not only for continued CMOS scaling to 22 nm node and beyond but also for improving the performances of legacy technology when retrofitting to old technology nodes. In this paper, we provide an overview of FDSOI technology, including the benefits and challenges in FDSOI design, manufacturing, and ecosystem. We articulate that FDSOI is potential cornerstone for China to catch up and leapfrog in semiconductor technology.     

Fabrication of nanoscale tungsten tip arrays for scanning probemicroscopy-based devices

A new fabrication process for nanoscale tungsten tip arrays was developed for scanning probe microscopy-based devices. It is suitable to make a huge array on a device chip and is potentially compatible with CMOS technology. In this study, tungsten was selected as a tip material because of its hardness and conductivity. The newly developed fabrication process mainly consists of several important techniques: a combination of optical lithography and electron beam (EB) lithography to reduce the total exposure time with high resolution and chromium/tungsten/chromium (Cr/W/Cr) sandwich deposition and etching in which the first chromium layer is used as a mask and a second one is used as an etch stop. A periodic array of dots in an EB resist with a spot diameter of less than 50 nm was obtained by a combination of optical lithography and EB lithography with a positive resist (polymethylmethacrylate) in which all processing conditions were optimized carefully. A thin and uniform chromium film, deposited by ion-beam sputtering, allowed the use of thin polymethylmethacrylate (PMMA) film which led to the high resolution. The conditions of dc magnetron sputtering were also optimized in order to deposit a densely packed and low-resistivity film. The resulting tungsten tip arrays had a cylindrical shape with diameters of less than 60 nm and heights of 300 nm     

CMOS technology trends and economics

CMOS has become the mainstream IC technology. Extending well into the sub-0.1-μm regime, its potential provides enormous chip complexities for integration of complete systems on one chip. A number of general trends in the development and manufacturing of CMOS technologies and ICs are discussed. It is argued that unrestricted availability of this technology is of strategic importance for the European high-technology industry. Exploding development costs and investments per technology generation require global cooperation, particularly for the relatively small European IC manufacturers to survive in this key technology. Trends in the development of 64-Mb and 256-Mb DRAMs, optical lithography processes, multilayer resist technologies, retrograde-well structures for CMOS device isolation, low-resistive and dense interconnection systems with low capacitances and silicon-on-insulator technology for the development of CMOS devices are described     

Minimum energy solution for ultra-low power applications

Microsystem Technologies - This paper examines device sizing of CMOS inverter circuit at 22-nm technology node using predictive technology model in deep subthreshold region. Channel length (L) of...     

Novel devices and process for 32 nm CMOS technology and beyond

The development of next 32 nm generation and below needs innovations on not only device structures, but also fabrication techniques and material selections. Among those promising technologies, new gate structures as high-κ gate dielectric and metal gate, strain channel carrier mobility enhancement technology, and novel non-planar MOSFET structures are all possible candidate technologies. In this paper, we will specify our discussion on the research progress of high-κ-metal gate and non-planar MOSFET-technologies that are suitable to 32 nm technology node and beyond.     

GDI logic implementation of uniform sized CSLA architectures in 45 nm SOI technology

The Carry Select Adder (CSLA) is one of the fastest multi-bit adder architectures being used in various high speed processors. The CSLA is fast but compromises on the area and power consumption due to its complex architecture when implemented using standard CMOS logic. In this work, an alternate implementation of the CSLA architecture is done using Gate Diffusion Input (GDI) logic; instead of the CMOS logic. This approach simplifies the overall architectural dimensions due to reduction in transistor count as well as the power consumption. In this work, various types of CSLA architectures are implemented using the GDI logic and compared with their CMOS logic counterparts in terms of average power, delay and transistor count in 45 nm technology node. The comparative analysis clearly shows that GDI based circuits are better compared to CMOS logic implementations.     

32 nm CMOS工艺的单粒子多点翻转加固锁存器设计

随着集成电路工艺不断改进,电荷共享效应诱发的单粒子多点翻转已经成为影响芯片可靠性的重要因素.为此提出一种有效容忍单粒子多点翻转的加固锁存器:低功耗多点翻转加固锁存器(low power multiple node upset hardened latch,LPMNUHL).该锁存器基于单点翻转自恢复的双联互锁存储单元(...     

The scaling challenges of CMOS and the impact on high-density non-volatile memories

Solid-state mass storage has experienced recently an explosive growth, mainly related to digital consumer application (digital cameras, MP3 players, USB keys). The demand is not expected to slow down in the near future. Present storage technology is based on NAND Flash, and it appears that there is still margin to scale it down at least to the 45 nm node. The likely appearance of physical limits to scalability is pushing for the investigation of alternative storage technologies, and several solutions have been proposed. However, any kind of memory needs a selection mechanism, and related parasitic effects can be a severe limitation to scaling. Scaling challenges of select devices (mostly CMOS), and their impact on memory scaling will be investigated, and alternatives proposed.     

Looking into the future of Nanoelectronics in the Diversification Efficient Era

The linear scaling of CMOS has encountered, since its beginning, many hurdles which request new process modules, driven mainly by the maximization of energy efficiency. Fabrication at the sub 10 nm node level will request Intrinsic Variability approaching to zero. The rapid growth of mobile, multifunctional and autonomous systems is hardly demanding to reach Zero Power consumption. The solutions to integrate Thin Film based devices, architectures and systems in order to face these challenges are described.     

Microlithography: trends, challenges, solutions, and their impact on design

With lithography parameters approaching their limits, continuous improvement requires increasing dialogues and compromises between the technology and design communities. Only with such communication can semiconductor manufacturers reach the 30 nm physical-gate-length era with optical lithography. Optical lithography is an enabling technology for transistor miniaturization. With the wavelength and numerical aperture of exposure systems approaching their limits, the semiconductor industry needs continuous reduction of the k/sub 1/ factor. Challenges include image quality improvement, proximity effect correction, and cost control. An indispensable ingredient for future success is improvement in the design-manufacture interface.     

65 nm CMOS可集成ps级窄脉冲驱动器

光电集成工艺和高速光脉冲队列技术的发展使得新型光互连技术——光SerDes收发器得以提出。相比现有光互连技术,光SerDes技术具有更高速率、更低功耗和更高集成度的优点。但其对于驱动光开关产生长周期窄脉冲光信号的驱动电路的性能、工艺及集成度有了更高要求。提出了一种应用于光SerDes收发器的65nm CMOS工艺下的集成ps级窄脉冲驱动器。该驱动器可产生脉宽精确可调的长周期窄脉冲,可获得窄至13ps的脉冲输出,其工作电压范围宽达1.4~2.0V,时钟频率范围可由数KHz宽至25GHz。     

Focussed ion beam based fabrication of micro-electro-mechanical resonators

A simple and fast process to fabricate micro-electro-mechanical (MEM) resonators with deep sub-micron transduction gaps in thin SOI is presented. The proposed process is realized on both 350 nm and 1.5 μm thin silicon-on-insulator (SOI) substrates, evaluating the possibilities for MEMS devices on thin SOI for future co-integration with CMOS circuitry on a single chip. Through the combination of conventional UV-lithography and focused ion beam (FIB) milling the process needs only two lithography steps, achieving ∼100 nm gaps, thus ensuring an effective transduction. Different FIB parameters and etching parameters and their effect on the process are reported.     

光学视觉传感器技术研究进展

视觉传感是人类感知外界、认知世界的主要途径，研究表明人类获取的外界信息大约有80%来自于视觉。作为感知外界信息的“电子眼球”，视觉传感器是消费电子、机器视觉、安防监控、科学探测和军事侦察等领域的核心器件。近年来视觉传感器技术发展迅速，不同类型的传感器从不同维度提供丰富的视觉数据，不断增强人类感知与认知能力，视觉传感器研究工作具有重要的理论与应用需求。本报告以典型光学视觉传感器技术为主线，通过综合国内外文献和相关报道，从CCD图像传感器、CMOS图像传感器、智能视觉传感器以及红外图像传感器等研究方向，梳理论述近年来光学视觉传感器技术的发展现状、前沿动态、热点问题和趋势。     

Fabrication of Fresnel zone plates with high aspect ratio by soft X-ray lithography

High focusing efficiency Fresnel zone plates for hard X-ray imaging is fabricated by electron beam lithography, soft X-ray lithography, and gold electroplating techniques. Using the electron beam lithography, Fresnel zone plates which has an outermost zone width of 100 nm and thickness of 250 nm has been fabricated. Fresnel zone plates with outermost zone width of 150 nm and thickness of 660 nm has been fabricated by using soft X-ray lithography.     

网络编码调度算法的研究

近年来,网络编码作为提高通信系统吞吐量一种手段。在多播的通信网络,网络中各个传送节点结合动态变化的网络情况,对不同信息流的数据包进行编码处理,从而减轻局部节点的阻塞,提高了整个通信系统的性能。文章主要工作要体现在典型无线通信网络中,引入动态网络编码调度算法,提高无线通信系统的网络编码增益和系统吞吐量;探讨在自适应无线通信系统下,如何适当的使用自适应技术,使得动态网络编码调度算法的作用发挥到最大。各个节点间的发送端更应选取适合的自适应技术,来提高无线通信系统性能。通过MATLAB仿真显示,带有自适应技术的无线网络,在动态网络编码调度算法作用下,对改进系统性能有着更加重要的现实意义。     

SVM based layout retargeting for fast and regularized inverse lithography

Inverse lithography technology （ILT）, also known as pixel-based optical proximity correction （PB-OPC）, has shown promising capability in pushing the current 193 nm lithography to its limit. By treating the mask optimization process as an inverse problem in lithography, ILT provides a more complete exploration of the solution space and better pattern fidelity than the tradi-tional edge-based OPC. However, the existing methods of ILT are extremely time-consuming due to the slow convergence of the optimization process. To address this issue, in this paper we propose a support vector machine （SVM） based layout retargeting method for ILT, which is designed to generate a good initial input mask for the optimization process and promote the convergence speed. Supervised by optimized masks of training layouts generated by conventional ILT, SVM models are learned and used to predict the initial pixel values in the‘undefined areas’ of the new layout. By this process, an initial input mask close to the final optimized mask of the new layout is generated, which reduces iterations needed in the following optimization process. Manu-facturability is another critical issue in ILT;however, the mask generated by our layout retargeting method is quite irregular due to the prediction inaccuracy of the SVM models. To compensate for this drawback, a spatial filter is employed to regularize the retargeted mask for complexity reduction. We implemented our layout retargeting method with a regularized level-set based ILT （LSB-ILT） algorithm under partially coherent illumination conditions. Experimental results show that with an initial input mask generated by our layout retargeting method, the number of iterations needed in the optimization process and runtime of the whole process in ILT are reduced by 70.8%and 69.0%, respectively.     

Scaling CMOS devices through alternative structures

The conventional wisdom holds that CMOS devices cannot be scaled much further from where they are today because of several device physics limitations such as the large tunneling current in very thin gate dielectrics. It is shown that alternative device structures can allow CMOS transistors to scale by another 20 times. That is as large a factor of scaling as what the semiconductor industry accomplished in the past 25 years. There will be many opportunities and challenges in finding novel device structures and new processing techniques, and in understanding the physics of future devices.     

Dual layer photoresist complimentary lithography applied on sapphire substrate for producing submicron patterns

In this study, the combined technologies of dual-layer photoresist complimentary lithography (DPCL), inductively coupled plasma-reactive ion etching and laser direct-write lithography are applied to produce the submicron patterns on sapphire substrates. The inorganic photoresist has almost no resistance for chlorine containing plasma and aqueous acid etching solution. However, the organic photoresist has high resistance for chlorine containing plasma and aqueous acid etching solution. Moreover, the inorganic photoresist is less etched by oxygen plasma etching process. The organic and inorganic photoresist deposit sequentially into a composite photoresist on a substrate. The DPCL takes advantages of the complementary chemical properties of organic and inorganic photoresist. We fabricated two structures with platform and non-platform structure. The non-platform structure featured structural openings, the top and bottom diameters and the depth are approximately 780, 500 and 233 nm, respectively. The platform structure featured structural openings, the top and bottom diameters and the depth are approximately 487, 288 and 203 nm, respectively. The precision submicron or nanoscale patterns of large etched area and patterns with high aspect ratio can be quickly produced by this technique. This technology features a low cost but high yield production technology. It has the potential applications in fabrication of micro-/nanostructures and devices for the optoelectronic industry, semiconductor industry and energy industry.     

低功耗低电源线噪声纳米CMOS全加器

提出一种低功耗低电源线噪声的纳米CMOS全加器。采用电源门控结构的全加器来降低纳米CMOS电路的漏电功耗,改进了传统互补CMOS全加器的求和电路,减少了所需晶体管的数目,并进一步对休眠晶体管的尺寸和全加器的晶体管尺寸进行了联合优化。用Hspice在45nmCMOS工艺下的电路仿真结果表明,改进后的全加器电路在平均功耗时延积、漏电功耗和电源线噪声等方面取得了很好的效果。