Circuit Design of a High Speed and Low Power CMOS Continuous-time Current Comparator

Current comparator is a fundamental component of current-mode analog integrated circuits. A novel high-performance continuous-time CMOS current comparator is proposed in this paper, which comprises one CMOS complementary amplifier, two resistive-load amplifiers and two CMOS inverters. A MOS resistor is used as the CMOS complementary amplifier's negative feedback. Because the voltage swings of the CMOS complementary amplifier are reduced by low input and output resistances, the delay time of the current comparator is shortened. Its power consumption can be reduced rapidly with the increase of input current. Simulation results based on 1.2 m CMOS process model show the speed of the novel current comparator is comparable with those of the existing fastest CMOS current comparators, and its power consumption is the lowest, so it has the smallest power-delay product. Furthermore, the new current comparator occupies small area and is process-robust, so it is very suitable to high-speed and low-power applications.     

A 1.2 V Rail-to-Rail Analog CMOS Rank-Order Filter with k-WTA Capability

In this paper, we design a rank-order filter with k-WTA capability for 1.2 V supply voltage. The circuit can find a rank order among a set of input voltages by setting different binary signals. Moreover, without modifying the circuit, the k-WTA function can be easily configured. The circuit has been designed using a 0.5 m DPDM CMOS technology. Seven input voltages are used to verify the performance of the circuit. The results of HSPICE post-layout simulation show that the response time of the circuit is 10 s for each rank-order operation, the input dynamic range is rail-to-rail, and the resolution is 10 mV for 1.2 V supply voltage. An experimental chip has been fabricated, in which accuracy of the comparator is measured as 40 mV for low-voltage operation. The dynamic power dissipation of the chip is 550 W.     

A CMOS Voltage Comparator with Rail-to-Rail Input-Range

A simple new continuous-time CMOS comparator circuit with rail-to-rail input common-mode range and rail-to-rail output is presented. This design uses parallel complementary decision paths to accommodate power-supply-valued inputs. The 2 decision results are combined at a current summing node, converted to a voltage, and buffered to drive voltage loads. The circuit has been realized in an area of 416 m×221 m in a MOSIS 2-micron CMOS technology. Average delay of about 63 ns has been measured at 3 V (1.3 mA), and about 89 ns at 5 V (1.1 mA).     

A 10 bit Current-Mode CMOS A/D Converter with a Current Predictor and a Modular Current Reference

This paper describes a 10 bit CMOS current-mode A/D converter with a current predictor and a modular current reference circuit. A current predictor and a modular current reference circuit are employed to reduce the number of comparator and reference current mirrors and consequently to decrease a power dissipation. The 10 bit current-mode A/D converter is fabricated by the 0.6 m n-well double poly/triple metal CMOS technology. The measurement results show the input current range of 16–528 A, DNL and INL of ±0.5 LSB and ±1.0 LSB, conversion rate of 10 M samples, and power dissipation of 94.4 mW with a power supply of 5 V. The effective chip area excluding the pads is 1.8 mm×2.4 mm.     

Precision Multi-Input Current Comparator and Its Application to Analog Median Filter Implementation

In this work, a simple architecture of a precision CMOS multi-input current comparator is proposed. The circuit is based on the usage of a multi-input current Max circuit. The inherent corner error of the Max circuit is eliminated, using a feedback circuit, increasing thus the precision of the comparator. Only the digital output corresponding to the maximum (or minimum) input current is at logic 1, while the other outputs are at logic 0. An application of the comparator to the analog implementation of a current-mode median filter is also presented. A five-input comparator and a three-input median filter were fabricated using double-poly double-metal 2 m CMOS MIETEC technology. Experimental results are given, to validate the theoretical analysis and to demonstrate the feasibility and the precision of the proposed circuits.     

Design Theory and Performance of 1-GHz CMOS Downconversion and Upconversion Mixers

A CMOS mixer topology capable of both downconversion and upconversion mixing for use in integrated wireless transceivers is presented. The mixing is based on two cross-coupled differential pairs as commutators with two source-followers as current modulators. Independence of the input and output bandwidths allows this topology to be optimized separately for either downconversion or upconversion mixer. The prototypes of both upconversion and downconversion mixers, optimized for linearity and realized in 0.8 m CMOS technology, have been demonstrated to fully operate at 1 GHz with good linearity and low power consumption. In addition, another mixer, optimized for noise figure and realized in 0.5 m CMOS technology, has been designed to achieve a NF of around 12 dB.     

Design and Analysis of Built-In Testers for CMOS Switched-Current Circuits

This paper presents the design and analysis of a built-in tester circuit for MOS switched-current circuits used in low-voltage/low-power mixed-signal circuits/systems. The use of the tester can reduce the test length significantly. The developed tester is comprised of a current comparator, a voltage window comparator, and a digital latch. The current comparator is required to have high-accuracy, low-power consumption, simple structure with small chip area, and moderate speed. Results show that the developed current comparator circuit is developed with a small offset current, 0.1 nA, low power consumption, 20 W, and a layout area of 0.01 mm², where the circuit is simulated with the MOSIS SCN 2 m CMOS process parameters and 2 V supply voltage.     

A 70-MHz Continuous-Time CMOS Band-Pass ΣΔ Modulator for GSM Receivers

A 70-MHz continuous-time CMOS band-pass modulator for GSM receivers is presented. Impulse-invariant-transformation is used to transform a discrete-time loop-filter transfer function into continuous-time. The continuous-time loop-filter is implemented using a transconductor-capacitor (G _m -C) filter. A latched-type comparator and a true-single-phase-clock (TSPC) D flip-flop are used as the quantizer of the modulator. Implemented in a MOSIS HP 0.5-m CMOS technology, the chip area is 857 m × 420 m, and the total power consumption is 39 mW. At a supply voltage of 2.5 V, the maximum SNDR is measured to be 42 dB, which corresponds to a resolution of 7 bits.     

Design of a New High Speed Amplifier Circuit for the Analog Subsystems

A high speed CMOS amplifier circuit with a new architecture especially suited for analog subsystems and a simple high speed CMOS comparator utilizing the proposed CMOS amplifier circuit are presented. The proposed circuit is simulated using 0.35 m process parameters. The configuration results in several performance improvements over a typical CMOS differential to single ended amplifier. Design details and simulation results show that the newly designed CMOS amplifier circuit and the high speed CMOS comparator are applicable to high speed analog subsystems, especially the flash A/D converter.     

The Concept of Operational Rank Extractor

An operational rank extractor (ORE) is introduced in this paper as an operational amplifier having rank extractors at its inputs. This versatile building block can implement a variety of nonlinear transfer functions such as a dead-zone amplifier, a limiter, a full-wave rectifier, and a tri-state comparator (including hysteretic behavior). A 6-input circuit has been implemented in a 2 m CMOS process. The total silicon area is 460 × 100m², and the circuit dissipates 0.7 mW from a single 5 V supply. Various circuit configurations are analyzed theoretically, and experimental results are also provided.     

Input/Output Rail-to-Rail CMOS Operational Amplifier with Shaped Common-Mode Response

This paper presents an input/output rail-to-rail class-AB CMOS operational amplifier with reduced variations in unity-gain frequency over the entire voltage range. The rail-to-rail amplifier input stage is based on two parallel-connected complementary differential pairs. Variations in the small-signal response are kept to a minimum by realizing an adequate shaping of the CM response of the input stage, while still reducing deviations in the total limiting current of the two input pairs with respect to traditional solutions. This is achieved independently of the g _m -I _D characteristic of the amplifier input devices and of any strict matching condition between the complementary input pairs. Experimental results from a 3-V 0.8-m CMOS test-chip are given.     

Very Low Voltage CMOS Current Multiplier with Floating DC Level Shifters

A compact, wide dynamic range, four-quadrant analog CMOS current multiplier is presented. The use of floating DC level shifters (floating batteries) made by resistors and current sources allows low supply voltages while maintaining at the same time a large input range and low harmonic distortion. Measurement results for an experimental prototype in a 0.8 m CMOS technology demonstrate on silicon the proposed technique.     

A CMOS transconductance element with improved DC gain and wide bandwidth for VHF applications

The design of a fully-differential, highly linear, voltage-tunable CMOS transconductance element with improved gain performance and wide bandwidth is described. A negative resistance technique for compensation of the parasitic output resistance of the transconductor circuit is employed without requiring extra internal nodes. As a result, dc-gain enhancement is obtained without any bandwidth penalty. SPICE simulations show that for a standard 3m CMOS technology with a power supply of ±5V, for most useful bias conditions THD is much lower than 1% for a 2V _RMS , 5MHz input sine wave; the tuning range of g _m is 36S to 265S. Finally the improved transconductance circuit is presented with an application to a transconductance-capacitor integrator with several tens of megahertz bandwidth.This work was supported in part by the State Scientific Research Committee, Poland, Grant No.8 S501 024 07, and by the National Science Foundation, USA, Grant No. MIP 91-21360.     

A nonvolatile analog neural memory using floating-gate MOS transistors

Simple floating-gate transistors fabricated by a conventional double-polysilicon process show excellent programming and charge-retention characteristics. A five-transistor synapse cell achieves 8-bit resolution and at least 6-bit accuracy for analog neural computation. It occupies 67 m×73 m in a 2-m CMOS process and can retain charge accuracy for over 25 years.This research was partially supported by DARPA under Contracts MDA972-90-C-0037 and MDA972-88-C-0048 and by TRW, Inc.     

A Very Low Voltage Bipolar Op-Amp for Sensor Applications

A new bipolar four-quadrant operational amplifier operating at a power supply voltage of 0.8 V and with a supply current of 800 A is here presented and illustrated. It features low input offset, low bias current, low noise, low crossover distortion and a rail-to-rail output swing. Control circuits ensuring minimum and maximum current limits for the output transistors have been incorporated. The biasing circuitry follows a PTAT scheme. A simple compensation topology allows the reduction of the area. The chip, whose area is about 2 mm², has been fabricated in HF2CMOS 2 /6 GHz technology. Finally, Spice simulations and experimental results, which confirm the expected overall performances of the low voltage op-amp, are reported.     

Low-voltage CMOS subthreshold four-quadrant tripler

A CMOS four-quadrant tripler using transistors operated in the subthreshold region is presented. The goal of this circuit is to realize the product of three input signals. This circuit has been implemented in a 0.8 m single-poly double-metal n-well CMOS process. Experimental results show that for a power supply of ±1.5V, the linear input range of this tripler is within ±100mV with the linearity error less than 2%. The total harmonic distortion is less than 2.5% with input range up to ±100mV. The-3dB bandwidth of this tripler is measured to be about 700 kHz.     

Design and Analysis of On-Chip ESD Protection Circuit with Very Low Input Capacitance for High-Precision Analog Applications

An ESD protection design is proposed to solve the ESD protection challenge to the analog pins for high-frequency or current-mode applications. By including an efficient power-rails clamp circuit into the analog I/O pin, the device dimension (W/L) of ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (m/m) in a 0.35-m silicided CMOS process, but it can sustain the human-body-model (machine-model) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only 1.0 pF (including the bond pad capacitance) for high-frequency applications. A design model to find the optimized layout dimensions and spacings on the input ESD clamp devices has been also developed to keep the total input capacitance almost constant (within 1% variation), even if the analog input signal has a dynamic range of 1 V.     

An Implantable CMOS Amplifier for Nerve Signals

In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. The amplifier is constructed in a fully differential topology to maximize noise rejection. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved. A continuous-time current-steering offset-compensation technique is utilized in order to minimize the noise contribution and to minimize dynamic impact on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0.5 m CMOS single poly, n-well process. The prototype amplifier features a gain of 80 dB over a 10 kHz bandwidth, a CMRR of more than 87 dB and a PSRR greater than 84 dB. The equivalent input referred noise in the bandwidth of interest is 4.8 nV/ . The amplifier power consumption is 275 W, drawn from a power supply; V _DD = –V _SS = 1.5 V.     

RF CMOS Cells for Wireless Applications

There is increasing interest in the use of CMOS circuits for high frequency highly integrated wireless telecommunications systems. This paper presents the results of on-going work into the development of a cell library that includes many of the circuit elements required for the high frequency sub-systems of communications integrated circuits. The cell library studied included an RF control element, single ended Class A amplifier, RF isolator, and Gilbert cell mixer circuit topologies. Circuit design criteria and measurement results are presented. All cells were fabricated using standard 2.0, 1.2, and 0.8 m CMOS integrated circuit fabrication processes with no post-processing performed. The results indicate that 2.0 m CMOS can be used successfully up to approximately 250 MHz with 0.8 m cells useful up to approximately 1000 MHz.     

CMOS Front-end Amplifier Dedicated to Monitor Very Low Amplitude Signal from Implantable Sensors

We describe in this paper a low-noise, low-power and low-voltage analog front-end amplifier dedicated to very low amplitude signal recording and processing applications. Our main focus is acquiring action potentials from peripheral nerves to recuperate lost functions in paralyzed patients. Low noise and low DC offset are realized using Chopper stabilization (CHS) technique. In addition, due to the use of a rail-to-rail input stage, low power supply (1.8 V) and wide common mode input range (0–1.8 V) are achieved also. It features a gain of 51 dB and a bandwidth of 4.5 kHz. The equivalent input noise is about 56 nV/ . The proposed preamplifier includes a matching clock generator, a 4th order continuous-time low-pass filter and an instrumentation amplifier. The proposed design has been implemented in 0.35 m double-poly n-well CMOS process with an active die area of 450 × 1150 m². The total data acquisition device consumes only 775 W.