总剂量辐射下的NMOS/SOI器件背栅阈值电压漂移模型

SOI(绝缘体上硅)器件在总剂量辐照下的主要性能退化是由于SOI器件的背栅阈值电压漂移引起的背沟道漏电。本文首先采用二维有限元方法,对辐射在SOI器件的埋氧层中的感生氧化物电荷进行模拟,然后分析此氧化物电荷对器件的外部电学特性的影响,建立了器件在最劣偏置下辐射引起的背栅MOSFET的阈值电压漂移模型,提取背栅MOSFET受辐射影响参数,以用于在SOI电路设计中准确的评估辐射对SOI电路的影响。模拟数据和试验数据具有很好的一致性。     

纳米 MOSFET/SOI器件新结构

重点介绍器件进入纳米尺度后出现的MOSFET／SOI器件的新结构，如超薄SOI器件、双栅MOSFET、FinFET和应变沟道等SOI器件，并对它们的性能进行了分析。     

BJMOSFET 静态特性的解析模型及模拟分析

建立了新型半导体功率器件－双极型压控晶体管（BJMOSFET）的直流解析模型,通过提取模型参数,运用电路模拟软件PSPICE的多瞬态分析法对BJMOSFET的直流特性进行了模拟,分析得出这种新型器件在相同结构参数和同等外界条件下与传统MOSFET相比,电流密度提高30％－40％。     

深亚微米SOAN MOSFETs的高温应用分析与结构优化

在300-600K温度范围内分析并模拟了栅长为100nm的SOI(Silicon On Insulator)和SOAN(Silicon On Aluminum Nitride)MOSFETs的输出特性和有源区温度分布,得出了SOAN器件更适合高温应用的结论;针对高温应用环境,对SOAN器件结构参数及工艺参数进行优化,得出了各个参数的优化值,并使用优化后参数仿真CMOS反相器的瞬态特性,结果显示在环境温度为300K和500K时,SOAN CMOS门极延迟分别为19ps、25.5ps;而SOI CMOS的门极延迟在相同的温度下分别为28.5ps、35.5ps.     

SOI在高压器件中的应用

综述了绝缘层上的硅(SOI)材料在高压器件中的应用,分析了SOI高压器件的不同结构,并对现在最常用的RESURF LDMOS高压器件结构,以及不同器件参数对击穿电压的影响进行了分析和讨论.     

SOI光电子集成

SOI（Silicon-on-Insulator)光电子集成已成为十分引人注目的研究课题，其工艺与CMOS工艺完全兼容，可以实现低成本的SOI基整片集成光电子回路。本文综述了近几年来SOI集成光电子器件的发展以及一些最新的研究进展，着重分析几种最新型光无源器件的工作原理和结构，包括SOI光波导、SOI光波导耦合器、SOI光波导开关、相位阵列波导光栅（PAWG）、基于SOI的光探测器等，并介绍了中国科学院半导体所集成光电子国家重点实验室的研究进展。     

SOI技术优势及制造技术

介绍SOI器件结构,SOI优点,SOI制造方法;面对未来工艺设计竞争、挑战的思考。     

SOI的自加热效应与SOI新结构的研究

阐述了自加热效应产生的原因以及它对SOI电路的影响，并介绍了为克服自加热效应和满足某些特殊器件和电路的要求，国内外正在竞相探索研究的新型SOI结构，如SOIM，Silicon onAlN,GPSOI,SiCOI,GeSiOI,SON,SSOI等，结论SOI新结构制备工作，报道了SOI的自加热效应及其新结构的研究进展。     

SOI和应变Si的将来

利用SOI衬底生长部分／完全耗尽结构的晶体管或用应变沟道提高器件性能可制备出高性能CMOS逻辑器件；这两种方法均可用于CMOS结构，也可单独用于提高器件性能。将应变用于器件沟道，可将沟道迁移率提高50％，从而提高了器件电流。SOI晶体管的好     

Si-cap厚度对Si/SiGe/SOI量子阱p-FET电学性能的影响

本工作模拟仿真了Si/SiGe/SOI量子阱p-MOSFETs的电学性能,重点分析了Si-cap层厚度对Ge的层间互扩散的影响。依据本文的仿真模型,Si-cap层越薄,越有利于形成Si/SiGe突变异质结,并有利于形成势垒更深的量子阱,这有利于将更多的空穴限制在SiGe层中,而不是进入厚的Si-cap层中。空穴在SiGe层中的迁移率显著高于在Si-cap层中的迁移率,从而提高了器件性能。此外,较薄的Si-cap层有利于在SiGe层中形成更高的沟道电场,从而提高器件的开启电流。     

A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation

In this paper, we present the unique features exhibited by a modified asymmetrical double-gate (DG) silicon-on-insulator (SOI) MOSFET. The proposed structure is similar to that of the asymmetrical DG SOI MOSFET with the exception that the front gate consists of two materials. The resulting modified structure, i.e., a dual-material double-gate (DMDG) SOI MOSFET, exhibits significantly reduced short-channel effects (SCEs) when compared with the DG SOI MOSFET. SCEs in this structure have been studied by developing an analytical model. The model includes the calculation of the surface potential, electric field, threshold voltage, and drain-induced barrier lowering. A model for the drain current, transconductance, drain conductance, and voltage gain is also discussed. It is seen that SCEs in this structure are suppressed because of the perceivable step in the surface-potential profile, which screens the drain potential. We further demonstrate that the proposed DMDG structure provides a simultaneous increase in the transconductance and a decrease in the drain conductance when compared with the DG structure. The results predicted by the model are compared with those obtained by two-dimensional simulation to verify the accuracy of the proposed analytical model.     

Transfer of physically-based models from process to device simulations: Application to advanced SOI MOSFETs

Dopant implantation, followed by spike annealing is one of the main focus areas in the simulation of silicon processing due to its ability to form highly-activated ultra-shallow junctions. Coupled with the growing interest in the use of silicon-on-insulator (SOI) wafers, modelling and simulation of the influence of SOI structure on damage evolution and ultra-shallow junction formation on one hand, and on electrical MOSFET device characteristics on the other hand, are required.In this work, physically-based models of dopant implantation and diffusion, including amorphization, defect interactions and evolution, as well as dopant-defect interactions in both bulk silicon and SOI are integrated within a unique simulation tool to model the different physical mechanisms involved in the process of ultra-shallow junction formation.The application to 65 nm SOI MOSFET devices demonstrated the strong impact of the process simulation models on the simulated electrical device characteristics, in particular for both defect evolution and defect dopant interaction with the additional silicon/buried oxide (Si/BOX) interface. Simulation results of the threshold voltage (V_th) and the variation of the on- and off-state currents of the explored structures are in good agreement with experimental data and can provide important insight for optimizing the process in both bulk silicon and SOI technologies.     

SOI器件中浮体效应的研究进展

SOI（Silicon On Insulator）器件中氧化埋层的隔离作用带来的浮体效应，将显著地影响器件的性能。本文阐述了浮体效应产生的原因以及它对SOI器件和电路的影响，并从体接触和工艺角度两个方面介绍了目前国际上比较优异的抑制浮体效应的几种典型器件结构。     

全耗尽SOI MOSFET阈值电压解析模型

提出了一种简化的全耗尽SOIMOSFET闽值电压解析模型。该模型物理意义明确,形式简单,不需要非常复杂的计算。通过在不同条件下将本文的模拟结果和MEDICI模拟结果进行对比,验证了本模型的精确性。因此本模型对于器件物理特性的研究和工艺设计有很好的指导意义。     

Enhancement of adjustable threshold voltage range by substrate bias due to quantum confinement in ultrathin body SOI pMOSFETs

The body effect in ultrathin body (silicon-on-insulator) SOI MOSFETs has been investigated by experiments and modeling. It is demonstrated for the first time that the adjustable threshold voltage range by substrate bias is enhanced due to the quantum confinement effect in ultrathin body SOI. The enhancement ratio of the adjustable threshold voltage range in a 4.3-nm-thick SOI MOSFET compared to 11.7-nm-thick one is around 10%. This indicates that ultrathin body MOSFETs are useful not only for suppressing the short channel effects, but also for suppressing the off-leak current in the variable threshold CMOS scheme.     

Threshold voltage calculation in ultrathin-film SOI MOSFETs using the effective potential

The success of the effective potential method of including quantum confinement effects in simulations of MOSFETs is based on the ability to calculate ahead of time the extent of the Gaussian wave packet used to describe the electron. In the calculation of the Gaussian, the inversion layer is assumed to form in a triangular potential well, from which a suitable standard deviation can be obtained. The situation in an ultrathin silicon-on-insulator (SOI) MOSFET is slightly different, in that the potential well has a triangular bottom, but there is a significant contribution to the confinement from the rectangular barriers formed by the gate oxide and the buried oxide. For this more complex potential well, it is of interest to determine the range of applicability of the effective potential model with a constant standard deviation. In this paper, we include this effective potential model in Monte Carlo calculations of the threshold voltage of ultrathin SOI MOSFETs. We find that the effective potential recovers the expected trend in threshold voltage shift with decreasing silicon thickness, down to a thickness of approximately 3 nm.     

Silicon single electron transistors with SOI and MOSFET structures: the role of access resistances

Coulomb blockade has been widely reported in silicon and metallic structures without intentional tunnel barriers. In particular, a simple constriction in silicon-on-insulator (SOI) allows to build a three-terminal silicon single-electron transistor (SET) operating at moderate temperature. The key parameters are the access resistances confining the electrons and the size of the gate-channel overlap, which sets the Coulomb energy. Thin films of doped silicon with sheet resistance of a few tens of h/e/sup 2/ are well suited for fabricating optimized access resistances. Low doped extensions with typical resistivity 1000 /spl Omega//spl mu/m (at 300 K) are also good candidates. We illustrate this MOS-SET principle in SOI constriction and standard MOSFET of similar size. Although relying on different concepts, the ultimate MOSFET and MOS-SET are shown to be technologically close, differing mostly by the ratio between the channel resistance over the access resistance. Because this ratio is decreasing as the gate length shrinks, single electron effects should become more and more important at high temperature in the subthreshold regime of standard field effect transistor devices.     

Significant aspects of minority-carrier injection in dynamic-threshold SOI MOSFET at low-temperature

This paper demonstrates significant aspects of low-temperature minority-carrier injection in n-channel dynamic-threshold (DT) MOSFET having various silicon-on-insulator (SOI) layer thicknesses. Drain current vs. gate voltage and gate current vs. gate voltage characteristics are evaluated at temperatures ranging from 300 K to 30 K, and minority-carrier injection is characterized. Impacts of temperature, channel length, and silicon-on-insulator layer thickness on opposite drain current behavior are discussed by examining transconductance behavior.     

3-D Design and Analysis of Functional NEMS-gate MOSFETs and SETs

Nanoelectromechanical system (NEMS)-gate metal- oxide-semiconductor field effect transistor (MOSFET) and single- electron transistor (SET) structures are investigated by combining 3-D design and SPICE simulation. First, the metal gate is simulated by using a 3-D simulator, which enables to design realistic 3-D device structures, and its movement is studied for different design parameters. It is demonstrated that a low stiffness design of the structure is essential for a low-voltage actuation. Results are compared with theoretical numerical simulation and a tunable capacitor model is then embedded in a SPICE simulator and coupled either with a transistor model for MOS-NEMS or with a newly developed SET analytical model for SET-NEMS. It is shown that the use of NEMS membrane can add new functionalities to conventional MOSFET and SET, such as very abrupt switching of the current, which can break theoretical limits of MOSFET, or modulation of Coulomb oscillations governing SET characteristics