千兆位交换背板的测试

本文介绍了千兆位交换背板的测试系统。系统由背板、交换卡、线路卡和控制卡组成，可对交换背 板进行交换功能和传输功能的检测。经过实际运行和测试，证明了测试系统的交换能力达到了 Ｃｉｓｃｏ１２００８路由器的水平。     

DS12887时钟芯片及其在LED中的应用

本文介绍了兆位交换背板的测试系统。系统由背板、交换卡、线路卡和控制卡组成，可对交换北板进行交换功能和传输功能的检测。经过实际运行和测试，证明了测试系统的交换能力达到了Cisco12008路由器的水平。     

千兆位以太网技术

在计算机局域网中,以太网属于中、低速率的网络。目前,在构筑大规模LAN时,100Mbit／s的高速以太网已作为主干网得到普及。从用户角度来看,LAN将从单一的数据通信用的专用网扩展成为同时传送数据,话音和图像的多媒体通信网络。因此,网络必须向提供更高的带宽,更高的带宽利用率及更加灵活的扩展与升级能力方向发展,随着交换式以太网,100Mbit／S高速以太网技术的完善与成熟,网络业界对局域网技术进行了更深入的开发与研究,1996年5月成立的千兆位以太网联盟,帮助IEEE将以太网标准向千兆位速度扩展,推出了作为下一代主干网的…     

千兆位以太网技术

随着多媒体、因特网应用等各种信息业务的不断发展,速度更高更快的计算机、服务器等的大量涌现,以及越来越多的入网用户,局域网的业务量急剧增加,对带宽的要求也越来越高。虽然100BASE-T等主干局域网技术目前还具有极大优势,但随着对带宽越来越高的要求,人们同时也在寻求将ATM等革命性的技术引入局域网领域。由于ATM技术的复杂性、昂贵的建网费用以及额外的管理工具、培训和修改设计等因素,尽管它是一个非常优秀的解决方案,但对于大多数网络管理者来说它并不是一个性能价格比最优的方案。幸运的是,现在的以太网用户又多了项千兆位以太网技术可以选择了。     

GT-48300在千兆位以太网交换机中的应用

介绍了交叉交换矩阵GT-48300芯片的消息处理功能,提出了一种基于GT-48300的千兆位以太网交换机的构造方式。     

A gigabit multidrop serial backplane for high-speed digital systems based on asymmetrical power splitter

The maximum data rate in today's available multidrop backplanes is significantly limited due to signal integrity concerns. In this brief, a novel gigabit multidrop serial link configuration for high-speed digital systems based on newly developed asymmetrical broadband power splitters with matching trace impedance, is presented. The proposed power splitter features good impedance match at all ports without the insertion losses being inherent to common resistive power splitters. Experimental results obtained from implemented prototypes demonstrate a satisfactory operation of the proposed multidrop serial backplane for a data rate above 3.5 Gbps.     

Gunn device gigabit rate digital microcircuits

Monolithic integration of planar Gunn devices on GaAs is a very promising method to realize microcircuits for the Gbit/s range. Semiinsulating GaAs is readily available as substrate material. In this paper estimates of characteristic parameters of these circuits, such as maximum pulse rate, power consumption, and package density, are presented. Three different methods of domain control are available: a) by separate Schottky barrier diode; b) by MESFET; or c) by Schottky barrier gate on the channel of the Gunn device. Theoretical limits for these methods are given. Maximum pulse rates of 11, 5, and 7 Gbit/s, respectively, can be expected. Unidirectionality and trigger drive of the three methods are rated. Experimental integrated circuits were built to demonstrate the capability of the methods of domain control. Comparison with calculations yields good agreement. Coming close to the theoretical limits has not yet been accomplished in all practical cases since further miniaturization of the circuits and improvement of the material properties relevant to domain processes is needed. After progress in these two points it is expected that the theoretical limits will be reached.     

Ultralow error rate and dispersion-free transmission of 2.5 Gbit/s SONET for gigabit networks

It is demonstrated that for an NRZ modulated 1310 nm optical transmitter, dispersion-free transmission can be achieved up to approximately 250 km using dispersion-shifted singlemode fibre (DS-SMF) and optical pulse compression. This result implies that DS-SMFs have a potential advantage over standard SMFs for dual-window (1310/1550 nm) multigigabit per second transmission systems. Results on the long-term error performance of experimental prototype 2.5 Gbit/s SONET optical transmission systems are presented with measured error rates smaller than 10/sup -15/.<>     

DFE architectures for high-speed backplane applications

Embedded and look-ahead decision feedback equalisation (DFE) architectures are proposed to overcome the speed bottleneck of DFE design for high-speed backplane applications. DFE design examples simulated in 0.18 /spl mu/m CMOS technology demonstrate the feasibility of 10Gbit/s operation over a 34-inch FR4 backplane.     

DRAM technology perspective for gigabit era

Many challenges emerge as the DRAM enters into a generation of the gigabit density era. Most of the challenges come from the shrink technology which scales down minimum feature size by a factor of 0.84 per year. The need for higher performance to narrow the bandwidth mismatch between fast processors and slower memories and lower power consumption drives the DRAM technology toward smaller cell size, faster memory cell operation, less power consumption, and longer data retention times. In addition, increasingly complicated wafer processing requires simple process. In this paper, the challenges brought from the extremely small minimum feature, high performance, and simple wafer processing will be discussed. The solutions to overcome the challenges will be described focusing on the memory cell scheme, lithography, device, memory cell capacitor, and metallization     

The infrastructure for gigabit computer networks

The key features of the synchronous optical network (SONET) and asynchronous transfer mode (ATM) standards for the broadband integrated services digital network (B-ISDN) public network, which is expected to provide a powerful and ubiquitous infrastructure to support the emerging gigabit-per-second data and multimedia applications, are reviewed. The advantages of ATM, the ATM cell format, the B-ISDN protocol reference model and the ATM layer, the ATM adaptation layer, and ATM traffic management and signaling are discussed. An experimental high-performance parallel interface (HIPPI)-ATM-SONET interface is presented as an example to illustrate how the SONET and ATM techniques can be used to provide end-to-end transport for applications requiring a bandwidth of 800 Mb/s and possibly 1600 Mb/s     

背板加工技术简述

背板作为印制电路板的一种,因其结构特性、应用领域等,挑战常规印制电路板多项加工技术。本文浅谈背板加工流程之压合层间对准度、钻孔背钻、孔金属化深镀能力及最终表面工艺方面的技术及控制项,供同行参考与借鉴。     

VISTAnet gigabit testbed

The VISTAnet gigabit testbed project features the deployment of a network connecting distant supercomputers and research programs in communications, advanced graphics techniques, and a medical application. It has been established to experiment with and evaluate techniques associated with gigabit networking. The testbed goals, infrastructure, and driving applications are described. Early insights from the testbed activities are presented to identify important problems associated with networked supercomputers and their impact on public broadband integrated services digital networks. The conflict between the performance needs of supercomputer communications and the constraints of cell-oriented communications are identified and discussed. The concepts of metacomputing are introduced along with their network implications. The metacomputing model is applied to the VISTAnet application to illustrate these points     

GaAs MESFET ICs for gigabit logic applications

This paper gives an overview of the basic concepts used in the design and fabrication of gallium arsenide MESFET integrated circuits intended for gigabit logic applications. The present status of speed-power performances, packing densities, and integration levels is presented on the basis of some MSI and LSI MESFET IC realizations made possible by the principal GaAs logic approaches to date. Finally, the potential field of application and future trends of GaAs IC technology are assessed.