A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end

A fully integrated 10-Gb/s optical receiver analog front-end (AFE) design that includes a transimpedance amplifier (TIA) and a limiting amplifier (LA) is demonstrated to require less chip area and is suitable for both low-cost and low-voltage applications. The AFE is fabricated using a 0.18-/spl mu/m CMOS technology. The tiny photo current received by the receiver AFE is amplified to a differential voltage swing of 400 mV/sub (pp)/. In order to avoid off-chip noise interference, the TIA and LA are dc-coupled on the chip instead of ac-coupled though a large external capacitor. The receiver front-end provides a conversion gain of up to 87 dB/spl Omega/ and -3dB bandwidth of 7.6 GHz. The measured sensitivity of the optical receiver is -12dBm at a bit-error rate of 10/sup -12/ with a 2/sup 31/-1 pseudorandom test pattern. Three-dimensional symmetric transformers are utilized in the AFE design for bandwidth enhancement. Operating under a 1.8-V supply, the power dissipation is 210 mW, and the chip size is 1028 /spl mu/m/spl times/1796 /spl mu/m.     

A fully integrated SiGe receiver IC for 10-Gb/s data rate

A silicon germanium (SiGe) receiver IC is presented here which integrates most of the 10-Gb/s SONET receiver functions. The receiver combines an automatic gain control and clock and data recovery circuit (CDR) with a binary-type phase-locked loop, 1:8 demultiplexer, and a 2 ⁷-1 pseudorandom bit sequence generator for self-testing. This work demonstrates a higher level of integration compared to other silicon designs as well as a CDR with SONET-compliant jitter characteristics. The receiver has a die size of 4.5×4.5 mm2 and consumes 4.5 W from -5 V     

Improved sideband suppression of optical SSB modulation usingall-optical Hilbert transformer

A novel optical single-sideband (SSB) modulation system using an all-optical Hilbert transformer is proposed. The sideband suppression characteristics are analysed and compared with a conventional system using an electrical transformer. The side-lobe to main-lobe peak suppression ratio exceeding 40 to 60 dB is shown, significantly outperforming the conventional system     

An integrated direct-coupled 10-Gb/s driver for common-cathode VCSELs

An all- npn integrated driver for directly modulating common-cathode vertical-cavity surface-emitting lasers (VCSELs) at high speeds (such as 10 Gb/s) is proposed and experimentally demonstrated. Special biasing techniques allow the output transistors to operate with small collector-emitter voltages while maintaining their fast current-switching capabilities. A current-splitting technique in the output stage minimizes the transients through the bias source and reduces jitter and overshoot.     

2.5-Gb/s low-jitter low-power monolithically integrated optical receiver

A high-scale integrated optical receiver including a preamplifier, a limiting amplifier, a clock and data recovery (CDR) block, and a 1:4 demultiplexer (DEMUX) has been realized in a 0.25???m CMOS technology. Using the loop parameter optimization method and the low-jitter circuit design technique, the rms and peak-to-peak jitter of the recovered 625-MHz clock are 9.4 and 46.3?ps, respectively, which meet the jitter specifications stipulated in ITU-T recommendation G.958. The recovered and frequency divided 625?MHz clock has a phase noise of ?83.8 dBc/Hz at 20?kHz offset in response to 2.5?Gb/s PRBS input data (2²³?C1), and the 2.5?Gb/s PRBS data has been demultiplexed into four 625?Mb/s data. The power dissipation is only 0.3?W under a single 3.3 V supply (excluding output buffers).     

Si bipolar chip set for 10-Gb/s optical receiver

Three Si bipolar ICs, a preamplifier, a gain-controllable amplifier, and a decision circuit, have been developed for 10-Gb/s optical receivers. A dual-feedback configuration with a phase adjustment capacitor makes it possible to increase the preamplifier bandwidth up to 11.2 GHz, while still retaining flat frequency response. The gain-controllable amplifier, which utilizes a current-dividing amplifier stage, has an 11.4-GHz bandwidth with 20-dB gain variation. A master-slave D-type flip-flop is also operated as the decision circuit at 10 Gb/s. On-chip coplanar lines were applied to minimize the electrical reflection between the ICs     

A 25-Gb/s inductorless SiGe BiCMOS receiver for 100-Gb/s optical links

This paper presents the design and measurements of a 25-Gb/s inductorless optical receiver in a 0.25-μm SiGe BiCMOS process for 100-Gb/s (25-Gb/s × 4 lines) Ethernet. As the first stage of the proposed optical receiver, a transimpedance amplifier (TIA) employing a pseudo-differential structure with a feedback resistor incorporates DC offset cancellation (DOC) to enhance the input dynamic range. Cascaded by the improved two-stage limiting amplifiers and a 50-Ω output buffer, the receiver achieves high differential swings. For a bit-error rate (BER) of 10⁻¹² at 25 Gb/s, the measured transimpedance gain, bandwidth, sensitivity, and output swing are 63.17 dBΩ, 20.7 GHz, −10.3 dBm, and 352.7 mV, respectively. The power consumption of the entire receiver is 111.6 mW and the core area of the die is 640 μm × 135 μm.     

Low-power fully integrated 10-Gb/s SONET/SDH transceiver in 0.13-/spl mu/m CMOS

Here, we present a low-power fully integrated 10-Gb/s transceiver in 0.13-/spl mu/m CMOS. This transceiver comprises full transmit and receive functions, including 1:16 multiplex and demultiplex functions, high-sensitivity limiting amplifier, on-chip 10-GHz clock synthesizer, clock-data recovery, 10-GHz data and clock drivers, and an SFI-4 compliant 16-bit LVDS interface. The transceiver exceeds all SONET/SDH (OC-192/STM-64) jitter requirements with significant margin: receiver high-frequency jitter tolerance exceeds 0.3 UI/sub pp/ and transmitter jitter generation is 30 mUI/sub pp/. All functionality and specifications (core and I/O) are achieved with power dissipation of less than 1 W.     

A 3-V fully differential distributed limiting driver for 40-Gb/s optical transmission systems

A fully differential 40-Gb/s electro-absorption modulator driver is presented. Based on a distributed limiting architecture, the circuit can supply up to 3.0-V/sub pp/ (peak-to-peak) per side in a 50-/spl Omega/ load at data rates as high as 44 Gb/s. Both the input and the output are internally matched to 50 /spl Omega/ and exhibit return loss of better than 10 dB up to 50 GHz. Additional features of the driver include the use of a single -5.2-V supply, output swing control (1.7-3.0-V/sub pp/ per side), dc output offset control (-0.15 V to -1.1 V), and pulsewidth control (30% to 66%). The driver architecture was optimized based on a comprehensive analytical derivation of the frequency response of cascaded source-coupled field-effect transistor logic blocks using both single and double source-follower topologies.     

10-Gb/s external modulation in optical CPFSK format

We demonstrated a synchronous control technique for external optical modulation in a format of continuous-phase frequency-shift keying (CPFSK) at 10 Gb/s. In this method, the FSK signal in the upper- or lower-sideband state synchronously shifts to the other state at the timing when their phases are the same. We investigated the accuracy of the timing control required for the synchronous control. Experimental results show that the allowable timing misalignment to keep power penalty of the receiver sensitivity less than 1 dB was more than 25 ps, 25% of each bit period.     

Integrated optical architectures for tapped delay lines

An integrated optics (IO) device that is an implementation of an IO tapped delay line is discussed. It is capable of performing discrete convolution of an optical pulse sequence with a preset digital function. Several architectures for the device are presented. A systematic realization of the preset function samples that permits efficient utilization of all the input light power and maximization of the output signal-to-noise ratio (SNR) for the device is discussed. A detailed analysis of what determines the number of preset samples that can be realized and how to realize them on a LiNbO₃ crystal is given. Two digital filter design examples are presented, and the quantization error effects on their performance are examined. The same architectures are shown to implement digital-to-analog (D/A) conversion and systolic multiplication of a Toeplitz matrix with a vector having the form of optical pulses     

A wide-dynamic-range, high-transimpedance Si bipolar preamplifierIC for 10-Gb/s optical fiber links

A wide-dynamic-range, high-transimpedance preamplifier IC for 10-Gb/s optical fiber links was developed using a 0.3-μm Si bipolar process. The preamplifier with a limiting amplifier enables a wide dynamic range from 16 μApp to 2.5 mApp and a high transimpedance of 1 kΩ (2 kΩ in the differential output mode). Moreover, careful circuit design achieves a transimpedance fluctuation of 0.5 dBR and an average equivalent input noise current density of 12 pA/√Hz. This preamplifier IC has the highest transimpedance of any Si bipolar preamplifier for 10-Gb/s operation. Thus, the preamplifier is suitable for 10-Gb/s short-haul optical fiber links and can be used to provide a low-cost system     

A CMOS multichannel 10-Gb/s transceiver

We describe a CMOS multichannel transceiver that transmits and receives 10 Gb/s per channel over balanced copper media. The transceiver consists of two identical 10-Gb/s modules. Each module operates off a single 1.2-V supply and has a single 5-GHz phase-locked loop to supply a reference clock to two transmitter (Tx) channels and two receiver (Rx) channels. To track the input-signal phase, the Rx channel has a clock recovery unit (CRU), which uses a phase-interpolator-based timing generator and digital loop filter. The CRU can adjust the recovered clock phase with a resolution of 1.56 ps. Two sets of two-channel transceiver units were fabricated in 0.11-/spl mu/m CMOS on a single test chip. The transceiver unit size was 1.6 mm /spl times/ 2.6 mm. The Rx sensitivity was 120-mVp-p differential with a 70-ps phase margin for a common-mode voltage ranging from 0.6 to 1.0 V. The evaluated jitter tolerance curve met the OC-192 specification.     

A monolithically integrated 1-Gb/s optical receiver in 1-μm CMOStechnology

Results of a monolithically integrated Si optical receiver for applications in optical data transmission and in optical interconnects with wavelengths of 638 and 850 nm are presented. The optoelectronic integrated circuit (OEIC) implementing a vertical p-type-intrinsic-n-type photodiode achieves a data rate of 1 Gb/s for 638 nm with a sensitivity of -15.4 dBm at a bit-error rate of 10^-9 . The sensitivity of this OEIC in a 1.0-μm CMOS technology is improved by at least a factor of four compared to that of published submicrometer OEICs. A 25-THz.Ω effective transimpedance bandwidth product of the implemented amplifier is achieved     

10- and 40-Gb/s forward error correction devices for optical communications

Two standard forward error correction (FEC) devices for 10- and 40-Gb/s optical systems are presented. The first FEC device includes RS(255, 239) FEC, BCH(4359, 4320) FEC, and standard compliant framing and performance monitoring functions. It can support a single 10-Gb/s channel or four asynchronous 2.5-Gb/s channels. The second FEC device implements RS(255, 239) FEC at a data rate of 40 Gb/s. This paper presents the key ideas applied to the design of Reed-Solomon (RS) decoder blocks in these devices, especially those for achieving high throughput and reducing complexity and power. Implemented in a 1.5-V, 0.16-/spl mu/m CMOS technology, the RS decoder in the 10-Gb/s, quad 2.5-Gb/s device has a core gate count of 424 K and consumes 343 mW; the 40-Gb/s RS decoder has a core gate count of 364 K and an estimated power consumption of 360 mW. The 40-Gb/s RS FEC is the highest throughput implementation reported to date.     

Orthogonally polarized RF optical single sideband generation with integrated ring resonators

We review recent work on narrowband orthogonally polarized optical RF single sideband generators as well as dualchannel equalization,both based on high-Q integrated ring resonators.The devices operate in the optical telecommunications C-band and enable RF operation over a range of either fixed or thermally tuneable frequencies.They operate via TE/TM mode birefringence in the resonator.We achieve a very large dynamic tuning range of over 55 dB for both the optical carrier-to-sideband ratio and the dual-channel RF equalization for both the fixed and tunable devices.     

Optical single sideband transmission at 10 Gb/s using onlyelectrical dispersion compensation

A system is presented which uses optical single sideband transmission at 10 Gb/s together with electrical dispersion compensation at the receiver. Transmission with a bit error rate better than 10^-10 on nondispersion shifted fiber is experimentally demonstrated over 320 km and the dispersion from 1000 km of fiber was effectively equalized in simulation. In the transmitter, driving one or two modulators with a combination of a baseband digital signal and the Hilbert transform of that signal creates an optical single sideband signal. In terms of reducing the effects of chromatic dispersion, transmitting the signal in a single sideband format has two advantages over a double sideband format. First, the optical bandwidth of the transmitted single sideband signal is approximately one half of a conventional double sideband signal. Second, an optical single sideband signal with transmitted carrier can be “self-homodyne” detected and the majority of the phase information preserved since no spectrum back folding occurs upon detection. This allows the received signal to be partially equalized in the electrical domain     

A 10-Gb/s silicon bipolar IC for PRBS testing

A 10 Gb/s silicon bipolar IC for pseudorandom binary sequence (PRBS) testing was fabricated and tested. The IC features PRBS generation of the sequences of length 2¹⁵-1 and 2²³-1 b up to 10 Gb/s according to CCITT recommendations. Furthermore, the IC is capable of analyzing PRB sequences of the same length and generation polynomials so that a full test of components is possible. In addition, a new PRBS test word synchronization can be provided between two chips for external multiplexing of the sequences up to 40 Gb/s. The IC can be connected to a standard PC, so evaluation of the error test data can be performed in a flexible way. The IC was fabricated with the HP25 process of Hewlett Packard company, the chip size is 32 mm², and it consumes 6.2 W at the nominal supply voltage of -5 V     

10-Gb/s transmission and beyond

The authors outline obstacles encountered in the development of 10-Gb/s (STM-64, OC-192) systems. Technologies to overcome these obstacles are presented and compared, taking into account real field environments. A perspective on 40-Gb/s systems technologies is also given