Reliable CAD Analyses of CMOS Radio Frequency and Microwave Circuits Using Smoothed Gate Capacitance Models

The problems with convergence caused by both voltage- and charge-controlled models of MOSFET gate capacitances are often a limiting factor of the computer aided design tools. In the paper, an idea of the exponential smoothing of model discontinuities is proposed. The method is demonstrated on smoothing the gate capacitance discontinuity at zero drain-source voltage. An advanced integration algorithm convenient for the computer aided design of radio frequency and microwave CMOS circuits suppressing possible physically incorrect results of the traditional methods is also described. The updated model and algorithm are checked by analyzing a sophisticated CMOS flip-flop circuit.     

Hierarchical interconnection structures for field programmable gatearrays

Field programmable gate arrays (FPGA's) suffer from lower density and lower performance than conventional gate arrays. Hierarchical interconnection structures for field programmable gate arrays are proposed. They help overcome these problems. Logic blocks in a field programmable gate array are grouped into clusters. Clusters are then recursively grouped together. To obtain the optimal hierarchical structure with high performance and high density, various hierarchical structures with the same routability are discussed. The field programmable gate arrays with new architecture can be efficiently configured with existing computer aided design algorithms. The k-way min-cut algorithm is applicable to the placement step in the implementation. Global routing paths in a field programmable gate array can be obtained easily. The placement and global routing steps can be performed simultaneously. Experiments on benchmark circuits show that density and performance are significantly improved     

Design of active phase shifters based on multichannelheterojunction field effect transistors (MCHFET's)

Design criteria of active phase shifters based on GaAs/AlGaAs multichannel (MC) HFET in the frequency range 4-60 GHz are presented. The phase characteristics of MCHFET devices were studied using the computer aided design program TOUCHSTONE. The dependence of transmission phase on various intrinsic elements in the equivalent circuit model as a function of control gate bias was also studied. There are limited gate bias ranges which correspond to the active regions of the two conducting wells for which a quasi-linear continuous phase shift for analog applications was achieved. Continuously varying the gate bias from V_gs=-1.9 V to V_gs=-0.6 V results in a quasilinear phase shift of 10°, 15°, 21°, and 29° at f=12, 20, 30, and 60 GHz, respectively. Similarly, varying the gate bias from V_gs =-0.4 V to V_gs=0.7 V a quasi-linear phase shift of 21°, 26°, 27°, and 23° at f=12, 20, 30, and 60 GHz, respectively, was achieved. The gain variation was less than 3 dB in these bias regions. With digital applications in mind, a maximum differential phase shift of around 50° was obtained by switching the gate bias discretely. The transmission phase of single gate MCHFET mostly depends on variation of gate source capacitance with gate bias rather than on other intrinsic elements. The dependence of phase shift on various geometrical and structural parameters is also presented. To test the practicality of the device, other scattering parameters (e.g., S₁₁, S₂₂, S₁₂) and the noise figure (NF) were finally studied     

RAPID PROTOTYPING - Field programmable gate array based parallel matrix multiplier for 3D affine transformations

3D graphics performance is increasing faster than any other computing application. Almost all PC systems now include 3D graphics accelerators for games, computer aided design or visualisation applications. This article investigates the suitability of field programmable gate array devices as an accelerator for implementing 3D affine transformations. Proposed solution based on processing large matrix multiplication have been implemented, for large 3D models, on the RC1000 Celoxica board based development platform using Handel-C. Outstanding results have been obtained for the acceleration of 3D transformations using fixed and floating-point arithmetic     

不同栅压应力下1.8V pMOS热载流子退化机理研究

本文详细研究了不同栅压应力下1.8V pMOS器件的热载流子退化机理.研究结果表明,随着栅压应力增加,电子注入机制逐渐转化为空穴注入机制,使得pMOS漏极饱和电流(I_dsat)、漏极线性电流(I_dlin)及阈值电压(V_th)等性能参数退化量逐渐增加,但在V_gs=90%*V_ds时,因为没有载流子注入栅氧层,使得退化趋势出现转折.此外,研究还发现,界面态位于耗尽区时对空穴迁移率的影响小于其位于非耗尽区时的影响,致使正向I_dsat退化小于反向I_dsat退化,然而,正反向I_dlin退化却相同,这是因为I_dlin状态下器件整个沟道区均处于非耗尽状态.     

用于T形栅光刻的新型移相掩模技术

根据移相掩模基本原理,通过光刻工艺模拟提出了一种适于T形栅光刻的新型移相掩模技术——M-PEL。初步实验证明,M-PEL技术可在单层厚胶上经一次光刻形成理想的T形栅抗蚀剂形貌。     

An efficient memristor crossbar architecture for mapping Boolean functions using Binary Decision Diagrams (BDD)

The memristor is considered as the fourth fundamental circuit element along with resistor, capacitor and inductor. It is a two-terminal passive circuit element whose resistance value changes based on the amount of charge flowing through it. Another property of the memristor is that its resistance change is non-volatile in nature, and hence can be used for non-volatile memory applications. Researchers have been exploring memristors from various perspectives such as logic design and storage applications. In this paper, a slicing crossbar architecture for the efficient mapping of Boolean functions is proposed which exploits gate level parallelism using the memristor aided logic (MAGIC) design style. A Boolean function is first represented as a Binary Decision Diagram (BDD). The BDD nodes are expressed as netlists of NOR and NOT gates, and are mapped to the proposed slicing crossbar architecture with parallel node evaluation where possible. This is the first approach that combines BDD-based synthesis with MAGIC gate evaluation on memristor crossbar, while at the same time avoiding crossbar-related problems using a slicing architecture. Experimental evaluations on standard benchmark functions show considerable improvement in the solutions.     

Enhanced heterostructure field effect transistor CAD model suitablefor simulation of mixed mode circuits

We describe a new enhanced model for deep submicron heterostructure field effect transistors (HFET's) suitable for implementation in computer aided design (CAD) software packages such as SPICE. The model accurately reproduces both above-threshold and subthreshold characteristics of both n- and p-channel deep submicron HFET's over the temperature range 250-450 K. The current-voltage (I-V) characteristics are described by a single, continuous, analytical expression for all regimes of operation, thereby improving convergence. The physics-based model includes effects such as velocity saturation in the channel, drain-induced barrier lowering (DIBL), finite output conductance in saturation, frequency dispersion, and temperature dependence. The output resistance and the transconductance are accurately reproduced, making the model suitable for simulation of mixed mode (digital/analog) circuits. The model has been extensively verified against experimental data for two HFET technologies with gate lengths down to 0.3 μm     

GaAs MESFET circuit simulation model including negative differential mobility

A simple one-dimensional GaAs MESFET model for circuit simulation is presented which takes into account negative differential mobility. In this model, the drain current is derived from the electric field strength at the source side edge under the gate using a gradual depletion layer approximation. The calculated I/V characteristics agree well with the experimental data for GaAs power MESFETs, which show negative differential resistances. The proposed model can be used in computer aided design of GaAs integrated circuits and amplifiers with the great advantage of a small calculation time compared with that of 2-dimensional analysis.     

Design and characteristics of a lightly doped drain (LDD) device fabricated with self-aligned titanium disilicide

An As-P double-diffused lightly doped drain (LDD) device has been designed and fabricated with a self-aligned titanium disilicide process. The device design was aided by using an analytical one-dimensional model, and analytic results agree well with experimental data on the avalanche breakdown voltage gain and the ratio of substrate current to source current. Threshold voltage and subthreshold characteristics of this device do not deviate from those of a conventional device without LDD and silicide. The drain avalanche breakdown voltage of the LDD device is higher by 2.5 V over the conventional device. Transconductance degradation was observed for the LDD devices due to the inherently high source-drain series resistance of the LDD structure. Substrate current is reduced and hot-electron reliability is greatly improved. The titanium disilicide process effectively reduces the sheet resistances of the source-drain diffusion and the polysilicon gate to 3 Ω/sq compared with 150 Ω/sq of the unsilicided counterparts. It is also found that larger polysilicon grain size increases the sheet resistance of the silicide gate due to discontinuous titanium disilicide formation on top of polysilicon.     

Statistical design of experiments and analysis on gate poly-silicon critical dimension

Gate poly-silicon critical dimension is one of the most important characteristics of up-to-date integrated circuit devices. Hence, in a semiconductor wafer fabrication process, gate poly-silicon critical dimension control is inevitable in order to achieve a competitive net-die-per-wafer yield as well as electrically acceptable device test characteristics. This paper presents a framework for statistical design of experiments and analysis on gate poly-silicon critical dimension. Three typical types of design of experiments are considered: 1) a nested design; 2) a randomized complete block design; and 3) a factorial design. With these designs, relevant linear statistical models are established. Based on the models, the analysis of variance technique and Duncan's multiple range tests are chosen as major methodologies not only to estimate related variance components but also to test uniformity on gate poly-silicon critical dimension. Statistical analyses are illustrated with experimental datasets from real pilot semiconductor wafer fabrication processes. Results show that: 1) according to the sources of variation, variance components are estimated separately, and 2) distinctive patterns of gate poly-silicon critical dimension can be detected with statistical significance. Consequently, the framework in this study can provide guidelines to practitioners on the variance components estimation as well as the uniformity test in parallel for any characteristic datasets collected from similar designs in a semiconductor wafer fabrication process.     

设计中计算机辅助设计软件的联合应用研究

随着计算机技术的发展中,计算机辅助设计软件在许多企业中得到了广泛应用,但是依赖单一一种设计软件存在着很大的弊端,所以对设计中计算机辅助设计软件的联合应用进行研究.首先对计算机辅助软件优势以及联合流程进行分析,并且对计算机辅助软件数据传输技术与计算机辅助软件的实际应用做出研究,结合Por/E、Optistruct以及Ansys三种软件的优势,在设计中联合应用能够有效保证数据间的传输,减少结构的最大应力和变形,促进结构优化.     

Analytical modeling and simulation of germanium single gate silicon on insulator TFET

This paper proposes a new two dimensional（2D） analytical model for a germanium（Ge） single gate silicon-on-insulator tunnel field effect transistor（SG SOI TFET）. The parabolic approximation technique is used to solve the 2D Poisson equation with suitable boundary conditions and analytical expressions are derived for the surfacepotential,theelectricfieldalongthechannelandtheverticalelectricfield.Thedeviceoutputtunnellingcurrent is derived further by using the electric fields. The results show that Ge based TFETs have significant improvements inon-currentcharacteristics.Theeffectivenessoftheproposedmodelhasbeenverifiedbycomparingtheanalytical model results with the technology computer aided design（TCAD） simulation results and also comparing them with results from a silicon based TFET.     

TCAD Assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and Its Multilayered Gate Architecture—Part I: Hot-Carrier-Reliability Evaluation

This paper discusses a hot-carrier-reliability assessment, using ATLAS device simulation software, of a gate electrode workfunction engineered recessed channel (GEWE-RC) MOSFET involving an RC and GEWE design integrated onto a conventional MOSFET. Furthermore, the impact of gate stack architecture and structural design parameters, such as gate length, negative junction depth, substrate doping (NA), gate metal workfunction, substrate bias, drain bias, and gate oxide permittivity on the device behavior of GEWE-RC MOSFET, is studied in terms of its hot-carrier behavior in Part I. Part II focuses on the analog performance and large signal performance metrics evaluation in terms of linearity metrics, intermodulation distortion, device efficiency and speed-to-power dissipation design parameters, and the impact of gate stack architecture and structural design parameters on the device reliability. TCAD simulations in Part I reveal the reduction in hot-carrier-reliability metrics such as conduction band offset, electron velocity, electron temperature, hot-electron-injected gate current, and impact-ionization substrate current. This paper thus optimizes and predicts the feasibility of a novel design, i.e., GEWE-RC MOSFET for high-performance applications where device and hot-carrier reliability is a major concern.     

Influences of structure around gate-edge on high electric field strength in MISFETs with high-k gate dielectrics

In this paper, dependences of electric field strength around gate-edge in gate dielectrics of MISFETs with high-k gate dielectrics on design parameters are studied. It is newly found that locations of sidewall/gate dielectric interfaces relative to gate electrode edges are critical to electric field strength of high-k MISFETs. Electric field can be as high as 4 MV/cm, which could have large influences on the yield of large scale integrated circuits (LSIs) with high-k gate dielectrics. An explanation of this phenomenon is given by considering discontinuity in electric field at interfaces between two materials with different dielectric constants. It is clarified that an electrical potential of side and top surfaces of gate dielectrics is strongly affected by the discontinuity of electric field strength at interfaces. As a result, electric field strength around gate electrode edges critically depends on locations of sidewall/gate dielectrics interfaces relative to gate electrode edges. Based on the physical considerations, a structure, in which gate sidewalls are also made of high-k materials, is studied from the viewpoint of electric field strength around gate electrode edges. It is shown that this structure effectively suppresses electric field strength around gate edges.     

GaN/AlGaN p-channel inverted heterostructure JFET

A novel GaN/AlGaN p-channel inverted heterostructure junction field-effect transistor (HJFET) with a n/sup +/-type gate is proposed and demonstrated. A new superlattice aided strain compensation techniques was used for fabricating high quality GaN/AlGaN p-n junction. The p-channel HJFET gate leakage current was below 10 nA, and the threshold voltage was 8 V, which is close to that of typical n-channel HFETs. This new HJFET device opens up a way for fabricating nitride based complimentary integrated circuits.     

差分混沌通信研究综述:信号设计与性能优化

作为一种低复杂度的非相干信息传输方案,差分混沌通信系统以其良好的抗多径衰落性能而受到广泛关注。近年来,研究者围绕着以差分混沌移位键控(DCSK)为代表的差分混沌通信开展了一系列富有成效的研究,逐渐发展了差分混沌通信的信号设计与性能优化方法。为此,该文从信号帧结构设计、正交多级信号设计、信号星座图设计和多载波信号设计4个层面详细综述了差分混沌通信信号设计的主要研究进展。此外,该文重点总结了面向差分混沌通信的噪声抑制辅助性能优化、索引调制辅助性能优化和混沌成形滤波辅助性能优化等方面的研究工作。     

论计算机辅助设计在艺术设计专业教学中的应用

计算机技术的发展促进了计算机应用的广泛化.如今计算机更是凭借其先进的辅助设计、过程模拟等技术被应用到各行各业当中,对其工作效率的提升起到了很好的促进作用.为此,本文以计算机辅助设计在艺术设计专业教学中的应用为研究对象,通过对计算机辅助设计在艺术设计专业教学中重要性的分析,探寻了计算机辅助设计在艺术设计专业教学中应用的发展之路.     

20万门CMOS门阵列设计技术

本文主要介绍0.8umCMOS门阵列的设计技术,包括建库技术,可测性设计技术、时钟设计技术、电源、地设计技术、电路结构优化、余量设计技术等,最后介绍了20万门母片及电路的主要参数。     

亚微米门阵列ASIC设计技术

本文主要论述亚微米CMOS门阵列的设计技术,包括建库技术,可测性设计技术、时钟设计技术、电源、地设计技术、电路结构优化、余量设计技术等,最后给出了应用实例。