A CMOS self-calibrating frequency synthesizer

A programmable phase-locked-loop (PLL)-based frequency synthesizer, capable of automatically adjusting the nominal center frequency of the voltage-controlled oscillator (VCO) to an optimum value is described. In fully integrated PLLs, the VCO output frequency should be tunable over a wide range of frequencies, covering the desired range of the synthesizer output frequencies, for all processing variations and operating conditions. A wide tuning range realized by making the VCO gain K_o large has the unwanted effect of increasing the phase noise at the output of the VCO, and hence the PLL as well. In this work, the wide tuning range is realized by digital control, with process variability managed through self-calibration. The PLL is only required to pull the oscillator output frequency to account for the digital quantization, temperature variations, and some margin. This allows the K _o to be small, with better noise performance resulting. The prototype self-calibrating frequency synthesizer, capable of operating from 80 MHz to 1 GHz, demonstrates a measured absolute jitter of 20-ps rms at 480-MHz operating frequency. The prototype IC is fabricated in a 0.35-μm 3-V digital CMOS process     

A MOSFET-C variable equalizer circuit with simple on-chip automatictuning

The authors report a MOSFET-C variable bump equalizer architecture in MOS technology. The architecture is CAD-compatible in that it has a fixed physical layout, yet it achieves independent and continuous programmability of the three equalizer parameters ω₀ (center frequency), BW (bandwidth), and G (gain), using DC control voltages. To compensate for process and temperature variations the equalizer is tuned using a novel and simple master-slave automatic tuning scheme based on a switched-capacitor resistor in a gain control loop. The nonideal effects of the equalizer circuit due to finite amplifier gain bandwidth are studied, and a test chip is fabricated using the MOSIS 2-μm p-well double-poly CMOS process to verify the performance. The equalizer with the automatic tuning circuit occupies 1.25 mm² and operates from ±5-V power supplies. It dissipates 60 mW and provides wide tuning ranges for ω₀, BW, and G with less than 2.8% change in ω₀ over a 40°C temperature range     

Temperature effects in bulk GaAs amplifiers

The microwave-gain characteristics of a bulk GaAs amplifier have been investigated experimentally as a function of temperature. The resistivity of the samples showed a strong temperature dependence, hence the results have been interpreted in terms of changing carrier concentration assuming a constant mobility. It has been found that stable amplification only occurs within a narrow range of temperature (carrier concentration). The highestn . Lproduct (carrier density × sample length) for which gain has been observed was about 5 . 10¹¹cm^-2, and this is in agreement with earlier results and theory. Amplification did not occur belown . L = 8 . 10^{10}cm^-2. The frequency band where negative conductance appears was found to be strongly dependent on temperature (carrier density) and bias field. Noise figures, measured at temperatures where gain occurred, lay between 20 and 30 dB. Noise figure appears to be nearly independent of temperature. Gain versus field measurements on a stable amplifier indicate that the peak field of the velocity-field curve is about 4000 V/cm. Gain versus frequency and noise figure have also been measured on a bulk semiconductor amplifier which was operated with a coaxial transformer to increase the gain over a broad microwave frequency range.     

Current and Voltage gain in a monolithic GaAs/AlGaAs TTJ at room temperature

Transistor characteristics of monolithic GaAs/AlGaAs three-terminal junctions are studied at room temperature. It is found that the channel is controlled by the center branch, although considerable leakage currents flow into the junction. Large current gain, up to 60, is observed. Furthermore, a maximum differential-voltage gain up to values of -30 is demonstrated. The frequency dependence of the rectified output provides a cutoff frequency of 4 GHz.     

A CMOS bandpass filter for low-IF bluetooth receivers

A CMOS fully integrated 12th-order bandpass filter for low interemdiate frequency Bluetooth receivers is presented. The design is optimized to meet the selectivity and dynamic range requirements of Bluetooth while consuming relatively low power. The filter is based on unity gain cells and utilizes linearized MOSFET resistors for tuning. It exhibits a bandwidth of 1 MHz and a programmable center frequency range of 2 to 4 MHz. Experimental results obtained from a standard 0.5-/spl mu/m CMOS chip show that the filter exhibits an in-band dynamic range of 53.3 dB at gain of 0 dB, and 52 dB at gain of 15 dB, while consuming a total current of 1.32 mA. Attenuations of more than 10, 38, and 55 dB, are achieved for blockers one, two, and three, respectively.     

一种实现自调谐频率综合器的算法和结构

在集成的频率综合器中 ,工艺、温度和电源电压的变化使得频率综合器产生的中心频率和频率调谐范围与期望值发生偏移。文中指出了一种自调谐频率综合器的算法和结构 ,利用特殊结构的可编程压控振荡器和自调谐算法实现宽调谐范围的频率综合器 ,进而充分涵盖期望的输出频段。用 0 2 5 μmCMOS工艺设计了一个中心频率 2 2GHz,调谐范围为 338MHz的频率综合器 ,用于IEEE80 2 11b/g无线局域网系统的超外差收发机中 ,可以充分满足标准要求的 80MHz的调谐范围 ;给出了锁定某一目标频率时自调谐算法的具体工作过程 ,结果表明该算法和结构是正确的。     

A hybrid type traveling-wave tube for high-power pulsed amplification

A hybrid-type traveling-wave tube suitable for high gain amplification at pulsed high-power levels is described. The device utilizes a filter-type loaded waveguide slow-wave circuit, with interaction below the propagating range of the circuit. This gives rise to a broad-band inductive-wall type of amplification with high gain per unit length. The particular structure outlined employs a spatial-harmonic traveling-wave circuit to couple the energy to the input and to extract power at the output. The main interaction circuit is separated from the input and output section by short ceramic terminations. With proper design, performance at good efficiencies is obtained over a 10 per cent bandwidth to date. A special feature of the device is the possibility of adjusting the gain variation with frequency to suit the designer. This comes about from the fact that the gain per unit length decreases with frequency in the coupling sections, and increases with frequency in the center (nonpropagating) section. By proper selection of the relative lengths of the two circuits, it is possible to obtain either flat gain or peak gain at either end of the frequency range. The efficiency does not appear to be affected by the center section and is limited by the characteristics of the output section only. With the present configuration, it was possible to obtain both good stability and reasonable efficiency simultaneously.     

Low-power CMOS continuous-time filters

A design technique for low-power continuous-time filters using digital CMOS technology is presented. The basic building block is a fully-balanced integrator with its unity-gain frequency determined by a small-signal transconductance and MOSFET gate capacitance. Integrator excess phase shift is reduced using balanced signal paths, and open-loop gain is increased using low-voltage cascode amplifiers. Two-pole bandpass and five-pole lowpass ladder filters have been implemented in a 1.2 μm n-well CMOS process. The lowpass prototypes provided 300 kHz-1000 kHz bias-current-tunable -3 dB bandwidth, 67 dB dynamic range with 1% total harmonic distortion (THD), and 30 μW/pole (300 kHz bandwidth) power dissipation with a 1.5 V supply; the bandpass prototypes had a tunable center frequency of 300 kHz-1000 kHz, Q of 8.5, and power dissipation of 75 μW/pole (525 kHz center frequency) from a 1.5 V supply. The active filter area was 0.1 mm²/pole for both designs     

Heterogeneous High-Performance Quantum-Cascade Laser Sources for Broad-Band Tuning

A heterogeneous high-performance quantum-cascade laser gain chip comprising two bound-to-continuum active region designs emitting at 8.2 and 9.3 $mu$m is presented. Its extrapolated gain spectrum has a full-width at half-maximum (FWHM) of 350 cm$^{ - 1}$. Though a broad gain bandwidth invariably results in a reduced gain cross section, devices with a high-reflection coated back facet still lase continuous-wave (CW) up to a temperature of 50 $^{circ}$C and demonstrates output powers in excess of 100 mW at 30$^{circ}$C. Such high performance was achieved by designing the waveguide in a buried heterostructure fashion and epi-down mounting on a diamond submount, resulting in a thermal resistance of only 4.8 K/W. In pulsed mode, we reached a peak output power of 1 W at room temperature. Finally, in order to prove the usability for broad-band tuning, this chip was antireflection coated on the front facet with a residual reflectivity of $≪ {hbox {2.5}} times {hbox {10}}^{-3}$ and used in our external cavity (EC) setup operated at room temperature. In pulsed mode, we were able to tune the gain chip over 292 cm $^{-1}$, which is 25% of center frequency. In CW, we reached a coarse tuning range of 201 cm$^{-1}$ (18%) and an output power in excess of 135 mW at the gain maximum at 15$^{circ}$C. This gain chip enabled CW room temperature EC tuning with output powers in excess of 20 mW over 172 cm 相似文献   

An Active Recursive RF Filter in 0.35 μm BiCMOS

An active recursive filter approach is proposed for the implementaion of an inductorless, tuneable RF filter in BiCMOS. A test circuit was designed and manufactured in a 0.35 μm SiGe BiCMOS technology. In simulations, the feasibility of this type of filter was demonstrated and reasonably good performance was obtained. The simulations show a center frequency tuning range from 6 to 9.4 GHz and a noise figure of 8.8 to 10.4 dB depending on center frequency. Gain and Q-value are tunable in a wide range. Simulated IIP-3 and 1-dB compression point is ?26 and ?34 dBm respectively, simulated at the center frequency 8.5 GHz and with 15 dB gain. Measurements on the fabricated device shows a center frequency tuning range from 6.6 to 10 GHz, i.e. slightly higher center frequencies were measured than the simulated.     

基于SBS的通带可变微波光子滤波器

提出并分析了一种大范围可调谐的通带可变微波光子滤波器。它基于受激布里渊散射(SBS)效应并使用2个调制器与1个光纤布喇格光栅生成泵浦信号。通过分别调节这2个调制器的调制频率,可得双通带滤波器和通带间隔可变的四通带滤波器,并实现滤波器中心频率的大范围连续可调谐,而在整个调谐过程中,滤波器的3dB带宽保持不变。仿真分析了不同调制信号对滤波器通带及中心频率的影响,以及滤波器的带宽与泵浦的功率和SBS增益介质长度的关系。     

An X- and Ku-Band 8-Element Phased-Array Receiver in 0.18-$mu{hbox{m}}$ SiGe BiCMOS Technology

This paper demonstrates an 8-element phased array receiver in a standard 0.18-mum SiGe BiCMOS (1P6M, SiGe HBT f_t ap 150 GHz) technology for X- and Ku-band applications. The array receiver adopts the All-RF architecture, where the phase shifting and power combining are done at the RF level. With the integrations of all the digital control circuitry and ESD protection for all I/O pads, the receiver consumes a current of 100 ~ 200 m A from a 3.3 V supply voltage. The receiver shows 1.5 ~ 24.5 dB of power gain per channel from a 50 Omega load at 12 GHz with bias current control, and an associated NF of 4.2 dB (@ max. gain) to 13.2 dB (@ min. gain). The RMS gain error is < 0.9 dB and the RMS phase error is < 6deg at 6-18 GHz for all 4-bit phase states. The measured group delay is 162.5 plusmn 12.5 ps for all phase states at 6-18 GHz. The RMS phase mismatch and RMS gain mismatch among the eight channels are < 2.7deg and 0.4 dB, respectively, for all 16 phase states, over 6-18 GHz. The 8-element array can operate instantaneously at any center frequency and with a wide bandwidth (3 to 6 GHz, depending on the center frequency) given primarily by the 3 dB gain variation in the 6-18 GHz range. To our knowledge, this is the first demonstration of an All-RF phased array on a silicon chip with very low RMS phase and gain errors at 6-18 GHz. The chip size is 2.2 times 2.45 mm² including all pads.     

A low-power and high-gain fully integrated CMOS LNA

In this paper, we present the design of a fully integrated CMOS low noise amplifier (LNA) with on-chip spiral inductors in 0.18 μm CMOS technology for 2.4 GHz frequency range. Using cascode configuration, lower power consumption with higher voltage and power gain are achieved. In this configuration, we managed to have a good trade off among low noise, high gain, and stability. Using common-gate (CG) configuration, we reduced the parasitic effects of C_gd and therefore alleviated the stability and linearity of the amplifier. This configuration provides more reverse isolation that is also important in LNA design. The LNA presented here offers a good noise performance. Complete simulation analysis of the circuit results in center frequency of 2.4 GHz, with 37.6 dB voltage gain, 2.3 dB noise figure (NF), 50 Ω input impedance, 450 MHz 3 dB power bandwidth, 11.2 dB power gain (S₂₁), high reverse isolation (S₁₂)<−60 dB, while dissipating 2.7 mW at 1.8 V power supply.     

A Unilateral Parametric Amplifier

A theoretical investigation of a unilateral parametric amplifier using two varactor diodes indicates an improvement of unilateral stability over already existing types. A circuit is suggested which uses lower sideband idler energy for achieving forward gain and upper side-band energy to obtain substantial reverse loss. The phases of the applied signals and of the pump at the two varactors have to be 90/spl deg/ out of phase to achieve unilateral operation. Numerical evaluation of the theoretical results for a signal frequency at 4.0 GHz and a pump frequency at 12.0 GHz, assuming a diode junction capacitance of C/sub j/ = 0.4 pF and a bulk resistance of R/sub s/ = 2/spl Omega/ was done for several pump power levels. For 14 dB maximum forward gain, the 3 dB bandwidth of the gain versus frequency characteristic of the unilateral amplifier is about 18 percent smaller than that of the reflection type amplifier. The maximum reverse loss for these conditions is 7.3 dB. For lower forward gain the backward loss increases relatively until for very low gain values (about 1 dB) the amplifier is unconditionally stable, i.e., the backward loss is larger than the forward gain. The theoretical noise figure is about 1.95 dB at signal center frequency for 14 dB forward gain and, for /spl plusmn/80 MHz from the center frequency, only 0.1 dB higher than for the reflection type amplifier.     

一个4～12GHz混合集成宽带功率放大器

设计研制了一个4～12GHz的宽带混合集成平衡功率放大器电路.该平衡放大器由一个4指的微带兰格耦合器实现.其输出连续波饱和功率在中心频率为8GHz时达到29.5dBm,在4～12GHz频率范围内增益达到8.5dB,增益平坦度为+/-0.6dB.     

A 0.13 μm CMOS UWB RF Transmitter with an On‐Chip T/R Switch

This paper presents a fully integrated 0.13 μm CMOS MB‐OFDM UWB transmitter chain (mode 1). The proposed transmitter consists of a low‐pass filter, a variable gain amplifier, a voltage‐to‐current converter, an I/Q up‐mixer, a differential‐to‐single‐ended converter, a driver amplifier, and a transmit/receive (T/R) switch. The proposed T/R switch shows an insertion loss of less than 1.5 dB and a Tx/Rx port isolation of more than 27 dB over a 3 GHz to 5 GHz frequency range. All RF/analog circuits have been designed to achieve high linearity and wide bandwidth. The proposed transmitter is implemented using IBM 0.13 μm CMOS technology. The fabricated transmitter shows a ?3 dB bandwidth of 550 MHz at each sub‐band center frequency with gain flatness less than 1.5 dB. It also shows a power gain of 0.5 dB, a maximum output power level of 0 dBm, and output IP3 of +9.3 dBm. It consumes a total of 54 mA from a 1.5 V supply.     

一种温度不敏感的高线性功率放大器

设计了一种温度不灵敏的高线性度的射频功率放大器芯片,采用新颖的带温度反馈环路的有源片上自适应偏置电路,该电路降低了温度引起的放大器集电极直流电流分量的变化量,补偿了由温度变化而引起的性能偏差,进而有效提高了放大器的线性度。基于这个温度不灵敏的偏置结构采用InGaP/GaAs HBT工艺设计了一个工作在2110~2170 MHz频段的功率放大器。测试结果表明,该功放在工作频段内的增益大于等于35.3 dB;在中心频率2140 MHz处,1 dB功率压缩点大于33 dBm,功率附加效率在输出功率24.5 dBm时为18%;使用LTE_FDD调制信号,获得邻信道功率比为-47 dBc。在环境温度为-40℃、+25℃和+80℃条件下,功放的增益平坦度较好,增益变化量小于1.5 dB,输出级集电极电流基本不变,有效降低了功放对温度的敏感性。     

A high-frequency temperature-stable monolithic VCO

A new high-frequency monolithic voltage-controlled oscillator (VCO) is described that achieves /spl plusmn/60 ppm//spl deg/C temperature coefficient of frequency over 0-75/spl deg/C at center frequencies from DC to 20 MHz. The circuit also exhibits good linearity of voltage to frequency, and excellent triangle output waveform over the whole frequency range from low frequencies to 20 MHz. The circuit is fabricated using an eight mask IC process and has a die size of 65/spl times/50 mils/SUP 2/.     

32-GHz cryogenically cooled HEMT low-noise amplifiers

The cryogenic noise temperature performances of a two-stage and a three-stage 32-GHz HEMT (high-electron-mobility transistor) amplifier were evaluated. The amplifiers utilize quarter-micrometer conventional AlGaAs/GaAs HEMT devices, hybrid matching input and output microstrip circuits, and a cryogenically stable DC biasing network. The noise temperature measurements were performed in the frequency range of 31 to 33 GHz over a physical temperature range of 300 to 12 K. Across the measurement band, the amplifiers displayed a broadband response, and the noise temperature was observed to decrease by a factor of ten in cooling from 300 to 15 K. The lowest noise temperature measured for the two-stage amplifier at 32 GHz was 35 K with an associated gain of 16.5 dB, while for the three-stage amplifier it was 39 K with an associated gain of 26 dB. It was further observed that both amplifiers were insensitive to light     

A 65 mW, 0.4–2.3 GHz Bandpass Filter for Satellite Receivers

A monolithic tunable bandpass filter for satellite receiver front-ends is presented. The center frequency of the bandpass filter can be tuned from 0.4 GHz to 2.3 GHz. The filter is constructed using four transconductor-C poly-phase filter sections and has a 50 dB variable gain range. At 20 dB attenuation and at 30 dB gain the measured 1 dB compression point is –21 dBm and –56 dBm, respectively. Measured input IP3 is –12 dBm. The noise figure is 15 dB at maximum gain. An on-chip I/Q oscillator tracks the center frequency and enables automatic tuning. The bandpass filter dissipates 65 mW with 5 Volt supply voltage and occupies 0.16 mm² chip area. The filter is realized in a standard 11 GHz f _t bipolar technology.