FeGC: An efficient garbage collection scheme for flash memory based storage systems

NAND flash memory is a promising storage media that provides low-power consumption, high density, high performance, and shock resistance. Due to these versatile features, NAND flash memory is anticipated to be used as storage in enterprise-scale systems as well as small embedded devices. However, unlike traditional hard disks, flash memory should perform garbage collection that consists of a series of erase operations. The erase operation is time-consuming and it usually degrades the performance of storage systems seriously. Moreover, the number of erase operations allowed to each flash memory block is limited. This paper presents a new garbage collection scheme for flash memory based storage systems that focuses on reducing garbage collection overhead, and improving the endurance of flash memory. The scheme also reduces the energy consumption of storage systems significantly. Trace-driven simulations show that the proposed scheme performs better than various existing garbage collection schemes in terms of the garbage collection time, the number of erase operations, the energy consumption, and the endurance of flash memory.     

Next High Performance and Low Power Flash Memory Package Structure

In general, NAND flash memory has advantages in low power consumption, storage capacity, and fast erase/write performance in contrast to NOR flash. But, main drawback of the NAND flash memory is the slow access time for random read operations. Therefore, we proposed the new NAND flash memory package for overcoming this major drawback. We present a high performance and low power NAND flash memory system with a dual cache memory. The proposed NAND flash package consists of two parts, i.e., an NAND flash memory module, and a dual cache module. The new NAND flash memory system can achieve dramatically higher performance and lower power consumption compared with any conventionM NAND-type flash memory module. Our results show that the proposed system can reduce about 78% of write operations into the flash memory cell and about 70% of read operations from the flash memory cell by using only additional 3KB cache space. This value represents high potential to achieve low power consumption and high performance gain.     

Using data clustering to improve cleaning performance for flash memory

Flash memory offers attractive features for storage of data, such as non‐volatility, shock resistance, fast access speed, and low power consumption. However, it requires erasing before it can be overwritten. The erase operations are slow and consume comparatively a great deal of power. Furthermore, flash memory can only be erased a limited number of times. To overcome hardware limitations, we use the non‐in‐place update mechanism that requires a cleaner to reclaim space occupied by obsolete data. To improve cleaning performance and prolong flash memory lifetime, we propose a new data reorganization method. By this method, data in flash memory are dynamically classified and clustered together according to their accessing frequencies. Experimental results show that this clustering technique significantly improved the cleaning performance for a variety of cleaning algorithms. The number of erase operations performed is greatly reduced and flash memory lifetime is prolonged. Even wearing is ensured as well. Copyright © 1999 John Wiley & Sons, Ltd.     

Transaction Management for Flash Media Databases in Portable Computing Environments

Flash memory is becoming a major database storage in building embedded systems or portable devices because of its non-volatile, shock-resistant, power-economic nature, and fast access time for read operations. Flash memory, however, should be erased before it can be rewritten and the erase and write operations are very slow as compared to main memory. Due to this drawback, traditional database management schemes are not easy to apply directly to flash memory database for portable devices. Therefore, we improve the traditional schemes and propose a new scheme called flash two phase locking (F2PL) scheme for efficient transaction processing in a flash memory database environment. F2PL achieves high transaction performance by exploiting the notion of the alternative version coordination which allows previous version reads and efficiently handles slow write/erase operations in lock management processes. We also propose a simulation model to show the performance of F2PL. Based on the results of the performance evaluation, we conclude that F2PL scheme outperforms the traditional schemes.     

Data loss recovery for power failure in flash memory storage systems

Due to the rapid development of flash memory technology, NAND flash has been widely used as a storage device in portable embedded systems, personal computers, and enterprise systems. However, flash memory is prone to performance degradation due to the long latency in flash program operations and flash erasure operations. One common technique for hiding long program latency is to use a temporal buffer to hold write data. Although DRAM is often used to implement the buffer because of its high performance and low bit cost, it is volatile; thus, that the data may be lost on power failure in the storage system. As a solution to this issue, recent operating systems frequently issue flush commands to force storage devices to permanently move data from the buffer into the non-volatile area. However, the excessive use of flush commands may worsen the write performance of the storage systems. In this paper, we propose two data loss recovery techniques that require fewer write operations to flash memory. These techniques remove unnecessary flash writes by storing storage metadata along with user data simultaneously by utilizing the spare area associated with each data page.     

基于逻辑区间热度的NAND闪存垃圾回收算法

针对现有的NAND闪存垃圾回收算法中回收性能不高,磨损均衡效果差,并且算法内存开销大的问题,提出了一种基于逻辑区间热度的垃圾回收算法。该算法重新定义了热度计算公式,把连续逻辑地址的NAND内存定义为一个热度区间,以逻辑区间的热度来代替逻辑页的热度,并将不同热度的数据分开存储到不同擦除次数的闪存块上,有效地实现了数据冷热分离,并且节约了内存空间。同时,算法还构造了一种新的回收代价函数来选择回收块,在考虑回收效率的同时,还兼顾了磨损均衡的问题。实验结果表明,该算法与性能优异的FaGC算法相比,总的擦除次数减少了11%,总的拷贝次数减少了13%,擦次数最大差值减少了42%,内存消耗能减少了75%。因此,该算法有利于增加闪存可用空间,改善闪存系统的读写性能,延长闪存使用寿命。     

Journaling deduplication with invalidation scheme for flash storage-based smart systems

Transaction support for filesystems has become a common feature in modern operating systems where data atomicity is achieved by writing transactions to the log region in advance. The logging mechanism is appropriate for flash storage devices due to the inherent nature of flash memory. However, the logging schemes inherently create multiple copies of data, leading to a decrease in the bandwidth of storage systems. In this paper, we present a simple and efficient invalidation scheme for multiple copies of data in a common journaling module. We identify two types of duplications, one in which there is an explicit duplication of the journal region and original region with the same data, and the other in which there is an implicit duplication of transaction commit operations. The invalidation of duplicated data reduces internal write and erase operations and garbage collection overhead for flash devices, which would otherwise increases external I/O bandwidth. Experimental results show that the overall performance improves roughly from 5% to 35% with the invalidation scheme for journal transactions.     

NVMRA: utilizing NVM to improve the random write operations for NAND‐flash‐based mobile devices

NAND flash memory has become the major storage media in mobile devices, such as smartphones. However, the random write operations of NAND flash memory heavily affect the I/O performance, thus seriously degrading the application performance in mobile devices. The main reason for slow random write operations is the out‐of‐place update feature of NAND flash memory. Newly emerged non‐volatile memory, such as phase‐change memory, spin transfer torque, supports in‐place updates and presents much better I/O performance than that of flash memory. All these good features make non‐volatile memory (NVM) as a promising solution to improve the random write performance for NAND flash memory. In this paper, we propose a non‐volatile memory for random access (NVMRA) scheme to utilize NVM to improve the I/O performance in mobile devices. NVMRA exploits the I/O behaviors of applications to improve the random write performance for each application. Based on different I/O behaviors, such as random write‐dominant I/O behavior, NVMRA adopts different storing decisions. The scheme is evaluated on a real Android 4.2 platform. The experimental results show that the proposed scheme can effectively improve the I/O performance and reduce the I/O energy consumption for mobile devices. Copyright © 2015 John Wiley & Sons, Ltd.     

Modeling the aging process of flash storage by leveraging semantic I/O

The major advantages of flash memory such as small physical size, no mechanical components, low power consumption, and high performance have made it likely to replace the magnetic disk drives in more and more systems. Many research efforts have been invested in employing flash memory to build high performance and large-scale storage systems for data-intensive applications. However, the endurance cycle of flash memory has become one of the most important challenges in further facilitating the flash memory based systems. This paper proposes to model the aging process of flash memory based storage systems constructed as a Redundant Array of Independent Disks (RAID) by leveraging the semantic I/O. The model attempts to strike a balance between the program/erase cycles and the rebuilding process of RAID. The analysis results demonstrate that a highly skewed data access pattern ages the flash memory based RAID with an arbitrary aging rate, and a properly chosen threshold of aging rate can prevent the system from aging with a uniform data access pattern. The analysis results in this paper provide useful insights for understanding and designing effective flash memory based storage systems.     

Prober: exploiting sequential characteristics in buffer for improving SSDs write performance

Solid state disks (SSDs) are becoming one of the mainstream storage devices due to their salient features, such as high read performance and low power consumption. In order to obtain high write performance and extend flash lifespan, SSDs leverage an internal DRAM to buffer frequently rewritten data to reduce the number of program operations upon the flash. However, existing buffer management algorithms demonstrate their blank in leveraging data access features to predict data attributes. In various real-world workloads, most of large sequential write requests are rarely rewritten in near future. Once these write requests occur, many hot data will be evicted from DRAM into flash memory, thus jeopardizing the overall system performance. In order to address this problem, we propose a novel large write data identification scheme, called Prober. This scheme probes large sequential write sequences among the write streams at early stage to prevent them from residing in the buffer. In the meantime, to further release space and reduce waiting time for handling the incoming requests, we temporarily buffer the large data into DRAM when the buffer has free space, and leverage an actively write-back scheme for large sequential write data when the flash array turns into idle state. Experimental results demonstrate that our schemes improve hit ratio of write requests by up to 10%, decrease the average response time by up to 42% and reduce the number of erase operations by up to 11%, compared with the state-of-the-art buffer replacement algorithms.     

Optimizing random write performance of FAST FTL for NAND flash memory

The NAND flash memory has gained its popularity as a storage device for consumer electronics due to its higher performance and lower power consumption.In most of these devices,an FTL(Flash Translation Layer)is adopted to emulate a block device interface to support the conventional disk-based file systems that make the flash management much easier.Among various FTLs,the FAST(Fully-Associative Sector Translation)FTL has shown superior performance,becoming one of the state-of-the-art approaches.However,the FAST FTL performs poorly while dealing with a huge number of small-sized random writes brought by upper applications such as database transaction processing workloads.The two important reasons are the absence of efficient selection schemes for the reclaiming of random log blocks that leads to large overhead of full merges,and the sequential log block scheme which no longer applies to random writes due to the large costs of partial merges.To overcome the above two defects in the presence of random writes,two techniques have been proposed.The first technique reduced full merge costs by adopting a novel random log block selection algorithm,based on the block associativity and the relevant-valid-page-amount of random log blocks as the key block selection criterion.The second technique replaced the sequential log block with a random log block to eliminate the overhead of partial merges.Experimental results showed that our optimizations can outperform FAST FTL significantly in three aspects:erase counts,page migration amount,and response time.The maximum improvement level in these cases could reach up to 66.8%,98.2%,and 51.0%,respectively.     

一种运用块级局部性的闪存缓存管理策略

闪存被广泛应用在电子产品的存储设备中, 针对闪存的研究也日益得到重视. 基于访问的局部性原理, 并结合闪存读写代价的差异性, 提出了一种针对闪存特点运用块级局部性原理的cache缓存管理算法LRU-BLL. 实验表明, 这种方法有效地提高了缓存的命中率, 并且减少了缓存的脏页回写次数和提高了缓冲区的平均换出长度.     

Generic and efficient framework for search trees on flash memory storage systems

Tree index structures are crucial components in data management systems. Existing tree index structure are designed with the implicit assumption that the underlying external memory storage is the conventional magnetic hard disk drives. This assumption is going to be invalid soon, as flash memory storage is increasingly adopted as the main storage media in mobile devices, digital cameras, embedded sensors, and notebooks. Though it is direct and simple to port existing tree index structures on the flash memory storage, that direct approach does not consider the unique characteristics of flash memory, i.e., slow write operations, and erase-before-update property, which would result in a sub optimal performance. In this paper, we introduce FAST (i.e., Flash-Aware Search Trees) as a generic framework for flash-aware tree index structures. FAST distinguishes itself from all previous attempts of flash memory indexing in two aspects: (1) FAST is a generic framework that can be applied to a wide class of data partitioning tree structures including R-tree and its variants, and (2) FAST achieves both efficiency and durability of read and write flash operations through memory flushing and crash recovery techniques. Extensive experimental results, based on an actual implementation of FAST inside the GiST index structure in PostgreSQL, show that FAST achieves better performance than its competitors.     

Virtual duplication and mapping prefetching for emerging storage primitives in NAND flash memory storage systems

NAND flash memory has become the mainstream storage medium for both enterprise high performance computers and embedded systems. However, over the past several decades, the storage primitives that access secondary storage have remained unchanged, forcing NAND flash memory to serve merely as a block device like hard disk drive. Recently, several emerging storage primitives have been presented to explore the potential value of non-volatile memory devices. Although these primitives can significantly boost the access performance by providing virtual to logical address mappings, they still suffer from large RAM footprint to maintain the address mapping table and require further support for update operations.This paper presents ESP to optimize E merging S torage P rimitives with virtualization for flash memory storage systems. We propose two optimization strategies, virtual duplication and mapping prefetching to solve the critical issues in existing emerging storage primitives. The objective is to reduce unnecessary flash memory accesses and keep RAM footprint of address mapping table well under control. We have evaluated ESP on an embedded development platform. Experimental results show that ESP can significantly improve the write/read performance and reduce over 30% of garbage collection operations.     

嵌入式Flash文件系统的设计与实现

Flash存储器是一种在嵌入式系统中日益普及的存储介质,它提供了高密度且成本相对较低的固态存储。使用Flash存储器需要很多技巧来确保数据可靠性并延长Flash器件的使用寿命。根据Flash存储器的特点提出了一种文件系统模型,可以合理且有效地利用Flash存储器,同时提供日志特性以增强使用该文件系统的嵌入式系统的可靠性。     

OAFTL:一种面向企业级应用的高效闪存转换层处理策略

基于NAND闪存的存储设备通过引入闪存转换层来对闪存芯片进行封装,使得闪存存储设备像普通块设备一样使用.闪存转换层算法的性能很大程度上决定了闪存设备的存储性能,已有方法尽管可以在嵌入式环境下正常工作,但当应用到随机访问频繁的企业级应用环境中时存在访问性能低的问题.提出了一种面向企业级应用的闪存转换层算法OAFTL,该算...     

3G智能卡文件系统的研究与设计

对基于Flash的3G智能卡文件系统的研究与设计,引用了数据库日志技术和掉电保护机制,保证了智能卡文件系统可靠性,数据的一致性和完整性;按字节静态分配存储空间、合理有效地回收与重用碎片空间,提高了存储空间的利用率;平均磨损和页面映射技术的使用延长了Flash的使用寿命;有效的存储设计提高了数据检索的速度,从而提高了智能卡的整体性能。测试证实了该文件系统设计适合3G EVDO卡。     

NAND闪存存储文件系统

NAND闪存已经成为便携式设备的主要存储介质。由于闪存自身的物理特性,需要在现有文件系统层与闪存的存储物理层之间引入闪存转换层。但是,现有文件系统主要针对磁盘存储系统设计的,没有考虑NAND闪存物理特性。这种方法效率低、影响便携式设备的性能。本文概述了NAND闪存的存储文件系统,分析比较了其中三种主要文件系统,为基于NAND闪存存储介质的便携式系统设计提供了参考意见。     

A flash-aware write buffer scheme to enhance the performance of superblock-based NAND flash storage systems

Most superblock-based NAND flash storage systems employ a high-speed write buffer to enhance their writing performance. The main objective is to bind data of adjacent addresses as much as possible in order to transform random data into sequential data, which then facilitates interleaving in the storage system. We have designed a new superblock-based buffer scheme for NAND flash storage systems that improves on traditional schemes. For buffer management, a series of lists need to be specified to monitor the dataflow changes in the current state of the buffered data and the NAND flash memory in order to maximize interleaving during the flush operation. Experimental results show that the proposed scheme achieves higher write speed performance in almost all configurations, with greater than 50% speedup in some cases. Our proposed flash-aware write buffer (FAWB) scheme achieves this higher write performance with a required buffer space of only 1/4th–1/8th that of other schemes, resulting in higher efficiency.     

Reducing SSD access latency via NAND flash program and erase suspension

In NAND flash memory, once a page program or block erase (P/E) command is issued to a NAND flash chip, the subsequent read requests have to wait until the time-consuming P/E operation to complete. Preliminary results show that the lengthy P/E operations increase the read latency by 2× on average. This increased read latency caused by the contention may significantly degrade the overall system performance. Inspired by the internal mechanism of NAND flash P/E algorithms, we propose in this paper a low-overhead P/E suspension scheme, which suspends the on-going P/E to service pending reads and resumes the suspended P/E afterwards. Having reads enjoy the highest priority, we further extend our approach by making writes be able to preempt the erase operations in order to improve the write latency performance. In our experiments, we simulate a realistic SSD model that adopts multi-chip/channel and evaluate both SLC and MLC NAND flash as storage materials of diverse performance. Experimental results show the proposed technique achieves a near-optimal performance on servicing read requests. The write latency is significantly reduced as well. Specifically, the read latency is reduced on average by 46.5% compared to RPS (Read Priority Scheduling) and when using write–suspend–erase the write latency is reduced by 13.6% relative to FIFO.