并行级联分组码基于相关运算的叠加反馈译码

并行级联分组码和串行级联分组码均可实现基于LLR计算的Turbo迭代译码,但前者具有更高的码率.将接收信息与子译码器的输出软信息进行线性叠加反馈能在省去繁琐的LLR计算的情况下实现并行级联分组码的Turbo迭代译码,仅通过对译码器的输出进行简单的相关运算以及对Chase2译码算法进行适当的改进便可获得接近LLR算法的译码性能.仿真研究验证了算法的有效性.     

一种Turbo乘积码编译码器的设计与实现

分析了Turbo乘积码的线性编码和基于Chase算法的软输入软输出迭代译码方法,讨论了硬件可实现的低延迟编码器、译码器应具有的结构特点,并采用此方法设计了1个长度为1024bit、码率66％的Turbo乘积码。该编码器工作时钟和输入数据速率相同,译码器则需要3倍于输入数据速率的时钟,译码器理论吞吐率可达60Mb／s。实测结果表明,其性能和仿真值相差不大于0．4dB。     

一种新的Turbo乘积码简化迭代译码算法

针对二维TPC码提出一种新的简化迭代译码算法以及一种新的译码器迭代结构。该算法在Chase迭代软输入软输出译码的基础上,通过简化软输入信息和外信息的计算来降低译码复杂度和系统存储量。仿真结果验证了该算法的正确性和可行性。     

基于DMR通信协议的信道编解码研究

为了提高DMR系统基带算法的性能,分析研究了DMR通信协议中的BPTC码和变长BPTC码.针对这两种码,提出了利用和积算法作为软输入软输出译码器,进行迭代译码的新方案.该方案在MATLAB下进行了仿真,并与伴随式译码方案进行了对比分析.BPTC和变长BPTC码的仿真实验结果表明,采用软判决迭代译码的方案在低信噪比和高信噪比时都有更好的编码增益.     

基于FPGA的改进Turbo译码器的设计与实现

Turbo码的译码性能几乎接近shannon理论极限,实现Turbo译码器对于降低信道传输的误码率、提高传输可靠性具有重要的意义。本文设计了一种基于SOVA算法的改进Turbo译码器,并下载到Xilinx公司的Spartan-3S1500 FP-GA开发板上验证成功。Turbo译码器的输入信息和输出信息通过FPGA板与PC机的通信获得。实验结果表明,所设计的Turbo译码器是正确的。     

低复杂度的Turbo乘积码迭代译码研究

Turbo乘积码（简称TPC码）的传统迭代译码算法寻找竞争码字难、软信息存储量大。针对这些问题提出一种低复杂度的迭代译码算法,并得出新的译码器迭代结构。该算法在Chase迭代SISO译码的基础上,采用无需寻找竞争码字的相关运算来简化软输出信息的计算,同时用前一个迭代译码单元的软输入信息替换传统算法中信道原始接收信息,然后与当前迭代译码单元的软输出信息直接进行线性叠加后作为下一个迭代译码单元的软输入,从而简化了软输入信息的计算和系统存储量。仿真结果验证了该算法的可行性和有效性。     

带限信道的Turbo均衡、信道估计和TTCM

给出了适用于带宽有限信道的Turbo均衡和译码模型,该模型基于高带宽效率的TTCM译码、软输入软输出均衡器和软输入WRLS信道估计。该模型的均衡器和译码器使用LOG-MAP准则,通过均衡器和译码器间的迭代可以获得更高的增益。     

Turbo码的迭代译码方法的优化设计

迭代译码可以提高Turbo码的译码性能,但也是增加译码复杂性、延时及功率损耗的主要原因。在分析Turbo码的迭代译码原理和译码算法的基础上,提出了一种迭代译码的优化设计方法(Turbo-CRC),即利用循环冗余检测码CRC对Turbo译码器硬判决的输出结果进行检测,可以有效地减小平均迭代次数。计算机仿真结果表明在不降低译码性能和不增加系统复杂度的情况下,使用该方法可以有效地减小平均迭代次数和译码延时,尤其是在大信噪比时,效果更好。     

应用于LTE-OFDM系统的Viterbi译码在FPGA中的实现

在OFDM系统中,为了获得正确无误的数据传输,要采用差错控制编码技术。LTE中采用Viterbi和Turbo加速器来实现前向纠错。提出一种在FPGA中实现的基于软判决的Viterbi译码算法,并以一个(2,1,2)、回溯深度为10的软判决Viterbi译码算法为例验证该算法,在Xilinx的XC3S500E芯片上实现了该译码器,最后对其性能做了分析。     

Turbo译码器的改进算法及FPGA实现

在传统的Turbo译码算法Log-MAP的基础上,对译码算法和SISO译码模块进行了优化,得到了改进的SW-Log-MAP算法,它在保证译码性能的前提下,大大降低了其运算复杂度,减少了存储空间。并且给出了改进译码算法硬件实现的设计方案,完成了Turbo译码器的FPGA实现,通过测试证明,译码器达到了设计要求。     

Turbo iterative equalization for HSDPA systems

In this paper, a turbo iterative receiver structure with chip equalization is proposed for the 3G high-speed downlink packet access (HSDPA) systems. The receiver equalizes the channel prior to the dispreading and then performs two successive soft-output decisions, achieved by a soft-input soft-output (SISO) multi-code de- tector and a SISO turbo decoder through an iterative process. At each iteration, extrinsic information is extracted from detection and decoding stages and is then used as a priori information in the next iteration, just as in turbo decoding. Com- puter simulations show that the turbo iterative receiver structure with chip equali- zation offers significant performance gain over the traditional receiver structure.     

Decoding algorithms for shortened-extended turbo product codes in WiMAX systems

The component codes of turbo product codes inWiMAX systems are extended Hamming codes and single parity check codes as well as their shortened forms. In this paper, three novel iterative decoding algorithms based on Chase, MAP algorithms and their combination are proposed for shortened-extended turbo product codes. The iterative decoding algorithm based on Chase algorithm is proposed to reduce the decoding complexity without any performance loss. An efficient MAP algorithm is then proposed to decode the component codes of shortened single parity check codes and shortened-extended Hamming codes. A comprehensive performance comparison of the proposed decoding schemes is conducted for three typical classes of turbo product codes in WiMAX OFDMA systems. The suitable decoding algorithms are recommended for different classes based on the simulation results.     

用于H.264的Turbo码非均等译码保护策略

从最新的H．264视频压缩标准出发，提出一种基于H．264的数据分类和Turbo码的非均等译码保护的策略。针对Turbo码译码的特点译码迭代次数越多，纠错能力越强，但带来更多的译码复杂度和时延即消耗较多的功率。对于H．264三种数据分类，按照信息比特重要性的不同进行非均等译码保护，重要的数据给予更多的迭代次数的译码，次重要的数据给予较少的迭代次数的译码，以实现性能和功耗的折衷。仿真结果表明，本文算法不仅能提高解码质量，而且在实时中能减少时延和复杂度及功耗，特别适用于视频手机和手持设备业务。     

TPC自适应迭代译码方法

提出一种TPC自适应迭代译码算法。从接收到的软信息估算信道的信噪比;根据信噪比选择最优的软译码迭代因子,将迭代因子与软信息送入SISO迭代译码器;检测每次SISO译码器的输出,达到迭代终止条件即结束译码。提出的自适应迭代译码方法大大地增强了译码器的灵活性,动态的选择译码策略,尤其在低噪声信道下有效地降低了译码的功耗。     

On chip interconnects for multiprocessor turbo decoding architectures

Turbo codes are among the most powerful and widely adopted error correcting codes in several communication applications. The high throughput requirements of current and future standards impose that parallel decoders composed by multiple interconnected processing elements are used at the receiver side to efficiently decode turbo codes. In this work, on chip interconnects for multiprocessor turbo decoding are investigated. Due to the dominant trend towards the design of flexible, multi-standard decoders, capable to support the decoding of several turbo codes, the Network-on-Chip approach is seen as a viable and promising solution, although the specific characteristics of the addressed application impose a drastic simplification in the network organization. Both indirect and direct network topologies are studied and experimental results show that a Network-on-Chip based decoder made of 16 processing elements can achieve a throughput of several hundreds of Mbps. Moreover, the area required by the network compares favorably with previously published works on flexible interconnect architectures for turbo decoding and the cost overhead of NOC based solutions with respect to a fully dedicated implementation is limited to 13%.     

Modeling the bit-level stochastic correlation for turbo decoding

After passing a systematic bit through a turbo encoder, the encoding process will introduce some extent of correlation between a systematic bit and its associated parity bits. However, this correlation is neglected in the subsequent turbo decoding process so as to reduce its computational complexity. In this paper, we try to explore the feasibility of modeling the bit-level stochastic correlation for the iterative turbo decoding. By properly adjusting the parameter of the correlation model, we can approximate various degrees of the underlying correlation within the received codewords. Reduction in bit error rate (BER) then may benefit from a more accurate capture of the correlation information at the cost of requiring only a small additional computation complexity. Experimental results indicate that incorporating the correlation model into the turbo decoding process can achieve better BER performance than that of conventional turbo decoders over AWGN channels.     

基于Turbo码的信息隐藏技术的研究

文章首先介绍了Turbo码的编码结构和用于Turbo码迭代译码的最大后验概率译码算法;然后提出了在几种不同方案下Turbo码的信息隐藏技术,对隐藏信息前后的译码效果进行了理论分析;最后通过实验对各种隐藏方案进行性能比较。     

Instruction set extensions for software defined radio

Software defined radios provide programmable solutions for implementing the physical layer processing of multiple communication standards. Mobile devices implementing these standards require high-performance processors to perform high-bandwidth physical layer processing in real time. In this paper, we present instruction set extensions for several important communication algorithms including cyclic redundancy checking, convolutional encoding, Viterbi decoding, turbo decoding, and Reed–Solomon encoding and decoding. We also present hardware designs for implementing these extensions, along with estimates of their area, critical path delay, and power consumption. The performance benefits of these extensions are evaluated using a supercomputer-class vectorizing compiler and the Sandblaster low-power multithreaded processor for software defined radio. The proposed instruction set extensions provide significant performance improvements at relatively low cost, while maintaining a high degree of programmability.     

Efficient hardware implementation of 8 × 8 integer cosine transforms for multiple video codecs

The current trend of digital convergence leads to the need of the video decoder that should support multiple video standards such as, H.264/AVC, JPEG, MPEG-2/4, VC-1, and AVS on a single platform. In this paper, we present a cost-sharing architecture of multiple transforms to support all five popular video codecs. The architecture is based on a new multi-dimensional delta mapping. Here the inverse transform matrix of the Discrete Cosine Transform (DCT) of AVS, that has the lowest computational unit, is taken as the base to compute the inverse DCT matrices of the other four codecs. The proposed architecture uses only adders and shifters on a shared basis to reduce the hardware cost significantly. The shared architecture is implemented on FPGA and later synthesized in CMOS 0.18 μm technology. The results show that the proposed design satisfies the requirement of all five codecs with a maximum decoding capability of 60 fps of a full HD video. The scheme is also suitable for low-cost implementation in modern multi-codec systems.