Jitter requirements of the sampling clock in software radio receivers

The effective number of bits of an analog-to-digital converter (ADC) is not only limited by the quantization step inaccuracy but also by sampling time uncertainty. According to a commonly used model, the error caused by timing jitter, integrated over the whole bandwidth, should not be bigger than the quantization noise, for a full swing input signals at the maximum input frequency. This results in unfeasible phase noise requirements for the sampling clock in software radio receivers with direct RF sampling. However, for a radio receiver not the total integrated error is relevant, but only the error signal in the channel bandwidth. This paper explores the clock jitter requirements for a software radio application, using a more realistic model and taking into account the power spectrum of both the input signal and the spectrum of the sampling clock jitter. Using this model, we show that the clock jitter requirements are very similar to reciprocal mixing requirements of superheterodyne receivers.     

时钟抖动对射频脉宽调制性能的影响分析

在全数字发信机系统中,射频脉宽调制(RF-PWM)将基带调制信号的幅度与相位信息编码为输出脉冲的宽度和位置。由于数字信号处理器件的非理想特性,其时钟信号的上升沿和下降沿存在抖动误差,影响RF-PWM的输出信号质量。基于3种RF-PWM实现方案,本文通过公式推导确定了时钟抖动引入的非线性失真项,并给出了时钟抖动影响下不同方案输出脉冲信号底噪的数学解析式。最后利用Matlab软件,对不同方案在时钟抖动条件下的基波、奇次谐波和底噪进行仿真验证,结果证明理论推导正确;同时对信号的矢量幅度误差(EVM)和邻信道功率比(ACPR)进行仿真,分析出时钟抖动对信号带内外性能的影响。结果表明,时钟抖动引入的非线性失真主要体现为底噪的抬高;不同RF-PWM实现方案时钟抖动的影响特性各有不同,其中五电平方案对时钟抖动影响具有抑制效果,且随时间分辨力的增大而增大。     

A performance analysis of an all-optical clock extraction circuitbased on Fabry-Perot filter

A performance analysis of an optical clock extraction circuit based on a Fabry-Perot filter (FPF) is presented. Two analytical methods, time-domain and frequency-domain analysis, are developed in this paper. Time-domain analysis shows that there is no phase jitter in the extracted optical clock if the free spectral range (FSR) of the FPF is exactly equal to the signal clock frequency. Based on this, we obtain an analytical expression for root mean square (rms) amplitude jitter of the extracted optical clock in time domain, in which we have taken the impacts of carrier frequency drift and carrier phase noise into account. When the FSR of the FPF deviates from the signal clock frequency, both phase jitter and amplitude jitter will occur in the extracted optical clock. In this situation, a more general frequency-domain method is developed to deal with the timing performance under the assumption that carrier phase noise is negligible. This method allows us to calculate both rms phase jitter and rms amplitude jitter of the extracted optical clock. Using the developed two methods, we present a detailed numerical investigation on the impacts of finesse of the FPF, carrier frequency drift, resonator detuning, carrier phase noise, and optical pulse chirp on the timing performance. Finally, the application of this circuit in multiwavelength clock recovery is discussed     

利用PLL减小时钟前沿抖动的研究

针对通信系统数字信号处理中的时钟前沿抖动问题,给出时钟时域抖动和漂移的定义。在推导时域抖动和频域相位噪声关系式的基础上,对时钟的前沿抖动进行了测量和分析,指出偏离载波远端的相位噪声是构成抖动的主要因素。研究通过窄带锁相环(PLL)提纯时钟的方法,给出了提纯PLL的具体设计过程中主要环路参数:阻尼系数ξ和自然角频率ωn的选取和计算过程,说明设计过程中的注意事项。实现了对高抖动时钟信号的提纯。     

Detailed Theoretical and Experimental Characterization of 10 Gb/s Clock Recovery Using a Q-Switched Self-Pulsating Laser

A detailed characterization of the clock recovery properties of a self-pulsating, three-section distributed feedback laser is presented by directly comparing simulation and experimental results for the dependence of the RMS timing jitter of the recovered clock signal on important properties of the input signal. These properties include the duty cycle, peak power, extinction ratio, state-of-polarization, optical signal-to-noise ratio (OSNR), and waveform distortion due to residual group velocity dispersion and polarization mode dispersion. The permissible range for each of these is identified in terms of the RMS timing jitter of the recovered clock signal being less than 2 ps. In particular, the self-pulsating laser is effective for input signals degraded by amplified spontaneous emission noise as it provides this level of jitter performance for input OSNRs larger than 8.8 dB (0.1 nm noise bandwidth).     

Timing Jitter Measurement of Intrinsic Random Jitter and Sinusoidal Jitter Using Frequency Division

This paper presents a new method for measuring random timing jitter or sinusoidal timing jitter in signals of telecommunication devices. The method uses a divide-by-M circuit to reduce the frequency and the number of clock samples, and applies the Hilbert transform to measure the timing jitter. This new frequency division method is validated with experimental data from a serializer-deserializer device and a modulated signal source generating a 2.5 GHz FM signal.     

Short-term frequency stability of clock generators for multigigahertz rapid-single-flux quantum digital circuits

Superconducting digital systems based on Josephson junctions have generally used a synchronous timing strategy. A master clock signal is used to delimit a data window during which the system changes state and data is transferred from one block to the next. The temporal stability of the clock signal has a profound effect on the performance of rapid single flux quantum (RSFQ) digital systems. In particular, short-term clock fluctuations, or clock jitter, can degrade system performance due to the hazard of timing constraint violations. The successful development of large-scale RSFQ digital systems will require highly stable multigigahertz on-chip clock sources. To meet this need, methods for characterizing and measuring the short-term stability of such sources are required. We identify the relevant figure of merit to characterize and compare various clocks: the cycle-to-cycle standard deviation of the clock periods. We present experimental techniques for the measurement of this figure of merit and apply them to the measurement of jitter in a clock generator used often in RSFQ systems, the ring oscillator. High-frequency phase noise measurements found the jitter of a 9.6-GHz clock to be in the range from 0.6% to 0.36% of the clock period. The measured values of clock jitter fell within the 95% confidence interval of our stochastic circuit simulations. This was sufficient evidence to conclude that thermal noise from the resistors in the circuit may be the dominant source of jitter in the ring oscillator.     

Additive noise and jitter performance analysis of passive optical interferometers operated at ultrahigh rates

In this paper, we theoretically associate the additive noise, the amplitude jitter and the timing jitter at the input and output of passive optical interferometers. We make use of the theoretical results to assess the noise and jitter performance of interferometer based applications such as pulse repetition frequency multiplication and clock recovery. We show that, for both applications, interferometers may successfully reduce the noise and the jitter existing in the input signals, and thus yield very high quality output signals. Furthermore, we focus on the practical aspects of deploying Fabry-Pe/spl acute/rot interferometers in rate multipliers and clock recoveries, and provide rules for selecting the characteristics of the Fabry-Pe/spl acute/rot interferometer to meet specific quality requirements for the output signal.     

基于放大反馈激光器高速全光时钟提取的研究

为了研究放大反馈激光器全光时钟提取的性能,采用单边带相位噪声功率谱积分的方法,对40Gbit/s无恶化信号和噪声恶化信号分别进行了时钟提取实验,计算了所提取时钟的时间抖动。同时还测量了放大反馈激光器的锁定范围。通过实验取得了恶化前后所提取时钟的时间抖动分别为130fs和150fs,放大反馈激光器的锁定范围为234MHz。结果表明,基于放大反馈激光器的全光时钟提取方案对噪声恶化具有较强的容忍度,而且具有较宽的锁定范围。这一结果对于全光时钟提取技术的进一步发展具有重要意义。     

Jittery Signal Generation for High-Speed Interconnect Simulation

By generating clock and data waveforms in the frequency domain through a truncated Fourier series, absolute control over both voltage noise and symbol transition timing is achieved. A parameterized Fourier series signal model is derived and used to form clock and data waveforms exhibiting arbitrary noise and jitter characteristics. The method not only facilitates more accurate interconnect modeling in tools like Matlab and Simulink, but also provides a simple means for generating realistic signals that may be imported into Spice-based simulators.      

Experimental Study of Pattern-Independent Phase Noise Accumulation in an All-Optical Clock Recovery Chain Based on Two-Section Gain-Coupled DFB Lasers

The pattern-independent phase noise accumulation in a chain of all-optical clock recovery devices (CRDs) based on two-section gain-coupled distributed feedback (TS-DFB) laser operating in the coherent mode is studied experimentally and theoretically. A simple theoretical model, where the CRD output phase noise is equal to the sum of the phase noise introduced by the CRD and the CRD input phase noise filtered by the phase noise transfer function, has been proposed for the CRD equivalent phase noise model. The accumulation of pattern-independent phase noise is investigated experimentally and theoretically for different cut-off frequencies of the phase noise transfer function of the TS-DFB laser and two different optical signal to noise ratios. It is shown that, due to the phase noise added by the CRD, phase noise accumulates in the passband of the phase noise transfer function, with the phase noise transfer function well approximated by a first-order lowpass filter. Excellent qualitative agreement between the experimental results and the theoretical model is observed. Also, it is concluded that the phase noise accumulation model for CRD, where the recovered clock is locked to the optical power of the incoming clock signal, presented by other authors holds in a qualitative point of view for the TS-DFB laser operating in the coherent mode. Since the root-mean-square (rms) of the timing jitter is proportional to the square root of the integrated power spectral density of the phase noise, the results show that a smaller cut-off frequency of the phase noise transfer function does not lead to a smaller rms value of the pattern-independent timing jitter along the chain of all-optical CRDs based on TS-DFB laser. It is shown that the minimum rms of the pattern-independent timing jitter along the CRD chain results from a compromise between the cut-off frequency of the phase noise transfer function and the phase noise introduced by the TS-DFB laser.     

Multicast-enabled high-speed VCSEL technology for flexible data center networks

We experimentally demonstrate the multiple signal modulation on a single class 10 G vertical cavity surface emitting laser (VCSEL) carrier at 1 310 nm for next generation multicast-enabled data center networks. A 10 Gbit/s data signal is directly modulated onto a single mode VCSEL carrier. To maximize carrier spectral efficiency, a 2 GHz reference frequency (RF) clock tone is simultaneously modulated on the VCSEL phase attribute. The inherent VCSEL orthogonal polarization bistability with changing bias current is further exploited in transmission of a polarization based pulse per second (PPS) timing clock signal. Therefore, we simultaneously transmit a 10 Gbit/s directly modulated data, 2 GHz phase modulated RF and a polarization-based PPS clock signals using a single mode 10 GHz bandwidth VCSEL carrier. It is the first time that a single class 10 G VCSEL carrier is reported to transmit a directly modulated data, phase modulated RF clock and polarization based PPS timing signal simultaneously in a single wavelength. A of G.652 single mode fibre (SMF) transmission over 3.21 km is experimentally attained. A receiver sensitivity of ?15.60 dBm is experimentally obtained for the directly modulated 10 Gbit/s data signal. A 3.21-km-long SMF transmission introduces a penalty of 0.23 dB to the data signal. The contribution of a 2 GHz phase modulated RF and a polarization-based PPS clock signal to this penalty is found to be 0.03 dB. An RF single-side band (SSB) phase noise values of ?82.36 dBc/Hz and ?77.97 dBc/Hz are attained without and with simultaneous directly modulated data and polarization-based PPS clock signals respectively for a 3.21-km-long SMF transmission. This work provides an alternative efficient and cost effective technique for simultaneous high-speed multiple information transmission to different network nodes within a data center network through shared network infrastructure.     

Statistical properties of timing jitter due to data echo in digitalmodem receivers

Consideration is given to the influence of the noise and data sequences present in the received data signal on a nondecision-aided timing recovery scheme in digital modem receivers, It is known that white noise is not particularly disturbing for timing recovery, whereas data signals such as local echo (or residual echo) introduce a bias, called jitter, into the sampling recovered phase. It is shown that when the disturbing data signal has power P less than the power S of the useful signal (whose timing must be recovered), the jitter is sinusoidal with amplitude proportional to the ratio P/S. In the opposite situation, the bias increases indefinitely with time     

Reducing clock jitter by using Muller-C elements

A simple method for reducing the cycle-to-cycle jitter of clock signals is described. The method uses Muller-C elements to merge redundant clock signals. If the two clock signals have nearly the same average phase and independently-distributed phase noise, then the jitter at the Muller-C element?s output is less than that of the input signals. This method can be used to reduce jitter in sampling clocks for analogueto- digital conversion, and in clock distribution networks for VLSI systems.     

Data clock jitter in supersampling multiplex transmission

An estimate of the signal/noise ratio (SNR) degradation at the output of a data clock timing recovery circuit for multiplexed transmission using supersampling is presented. Both the effects of sampling clock jitter and data edge uncertainty are accounted for to determine the performance degradation as a function of the sampling frequency/data bit rate ratio D.     

A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM

This paper describes clock recovery circuits specifically designed for the hostile noise environment found aboard dynamic RAM chips. Instead of a phase-locked loop having a voltage-controlled oscillator, these circuits implement a delay-locked loop, thereby achieving low jitter and reduced sensitivity to noise on the substrate and the power supply rails. Differential signals are employed both in signal paths and in control paths, further decreasing noise sensitivity and simultaneously allowing operation from low voltage supplies. An unorthodox voltage controlled phase shifter, operating on the principle of quadrature mixing, yields a circuit with unlimited delay range (modulo 2π radians). Minor loops, enclosed within the overall loop feedback path, perform active duty cycle correction. Measured results show peak-to-peak jitter of 140 ps on the internal clock signal, and 250 ps on the external data pins, sufficiently small to allow 500 Megabyte/s transfer rates at the I/O interface     

一种应用于阵列TDC的低抖动锁相环设计

传统的PLL（Phase Locked Loop）电路受限于环路参数的选定,其相位噪声与抖动特性已经难以满足大阵列、高精度TDC（Time-to-Digital Converter）的应用需求.本文致力于PLL环路带宽的优化选取,采取TSMC 0.35μm CMOS工艺实现了一款应用于TDC的具有低抖动、低噪声特性的锁相环（Phase Locked Loop,PLL）电路,芯片面积约为0.745mm×0.368mm.实际测试结果表明,在外部信号源输入15.625MHz时钟信号的条件下,PLL输出频率可锁定在250.0007MHz,频率偏差为0.7kHz,输出时钟占空比为51.59%,相位噪声为114.66dBc/Hz@1MHz,均方根抖动为4.3ps,峰峰值抖动为32.2ps.锁相环的相位噪声显著降低,输出时钟的抖动特性明显优化,可满足高精度阵列TDC的应用需要.     

Radio frequency digital-to-analog converter

Dynamic performance of high-speed high-resolution digital-to-analog converters (DACs) is limited by distortion at the data switching instants. Inter-symbol interference (ISI), imperfect timing synchronization, and clock jitter are all culprits. A DAC output controlled by an oscillating waveform is proposed to mitigate the effects of switching distortion and clock jitter. This architecture has the additional benefit of mixing the DAC impulse response energy to a higher frequency, allowing a high-frequency image of the input to be used as the output. This has the potential for better noise performance and power and hardware savings relative to a conventional DAC+mixer architecture. A narrow-band sigma-delta (/spl Sigma//spl Delta/) DAC with eight unit elements is chosen to demonstrate the radio frequency digital-to-analog converter (RF DAC) concept in a 1.8-V 0.18-/spl mu/m CMOS technology. Measured single-tone SFDR is -75 dBc, SNR is 53 dB, and two-tone IMD3 is -70.8 dBc for a 17.5-MHz band centered at 942 MHz. SNR performance is shown to have the predicted dependence on the phase alignment of the data clock and oscillating pulse.     

An Analytical Approach for Quantifying Clock Jitter Effects in Continuous-Time Sigma–Delta Modulators

Continuous-time sigma–delta modulators (CTSDMs) may suffer severe performance degradation from the timing error in a quantizer clock. We present an analytical approach to quantify the performance loss due to clock jitter in a CTSDM. Unlike many prior works that model the timing error of clocks as additive white Gaussian phase noise, we propose a jitter model that exhibits an auto-regression form, so we term it auto regressive (AR) jitter. This AR jitter model shows exactly the same jitter behavior as that of a clock generated by practical phase-locked loops. Based on this AR jitter model, we establish an analytical approach to examine the intricate effects of clock uncertainty on CTSDM system performance. We demonstrate the validity of the proposed analytical method by showing its excellent agreement with simulation results. The analytical method enables a profound insight into the problem of how clock jitter degrades the system performance and also provides a guideline on how to minimize the detrimental effects of clock jitter.     

Carrier and Clock Recovery for 8 PSK Synchronous Demodulation

Synchronous demodulation of Phase-shift-keyed transmissions requires the recovery of carrier and clock timing signals. Envelope detection of the 70 MHz IF signal is used to recover clock, and baseband processing is used to recover carrier for an 8 PSK digital radio with a data rate of 90 Mbits/s in the 11 GHz band. A sequential phase detector is used in a high noise application. Two versions of the carrier recovery circuit are presented. The first one employs hot carrier diode quads to form a compound Costas loop. The second one employs ECL exclusive-OR gates. Emphasis is placed on providing high performance while conserving energy, space, and manufacturing cost.