一种高性能CMOS电荷泵的设计

设计了一种用于电荷泵锁相环的CMOS电荷泵电路。电路中采用3对自偏置高摆幅共源共栅电流镜进行泵电流镜像,增大了低电压下电荷泵的输出电阻,实现了上下两个电荷泵的匹配。为消除单端电荷泵存在的电荷共享问题,引入了带宽幅电压跟随的半差分电流开关结构,使电荷泵性能得以提高。设计采用0.18μm标准CMOS工艺。电路仿真结果显示,在0.35～1.3V范围内泵电流匹配精度达0.9%,电路工作频率达250MHz。     

一种应用于锁相环的增益提高型电荷泵设计

采用0.18μm 1.8V CMOS工艺设计一种增益提高型电荷泵电路,利用增益提高技术和折叠式共源共栅电路实现充放电电流的匹配.该电荷泵结构可以很大程度地减小沟道长度调制效应的影响,使充放电电流在宽输出电压范围内实现精确匹配,同时具有结构简单的优点.仿真结果表明,电源电压1.8V时,电荷泵电流为600μA,在0.3～1.6V输出范围内电流失配为0.6μA,功耗为3mW.     

一种用于PLL的新型电荷泵结构

本文设计了一种适用于PLL的新型电荷泵电路,将MOS开关置于源极,抑制电荷共享和电荷注入,并且采用可调节共源共栅结构增大输出阻抗,用于抑制电流失配。同时该电路具有结构简单、功耗低、充放电速度快等特点。采用Charter 0．35μm CMOS工艺模型,Mentor Graphics公司的Eldo进行仿真,在电荷泵输出电压范围为0．5～2．8V内,充放电电流匹配良好。     

锁相环频率合成器中的电荷泵设计

用TSMC 0.18μm CMOS工艺设计了一种电荷泵电路。传统的电荷泵电路中充放电电流有较大的电流失配,文章采用与电源无关的基准电流源电路,运用运算放大器和自偏置高摆幅共源共栅电流镜电路实现了充放电电流的高度匹配。仿真结果表明:电源电压1.8V时,电荷泵电流为0.5mA;在0.3V～1.6V输出电压范围内电流失配小于1μA,功耗为6.8mW。     

一种锁相环中高性能电荷泵电路

设计了一种新型电荷泵电路.该电荷泵电路采用可调节共源共栅结构增大输出阻抗,具有结构简单、速度快、充放电电流匹配性好、抑制了电荷注入等特点.采用0.18μmCMOS工艺模型以及Hspice仿真工具的仿真结果显示,输出电压在0.4~1.3V之间变化时,电荷泵的充放电电流处处相等.     

一种用于模数转换器时钟管理电路的电荷泵

采用0.13μm CMOS工艺,设计了一种用于模数转换器时钟电路的电荷泵。在共源共栅充/放电流源与其偏置电路之间增加传输门,有效地抑制了电荷泵关闭时产生的漏电流。同时,采用电流源提升技术,有效地提高了电荷泵充/放电电流支路的阻抗,抑制了沟道长度调制效应的影响,提高了电荷泵的电流匹配性。仿真结果表明,在1.2 V电源电压、20μA输出电流的条件下,输出电压的变化范围为0.13～0.93 V时,该电荷泵的充/放电电流失配低于1%。     

低杂散锁相环中的电荷泵设计

用TSMC0.18μm CMOS工艺设计并实现了一种电荷泵电路，传统的电荷泵电路中充放电电流有较大的电流失配,电流失配导致相位偏差,从而引起杂散并降低了锁相环的锁定范围，文中采用与电源无关的基准电流源电路,运用运算放大器和自偏置高摆幅共源共栅电流镜电路实现了充放电电流的高度匹配,从而降低了杂散。测试结果表明：电源电压1.8V时,电荷泵电流为0.475mA,在0.3-1.6V输出电压范围内电流失配小于10mA,功耗为6.8mW。     

低杂散锁相环中的电荷泵设计

用TSMC 0.18μm CMOS工艺设计并实现了一种电荷泵电路.传统的电荷泵电路中充放电电流有较大的电流失配,电流失配导致相位偏差,从而引起杂散并降低了锁相环的锁定范围.文中采用与电源无关的基准电流源电路,运用运算放大器和自偏置高摆幅共源共栅电流镜电路实现了充放电电流的高度匹配,从而降低了杂散.测试结果表明:电源电压1.8V时,电荷泵电流为0.475mA,在0.3～1.6V输出电压范围内电流失配小于10mA,功耗为6.8mW.     

锁相环频率综合器中高性能电荷泵设计

本文基于0.18μm CMOS工艺设计并实现了一种新的高性能电荷泵电路。采用宽输入范围的轨到轨运算放大器和自偏置共源共栅电流镜技术提高了电荷泵在宽输出电压范围内的电流匹配精度;同时,提出通过增加预充电电流源技术来提高电荷泵的初始充电电流,以缩短CPPLLs的建立时间。测试结果表明电荷泵在0.4～1.7V输出电压范围内失配电流小于0.4%,充电电流为100μA,预充电电流为70μA。在1.8V电源电压下,电荷泵电路锁定时的平均功耗为0.9mW。     

锁相环中高性能电荷泵的设计

设计了一种结构新颖的动态充放电电流匹配的电荷泵电路，该电路利用一种放电电流对充电电流的跟随技术，使充放电电流达到较好匹配，同时，在电荷泵中增加差分反相器，提高电荷泵的速度。采用Istsilicon 0．25μmCMOS工艺进行仿真，结果显示：输出电压在0．3—2．2V之间变化时，电荷泵的充放电电流处处相等。     

Charge pump with perfect current matching characteristics inphase-locked loops

Conventional CMOS charge pump circuits have some current mismatching characteristics. The current mismatch of the charge pump in the PLLs generates a phase offset, which increases spurs in the PLL output signals. In particular, it reduces the locking range in wide range PLLs with a dual loop scheme. A new charge pump circuit with perfect current matching characteristics is proposed. By using an error amplifier and reference current sources, one can achieve a charge pump with good current matching characteristics. It shows nearly perfect current matching characteristics over the whole VCO input range, and the amount of the reference spur is <-75 dBc in the PLL output signal. The charge pump circuit is implemented in a 0.25 μm CMOS process     

Gain-Boosting Charge Pump for Current Matching in Phase-Locked Loop

The charge pump (CP) circuit is a key element in a phase-locked loop (PLL). Its function is to transform the Up and Down signals from the phase/frequency detector into current. In CMOS CPs, which have Up and Down switches made of p-channel MOS and n-channel MOS, respectively, a current mismatch occurs when dumping the charge to the loop filter. This current mismatch of the CP in the PLL generates fluctuations in the voltage-controlled-oscillator input and subsequently, a large phase noise on the PLL output signals. In this brief, a new CP with good current matching characteristics is proposed. By using a simple gain-boosting circuit, good current matching characteristics can be achieved with less than 0.1% difference of the Up/Down current over the CP output voltage ranges of 0.8-2.2 V and 0.5-1.2 V on 0.35-mum 3.3-V and 0.18-mum 1.8-V CMOS processes, respectively. The proposed CP circuit is simulated and verified by HSPICE with 0.35-mum 3.3-V and 0.18-mum 1.8-V CMOS parameters     

锁相环中克服非理想因素的鉴相器和电荷泵设计

讨论了锁相环中鉴相器和电荷泵中非理想因素及其克服方法.电路设计采用SMIC 0.18 μm CMOS工艺和Cadence Spectre仿真器.通过在重置反馈路径上加入延迟单元的方法来消除鉴相器的死区.比较了两种传统电荷泵电路的设计方法,通过加入Replica Bias电路和单位增益运放,实现了上下电流的高匹配性.     

Reduction of pump current mismatch in charge-pump PLL

A charge pump that minimises the mismatch between the charging and discharging currents and keeps the currents constant across a wide output voltage range is described. The improved current matching helps reduce the static phase offset and reference spur of a chargepump phase-locked loop (PLL) and the constant currents help control the PLL dynamics precisely. The proposed charge pump with dual compensation circuits demonstrates current mismatch of less than 3.2% and pump-current variation of 1.7% over the output voltage ranging from 0.2 to 1.0 V in the 0.13 μm CMOS process with 1.2 V supply.     

显示控制CMOS锁相环频率合成器设计

从工程的角度出发,设计了一个应用于显示控制芯片的新颖实用的CMOS锁相环频率合成器.详细论述了系统设计的关键问题,研究了电荷泵充放电电流匹配、精度和输出电压等工程设计问题,并对环路滤波器的计算和仿真以及压控振荡器的噪声性能进行了研究.采用1st Si 0.25μm的CMOS混合信号工艺对整个电路系统进行了带版图寄生的后仿真,仿真结果表明锁相环频率合成器设计的正确性.     

An evaluation of MOS interface-trap charge pump as an ultralow constant-current generator

Explores the MOS interface-trap charge-pump as an ultralow constant-current generator for analog CMOS applications. Charge pumping techniques in general are more suitable than conventional continuous-time techniques for ultralow current generation because the linear controllability of current by frequency is maintained regardless of the level of current. An interface-trap pump has the same property but the minimum charge it puts out per cycle is at least two orders of magnitude smaller than that of a switched-capacitor charge pump. This helps generate the same current more accurately at a much higher frequency with a much smaller filter capacitance. The paper presents a simplified model of the terminal characteristics of the interface-trap pump and an evaluation of its performance as a stand-alone current generator. Cascoding and complementary pumping are introduced as measures of performance improvement. Temperature sensitivity, pulse feedthrough, controllability, matching, reliability, and trimming issues are addressed. Transconductor circuits built with the charge pump are presented and experimentally evaluated.     

Design and noise analysis of a fully-differential charge pump for phase-locked loops

A fully-differential charge pump (FDCP) with perfect current matching and low output current noise is realized for phase-locked loops (PLLs). An easily stable common-mode feedback (CMFB) circuit which can handle high input voltage swing is proposed. Current mismatch and current noise contribution from the CMFB circuit is minimized. In order to optimize PLL phase noise, the output current noise of the FDCP is analyzed in detail and calculated with the sampling principle. The calculation result agrees well with the simulation. Based on the noise analysis, many methods to lower output current noise of the FDCP are discussed. The fully-differential charge pump is integrated into a 1-2 GHz frequency synthesizer and fabricated in an SMIC CMOS 0.18 μm process. The measured output reference spur is -64 dBc to -69 dBc. The in-band and out-band phase noise is -95 dBc/Hz at 3 kHz frequency offset and -123 dBc/Hz at 1 MHz frequency offset respectively.     

低杂散锁相环中电荷泵的设计

采用IBM 0.18 μm CMOS工艺,设计了一款应用于433 MHz ASK接收机中低杂散锁相环的电荷泵电路.设计采用与电源无关的带隙基准偏置电流源和运算放大器,实现了电荷泵充放电电流源的精确匹配,有效抑制了传统电荷泵对锁相环锁定状态中杂散信号的影响.电路在Cadence的Spectre工具下进行仿真,结果表明:当电源电压为1.8 V、参考电流为30 μA、输出电压范围在0.5～1.5 V时,充放电电流精确匹配,杂散小于-80 dB,其性能符合接收机系统要求.     

Design to suppress return-back leakage current of charge pump circuit in low-voltage CMOS process

A new charge pump circuit has been proposed to suppress the return-back leakage current without suffering the gate-oxide reliability problem in low-voltage CMOS process. The four-phase clocks were used to control the charge-transfer devices turning on and turning off alternately to suppress the return-back leakage current. A test chip has been implemented in a 65-nm CMOS process to verify the proposed charge pump circuit with four pumping stages. The measured output voltage is around 8.8 V with 1.8-V supply voltage to drive a capacitive output load, which is better than the conventional charge pump circuit with the same pumping stages. By reducing the return-back leakage current and without suffering gate-oxide overstress problem, the new proposed charge pump circuit is suitable for applications in low-voltage CMOS IC products.