3–5 GHz FSK-OOK ultra wideband transmitter based on memristive ring oscillator

The compatibility of a memristor with CMOS technology has attracted the attention of many researchers to explore its application further. In this work, an ultra low-power and low-complexity ultra wideband (UWB) chirp transmitter based on memristive ring oscillator (RO) is designed in 0.18 µm TSMC CMOS technology. The Chirp waveform was chosen because of its low side-lobes and large time-bandwidth product, which allows for more spectrum use. OOK and FSK modulation are supported by the proposed UWB chirp transmitter. The chirp frequency is controlled linearly with time across the pulse duration using memristors. The binary data "1" and "0" are encoded using distinct chirp frequencies in FSK TX. The simulation results show a maximum TX output pulse of 457 mV _Vpp with a pulse width of 21 ns. The overall DC power consumption for a pulse repetition frequency (PRF) of 20 MHz is 0.328 mW, equivalent to an energy consumption of 16.4 pJ/pulse. The simulated output amplitude for OOK TX is 453 mV Vpp with a pulse width of 48 ns and a PSD of ? 10 dB over a frequency range of 3.2 to 4.8 GHz. The overall power consumption at 10 MHz PRF is 0.136 mW, which corresponds to an energy consumption of 13.6 pJ/pulse.

     

New design of 3.2–4.8 GHz generator for multi-bands architecture of UWB communication

In this paper a new design of Ultra-Wide Band (UWB) generator is presented. This circuit is the most important block in multi-bands transmitter architecture of UWB communication system. The proposed UWB generator is composed of multi-bands voltage controlled oscillator (VCO), mixer and rectangular pulse generator which consist of ring oscillator, time delay and AND gate function. The UWB generator is based on multiplying the rectangular pulse envelope to a continuous sinusoidal wave in order to generate the UWB signal. This UWB generator circuit produces an output signal which is characterized by the bandwidth of 1600 MHz divided into three sub-bands of 528 MHz, centered at frequencies of 3.432, 3.96, 4.488 GHz and the limited Power Spectral Density (PSD) is −41.44 dBm/MHz. The maximum amplitude of UWB signal is 214 mV, the pulse is during of 3 ns and the pulse repetition period (PRP) is 32 ns. The power consumption is approximately equal to 26 mW at a voltage supply of 2.5 V. This topology is designed in CMOS 0.35 μm AMS process technology.     

A fully integrated differential impulse radio transmitter

This paper presents a fully integrated differential impulse radio transmitter for ultra-wideband (UWB) applications. The design features low power dissipation, simple hardware, and a precise differential pulse shape. The transmitter employing the time hopping pulse position modulation (TH-PPM) scheme supports eight simultaneous users’ access with 2.5-ns hopping time allocated in a frame time of 20 ns. A differential 5th-derivative Gaussian pulse generator (PG) is designed for the first time to regulate the pulse shape so as to automatically satisfy the Federal Communications Commission (FCC) spectrum mask. The transmitter in a 1.8-V 0.18-μm CMOS process is realized in an IC area of 629 μm × 797 μm for its all digital circuit design. The measured digital pulse width of the TH-PPM pulse train is 2.5 ns and the measured 5th-derivative Gaussian pulse has a peak-to-peak amplitude of 154 mV and a pulse width of 820 ps. The power dissipation of the transmitter is 23 mW.     

Ultra-Wideband, Low-Power, Inductorless, 3.1�C4.8?GHz, CMOS VCO

A low-power, inductorless, UWB CMOS voltage controlled oscillator is designed in 0.18 μm CMOS technology targeting to a UWBFM transmitter application. The VCO is a Double-Cross-Coupled Multivibrator and generates output frequencies ranging from 1.55 GHz to 2.4 GHz. A low-power frequency doubler based on a Gilbert cell, which operates in weak inversion, doubles the VCO tuning range from 3.1 GHz to 4.8 GHz. The proportionality between the oscillation frequency and the bias current is avoided in this case for the entire achieved tuning range resulting in a low-power design. The selected architecture provides high suppression, over 45 dB, for the 1^st and 3^rd harmonics, while enabling high-frequency operation and conversion gain due to the unbalanced structure and the single-ended output. The proposed VCO draws 4 mA from a 1.8 V supply, it has a phase noise of −76.7 dBc/Hz at 1 MHz offset from the center frequency, while it exhibits a very high ratio of tuning range (43%) over power consumption equal to 7.76 dB.     

A PLL based WSN transmitter and I/Q LO signal generator at 430–435 MHz

A fully integrated Phase-Locked Loop (PLL) based transmitter and I/Q Local Oscillating (LO) signal generator used for half-duplex Wireless Sensor Networks (WSN) transceivers is proposed. Instead of one 430–435 MHz PLL for frequency synthesizing, a 1.72–1.74 GHz PLL is designed together with a 1/4 frequency divider. Then the chip area of the inductors in the Voltage-Controlled Oscillator (VCO) is decreased to about 1/16, and I/Q dual-path LO signals can be obtained without additional power consumption. A Gray-code controlled prescaler is proposed to avoid the glitches and uncertain states, and then the frequency dividing accuracy is improved by 17%. A Gauss Frequency Shift Keying (GFSK) transmitter with a pipeline modulator is proposed, the 1st and 2nd Adjacent Channel Power Ratio (ACPR) are −19.9 and −20.7 dBc, respectively. A mathematical spur model of 1/4 frequency dividers is built here, and then a low-spur 1/4 frequency divider composed of our proposed improved Current Mode Logic (CML) latches is designed. The testing results show that the reference spurs are −61.2 dBc@20 MHz and −57.7 dBc@40 MHz at the output of the PLL, and −70.5 dBc@20 MHz and −66.6 dBc@40 MHz at the output of our 1/4 divider. With 2.6-mW power consumption, our proposed 1/4 frequency divider has a phase-noise contribution of only 0.5 dBc/Hz@500 kHz and 0.2 dBc/Hz@1 MHz.     

A Fully Differential Digital CMOS UWB Pulse Generator

A new fully digital CMOS pulse generator for impulse radio ultra-wideband (UWB) systems is presented. First, the shape of the pulse which best fits the FCC regulation in the 3.1–5 GHz sub-band of the entire 3.1–10.6 GHz UWB bandwidth is derived and approximated using rectangular digital pulses. In particular, the number and the width of pulses that approximate an ideal template are found through an ad hoc optimization methodology. Then a fully differential digital CMOS circuit that synthesizes the pulse sequence is conceived and its functionality demonstrated through post-layout simulations. The results show a very good agreement with the FCC requirements and a low power consumption.     

On the Impact of Ultra Wide Band (UWB) on Macrocell Downlink of CDMA-PCS System

In this paper, we present an analytical model to quantify the effect of the Ultra-Wide Band (UWB) transmitters on the CDMA-PCS downlink range and normalized capacity. The effect is given for different configuration and environments. Our analysis shows that, for a single UWB transmitter, an UWB power density of −78dBm/MHz is the maximum permitted power density to have only PCS macrocell capacity reduction of 1% when the distance between the PCS mobile and the UWB transmitter is 1 m. For the multiple UWB transmitters case, a power density of −80dBm/MHz, is the maximum permitted power density to have only PCS macrocell capacity reduction of 1% when the distance between the PCS mobile and the UWB transmitter is 1 m.     

A UWB-IR Transmitter With Digitally Controlled Pulse Generator

A novel transmitter for ultra-wideband (UWB) impulse radio has been developed. The proposed architecture enables low-power operation, simple design, and accurate pulse-shape generation. The phase and amplitude of the pulse are controlled separately and digitally to generate a desired pulse shape. This digital control method also contributes to the low-power transmission and eliminates the need for a filter. The transmitter is fabricated using a 0.18-mum CMOS process. The core chip size is only 0.40 mm². From experimental measurements, it was found that the generated signal satisfied the FCC spectrum mask, and the average power dissipation was only 29.7 mW at A 2.2-V supply voltage. Therefore, the developed UWB transmitter generates accurate pulses with low power consumption and simple design architecture     

A 4 Gbps current-mode transmitter for 12-bit 250 MSPS ADC

A 4 Gbps transmitter for a 12-bit 250 MSPS pipelined ADCs is presented. A low power current mode (CM) output driver with reverse scaling technique is proposed. A high speed, low power combined serializer is implemented to convert 12 bit parallel data into a seria1 data stream. The whole transmitter is used in a 12-bit 250 MSPS pipelined ADC for the digital output buffer and fabricated in 180 nm 1. 8 V 1P5M CMOS technology. Test results show that the transmitter provides an eye height greater than 800 mV for data rates of both 2 Gbps and 4 Gbps, the 12-bit 250 MSPS ADC achieves the SNR of 69.92 dBFS and SFDR of 81.17 dB with 20.1 MHz input at full sampling speed. The ADC with the 4 Gbps transmitter consumes the power consumption of 395 mW, where the power consumption of transmitter is 75 mW. The ADC occupies an area of 2.5×3.2 mm², where the active area of the transmitter block is 0.5×1.2 mm².     

Analysis and Design of a W-band Coherent Pulsed Transmitter Using a New Timing Scheme

This paper presents the analysis and design of a new W-band pulsed transmitter using injection-locking to achieve pulse-to-pulse coherence and power amplification. First, a new timing scheme is introduced to solve the asynchronous problem that commonly exists in multistage injection-locked transmitters. Then the pulsewidth of one stage in the transmitter is intentionally made somewhat longer than that of the next stage, and thus, the rising edge noise of the output pulse is minimized. Finally, a high coherent peak power can be achieved without using complex power combing techniques. To verify our analysis, a W-band pulse transmitter is designed and fabricated that operates at a 78 ns pulsewidth, 50 μs pulse period, and 600 MHz locking bandwidth. The experiment shows that a coherent peak power of 22.3 ± 0.9 W was achieved at 94.2 GHz.     

Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation

The successful realization of a wireless body area network (WBAN) requires innovative solutions to meet the energy consumption budget of the autonomous sensor nodes. The radio interface is a major challenge, since its power consumption must be reduced below 100 /spl mu/W (energy scavenging limit). The emerging ultra-wide-band (UWB) technology shows strong advantages in reaching this target. First, most of the complexity of an UWB system is in the receiver, which is a perfect scenario in the WBAN context. Second, the very little hardware complexity of a UWB transmitter offers the potential for low-cost and highly integrated solutions. Finally, in a pulse-based UWB scheme, the transmitter can be duty-cycled at the pulse rate, thereby reducing the baseline power consumption. We present a low-power UWB transmitter that can be fully integrated in standard CMOS technology. Measured performances of a fully integrated pulse generator are provided, showing the potential of UWB for low power and low cost implementations. Finally, using a WBAN channel model, we present a comparison between our UWB solution and state-of-the-art low-power narrow-band implementations. This paper shows that UWB performs better in the short range due to a reduced baseline power consumption.     

Impulse Radio UWB Pulse Shaping for Cognitive Radio Applications

This paper introduces a method of shaping impulse radio Ultra Wideband (UWB) pulses in the context of using higher than normal power transmissions and cognitive radio to provide the ability for such systems to avoid interference with primary users in shared radio spectrum. Using multiple shaping frequencies and a standard Gaussian pulse shape, pulses are shaped in the time domain, according to the requirements of the frequency spectrum in use, and any limits on power spectral density. Simulation results are presented for an example scenario based on measured data, along with a more general approach applicable to a free spectrum scenario. We show that the introduced shaping technique ensures that up to 98.8% of capacity of the UWB bandwidth within the conventional spectrum mask can be achieved for a time scaling factor of 11 ns and shaping frequency of 30 MHz. Capacity well in excess of the 100% achievable with the spectral mask is possible when the transmit power is permitted to increase in areas of ‘white space’ spectrum.     

Design of a laminated current cell relocation 12-bit CMOS D/A converter with a high output impedance technique and a merged switching logic

A compact and low power 12-bit 300 MS/s current steering CMOS D/A converter is presented. The architecture of the D/A converter is based on the current steering 6 + 6 segmented type with a laminated current cell relocation technique. In order to improve the linearity and glitch noise, a high output impedance analog current cell is designed. Furthermore, for the purpose of reducing the chip area and power dissipation, a noble merged switching logic and a compact layout technique are proposed. To verify its performance, the chip was fabricated with 0.13 μm thick-gate 1-poly 6-metal N-well Samsung CMOS technology. The effective chip area is 0.26 mm² (510 × 510 μm) with a power consumption of 100 mW. The measured INL and DNL are within ±3LSB and ±1LSB, respectively. The measured SFDR is about 70 dB, when the input frequency is 1 MHz at a clock frequency of 300 MHz.     

A 3–5 GHz low-power high-speed radiated power tuning UWB transmitter

To satisfy the different radiated power requirements for the ultra-wideband (UWB) data transmitting in the implantable electronic devices or the wireless component interconnections, a novel low-power high-speed UWB transmitter with radiated power tuning was proposed. The tunable radiated power is achieved by a UWB RF buffer with a peak value controller. The designed low-complex narrow pulse generator and digital ring on–off VCO ensure a high speed transmitting. The low power is realized by using a subtractor to eliminate the base-band component from the output of the VCO and making the UWB RF buffer and the VCO operating in standby mode. The design was fabricated by a standard 0.18 μm CMOS technology. The test results show that the design can achieve maximum data-rate of 250 Mbps, frequency bandwidth from 3 to 5 GHz, radiated power tuning from −40 dBm to −60 dBm, low-power of 8 pJ/bit, and small circuit area of 0.18 mm².     

A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a

We propose an all-digital UWB transmitter architecture that exploits the low duty cycle of impulse-radio UWB to achieve ultra-low power consumption. The design supports the IEEE 802.15.4a standard and is demonstrated for its mandatory mode. A digitally controlled oscillator produces the RF carrier between 3 and 10 GHz. It is embedded in a phase-aligned frequency-locked loop that starts up in 2 ns and thus exploits the signal duty cycle that can be as low as 3%. A fully dynamic modulator shapes the BPSK symbols in discrete steps at the 499.2 MHz chip rate as required by the standard. The transmitter can operate in any 499.2 MHz band of the standard between 3.1 and 10 GHz, and the generated signal fulfills the emission spectral mask. The jitter accumulation over a burst is below 6 ps_RMS, which is within specifications. The transmitter was realized in a 1 V 90 nm digital CMOS technology, and its power consumption drawn from a 1 V supply is from 0.65 mW at 3.1 GHz to 1.4 mW at 10 GHz for a 1 Mb/s data rate.     

All-digital low-power CMOS pulse generator for UWB system

An all-digital CMOS ultra-wideband (UWB) pulse generator which complies with FCC regulations is presented. The proposed pulse generator generates a single UWB pulse satisfying FCC regulations without any filtering. The average power consumption of the whole circuit is 15.4 mW and 675 /spl mu/W at the pulse repetition frequency of 500 and 1 MHz, respectively.     

FM-UWB for Communications and Radar in Medical Applications

UWB technology is a useful and safe new technology in the area of wireless body area network. There are many advantages of using UWB as a communication standard for biomedical applications. Due to very low radiated power (−41.3 dBm/MHz), low power consumption, good coexistence with the other existing instruments, Robustness to interference and multipath. Moreover, one specific UWB technology, namely Frequency Modulated (FM)-UWB, has also an important advantage, which make it even more convenient for medical applications, such as simple low cost design (FM, no receive LO, no carrier synchronization as in IR-UWB). UWB technology has been also proposed radar applications such as: Non-Invasive Heart and Respiration Rate Monitoring; Detection of Cardiac Arrhythmias; Detection of Pathological Respiratory Patterns, particularly in Sudden Infant Death Syndrome (SIDS) and Sleep Apnea; Multi-Patient Monitoring; Detection and Non-Invasive Imaging of Breast Tumors. However, pulsed radar are mainly used for these applications. The main issue that is addressed in this paper is the integration of sensing and communication using FM-UWB and radar technology so that a single device can be obtained for two different operational mode. We have show that FM-UWB as radar can meet the requirements of typical biomedical applications such as Non-Invasive Heart and Respiration Rate Monitoring. Advantages and challenges of this integration are shown. Future perspectives of this novel activity will be drawn.     

An efficient power reduction technique for CMOS flash analog-to-digital converters

An efficient power reduction technique for CMOS flash analog-to-digital converter (ADC) is presented. The presented technique adopts the procedure with a simple coarse comparison first followed by a finer comparison later. Our ADC design does not decrease the total number of comparators, though it is able to reduce the power consumption. Subject to time signal controlling, the manipulation is to interchangeably shut down the comparator sections for the coarse comparison function. Experimental results show that this new method consumes about 48.14 mW at 400 MHz with 3.3 V supply voltage in TSMC 0.35 μm 2P4 M process. Compared with the traditional flash ADC, our low power method can reduce up to 47.8% in power consumption. The DNL of our proposed flash ADC is 0.5 LSB, the INL is 0.7 LSB, and the ENOB is 5.75 bits. The chip area occupies 0.4 × 0.9 mm² without I/O pads.     

New design of low power, 100 Mb-s IR-UWB pulse generator in 0.18 µm CMOS technology

A new method of impulse radio ultra-wideband (IR-UWB) pulse generation, with advantage of providing a “notch” like representation of pulse in the spectrum domain for particular control parameters values, is investigated in this paper. Low power pulse generator is composed of a glitch generator, a switched oscillator, a two-stage buffer and a pulse shaping filter. The proposed architecture, designed in UMC 0.18 µm CMOS technology, can operate in a single band from 3.3 GHz to 9.3 GHz or in a double, lower and higher UWB band (from 3 GHz to 9.15 GHz), suppressing frequencies in the WLAN band. Both spectrums fully comply with the corresponding FCC spectral mask, while the pulse generator regime and the spectrum range are determined by control signal values. Post-layout simulation results showed a pulse width of 0.5 ns, and a peak-to-peak amplitude of 211 mV for one band spectrum. The average power consumption is 0.89 mW corresponding to the energy consumption of 8.9 pJ/pulse for 100 MHz pulse repetition rate (PRF). The pulse duration is 1 ns and peak-to-peak amplitude is 202 mV in the case of the WLAN frequency band suppression. The total chip area is 0.31 mm². The pulse generator has been evaluated for the best performance supporting the on-off keying (OOK) modulation.     

Power-efficient switching-based CMOS UWB transmitters for UWB communications and Radar systems

This paper presents a new carrier-based ultra-wideband (UWB) transmitter architecture. The new UWB transmitter implements a double-stage switching to enhance RF-power efficiency, reduce dc-power consumption, and increase switching speed and isolation, while reducing circuit complexity. In addition, this paper also demonstrates a new carrier-based UWB transmitting module implemented using a 0.18-/spl mu/m CMOS integrated pulse generator-switch chip. The design of a UWB sub-nanosecond-switching 0.18-/spl mu/m CMOS single-pole single-throw (SPST) switch, operating from 0.45 MHz to 15 GHz, is discussed. The design of a 0.18-/spl mu/m CMOS tunable impulse generator is also presented. The edge-compression phenomenon of the impulse signal controlling the SPST switch, which makes the generated UWB signal narrower than the impulse, is described. Measurement results show that the generated UWB signal can vary from 2 V peak-to-peak with 3-dB 4-ns pulsewidth to 1 V with 0.5 ns, covering 10-dB signal bandwidths from 0.5 to 4 GHz, respectively. The generated UWB signal can be tuned to cover the entire UWB frequency range of 3.1-10.6 GHz. The sidelobe suppression in the measured spectrums is more than 15 dB. The entire CMOS module works under a 1.8-V supply voltage and consumes less than 1 mA of dc current. The proposed carrier-based UWB transmitter and the demonstrated module provide an attractive means for UWB signal generation for both UWB communications and radar applications.