Low-frequency noise characteristics of p-n-p InAlAs/InGaAs HBTs

The low-frequency noise characteristics of p-n-p InAlAs/InGaAs heterojunction bipolar transistors (HBTs) were investigated. Devices with various geometries were measured under different bias conditions. The base noise current spectral density (3.11 /spl times/ 10/sup -16/ A/sup 2//Hz) was found to be higher than the collector noise current spectral density (1.48 /spl times/ 10/sup -16/ A/sup 2//Hz) at 10 Hz under low bias condition (I/sub C/=1 mA, V/sub EC/=1 V), while the base noise current spectral density (2.04 /spl times/ 10/sup -15/ A/sup 2//Hz) is lower than the collector noise current spectral density (7.87 /spl times/ 10/sup -15/ A/sup 2//Hz) under high bias condition (I/sub C/=10 mA, V/sub EC/=2 V). The low-frequency noise sources were identified using the emitter-feedback technique. The results suggest that the low-frequency noise is a surface-related process. In addition, the dominant noise sources varied with bias levels.     

Striped-channel InAlAs/InGaAs HEMTs with shallow-grating structures

Striped-channel (SC) InAlAs/InGaAs HEMTs have been demonstrated with shallow gratings. The shallow grating structure keeps the gate from touching the channel layer and thus solves the gate leakage problem observed in the deep grating devices on InP substrates. Various channel widths have been realized to study the impact of the channel width on the dc and microwave performance. Due to the enhanced charge control in the SC HEMTs, enhanced transconductance/source-drain current (G_m /I_ds) and transconductance/output conductance (G_m /G_ds) were observed. Compared with conventional HEMTs, the SC HEMTs showed degraded f_T due to additional parasitic capacitances and improved f_max due to better carrier confinement     

Mesa-sidewall gate leakage in InAlAs/InGaAs heterostructurefield-effect transistors

InAlAs/InGaAs HFETs fabricated by conventional mesa isolation have a potential parasitic gate-leakage path where the gate metallization overlaps the exposed channel edge at the mesa sidewall. The existence of this path has been proven by fabricating special heterojunction diodes with different mesa-sidewall gate-metal overlap lengths. It is found that sidewall leakage is a function of the crystallographic orientation of the sidewall, and increases with channel thicknesses, sidewall overlap area, and InAs mole fraction in the channel. In HFETs fabricated alongside the diodes, sidewall leakage increased the subthreshold and forward gate leakage currents, and reduced the breakdown voltage     

Charge storage in InAlAs/InGaAs/InP floating gate heterostructures

Charge retention in floating gate InAlAs/InGaAs/InP field effect transistors is limited by lateral electron motion along the storage channel, a different direction for motion than found for AlAs/GaAs devices. Storage times as a function of temperature for the InP based alloy devices are reported and compared with similar AlAs/GaAs devices by using Poisson equation models.<>     

Low-frequency noise performance of self-aligned InAlAs/InGaAs heterojunction bipolar transistors

The first measurement of low-frequency noise performance for self-aligned InAlAs/InGaAs HBTs is reported. The 1/f noise obtained was around 20 dB lower than that for AlGaAs/GaAs HBTs at a fixed frequency, which is considered to be caused by the low surface recombination velocity of InGaAs.<>     

30-nm two-step recess gate InP-Based InAlAs/InGaAs HEMTs

Two-step recess gate technology has been developed for sub-100-nm gate InP-based InAlAs/InGaAs high-electron mobility transistors (HEMTs). This gate structure is found to be advantageous for the preciseness of the metallurgical gate length as well as a comparable stability to the conventional gate structure with an InP etch stop layer. The two-step recess gate is optimized focusing on the lateral width of the gate recess. Due to the stability of the gate recess with an InP surface, a laterally wide gate recess gives the maximum cutoff frequency, lower gate leakage current, smaller output conductance and higher maximum frequency of oscillation. Finally, the uniformity of the device characteristics evaluated for sub-100-nm HEMTs with the optimized recess width. The result reveals the significant role of the short channel effects on the device uniformity.     

InAlAs/InGaAs/InP HEMTs with high breakdown voltages using double-recess gate process

The DC and RF performance of InAlAs/InGaAs/InP HEMTs fabricated using a double-recess gate process are reported. A gate-drain breakdown voltage as high as 16 V was observed. The HEMTs also exhibited a high source-drain breakdown voltage near pinchoff of 16 V and a low RF output conductance of 6 mS/mm. For a 1.4 mu m gate length, an intrinsic transconductance of 560 mS/mm and f/sub T/ and f/sub max/ values of 16 and 40 GHz, respectively, were achieved.<>     

Drastic reduction of gate leakage in InAlAs/InGaAs HEMT's using apseudomorphic InAlAs hole barrier layer

Impact ionization in the channel of InAlAs/InGaAs HEMT's was shown to be a reason for excess gate leakage current. Hot electrons in the high field region of the channel under the gate generate electron-hole pairs. The generated holes can reach the gate (gate leakage) as well as the source, the electrons flow to the drain (kink effect). The number of holes reaching the gate strongly depends on the valence band discontinuity. In order to increase this valence band discontinuity a thin pseudomorphic InAlAs layer with high Al-content was inserted in the spacer of an InAlAs/InGaAs HEMT. The efficiency of this hole barrier was measured by photocurrent and DC measurements, while its influence on transport characteristics was measured by Hall and RF measurements. A reduction of gate leakage by a factor of 200 is demonstrated     

Impact ionization in InAlAs/InGaAs/InAlAs HEMT's

The kink effect and excess gate current in InAlAs/InGaAs/InAlAs HEMT's have been linked to impact ionization in the high field region of the channel. In this letter, a relationship is established between experimentally measured excess gate current and the tunneling of holes from the quantum well formed in the channel. The channel hole current is then obtained as the quotient of the excess gate current to the gate-voltage-dependent transmission probability. This channel hole current follows the exponential dependence of the ionization constant on the inverse electric field     

InAlAs/InGaAs/InP MODFET's with uniform threshold voltage obtainedby selective wet gate recess

Excellent uniformity in the threshold voltage, transconductance, and current-gain cutoff frequency of InAlAs/InGaAs/InP MODFETs has been achieved using a selective wet gate recess process. An etch rate ratio of 25 was achieved for InGaAs over InAlAs using a 1:1 citric acid:H₂O₂ solution. By using this solution for gate recessing, the authors have achieved a threshold voltage standard deviation of 15 mV and a transconductance standard deviation of 15 mS/mm for devices across a quarter of a 2-in-diameter wafer. The average threshold voltage, transconductance, and current-gain cutoff frequency of 1.0-μm gate-length devices were -234 mV, 355 mS/mm, and 32 GHz, respectively     

Submicrometer self-aligned recessed gate InGaAs MISFET exhibiting very high transconductance

A new submicrometer InGaAs depletion-mode MISFET with a self-aligned recessed gate structure is presented. The techniques used to implement this FET structure are angle evaporation for submicrometer pattern definition and sputter etching/wet chemical etching for channel recess. Highest transconductance observed was in excess of 250 mS/mm, with 200 mS/mm as a more typical value. The very high transconductance is attributed partly to the low source series resistance achieved in this structure, typically 0.5 Ω.mm or less. From the IV characteristics of these FET's, a saturation velocity equal to 2.4 × 10⁷cm/s at the drain end was deduced.     

Admittance spectroscopy of ring diode InGaAs/InAlAs/InP quantum-well structures

The admittance of ring planar diode Au/InGaAs/InP and Au/InGaAs/InAlAs heteronanostructures on i-InP has been studied. The structures are constituted by a silicon ??-doped layer and an InGaAs quantum well (QW) in InP or InAlAs epitaxial layers. An analysis of the capacitance-voltage and conductance-voltage characteristics yielded distribution profiles of the electron concentration and mobility in the vicinity of the QW and ??-doped layer. It is shown that lowering the temperature leads to an increase in the electron concentration and mobility in the QW.     

Molecular-beam epitaxy of InGaAs/InAlAs/AlAs structures for heterobarrier varactors

The molecular-beam epitaxy of InGaAs/InAlAs/AlAs structures for heterobarrier varactors is studied and optimized. The choice of the substrate-holder temperature, growth rate and III/V ratio in the synthesis of individual heterostructure regions, the thickness of AlAs inserts and barrier-layer quality are critical parameters to achieve the optimal characteristics of heterobarrier varactors. The proposed triple-barrier structures of heterobarrier varactors with thin InGaAs strained layers immediately adjacent to an InAlAs/AlAs/InAlAs heterobarrier, mismatched with respect to the InP lattice constant at an AlAs insert thickness of 2.5 nm, provides a leakage current density at the level of the best values for heterobarrier varactor structures with 12 barriers and an insert thickness of 3 nm.     

Ordering in InGaAs/InAlAs layers

The structure of InCaAs/InAlAs layers lattice matched to an InP substrate, grown on either (100) or on (110) with a 4° tilt toward [111] at 500 and 300°C has been investigated by transmission electron microscopy. High perfection resulted for the layers grown on [001] oriented substrates whereas growth on the near [110] substrates resulted in compositional nonuniformities, macrosteps formation, and ordering of the group III elements. This difference in structural perfection between the two sets of samples was also reflected in differences in electrical properties.     

Low-frequency dispersion of transconductance in GaAs JFETs andMESFETs with an ion-implanted channel layer

An analytical model of low-frequency dispersion of transconductanced in GaAs FETs which have nonuniform profiles of carrier concentration and mobility is reported. The frequency dependence of surface charge density is incorporated into the model as a variation in the source resistance of the FETs. The model explains the low-frequency dispersion of transconductance in GaAs p-n junction FETs (JFETs) and metal-semiconductor FETs (MESFETs), both of which have a channel layer formed by ion implantation. It is suggested that the low-frequency dispersion of transconductance can be attributed to the charge exchange which occurs with the surface states in GaAs FETs     

Anisotropic electroabsorption and optical modulation in InGaAs/InAlAs multiple quantum well structures

The first measurements to be made of large anistropic electroabsorption and modulation of long-wavelength light propagating along the plane of InGaAs/InAlAs multiple quantum well (MQW) structures grown by molecular beam epitaxy (MBE) are reported. Photocurrent response of waveguide p-i-n diodes is studied for incident light polarization parallel and perpendicular to the MQW layers. Photocurrent increase with reverse bias throughout the entire photoresponse spectrum is observed for both polarizations. The MQW p-in optical modulator shows a capacitance-limited pulse response of 250 ps and the modulation depth is 14 percent.     

Analysis of issues in gate recess etching in the InAlAs/InGaAs HEMT manufacturing process

We have developed an InAlAs/InGaAs metamorphic high electron mobility transistor device fabrication process where the gate length can be tuned within the range of 0.13 μm–0.16 μm to suit the intended application. The core processes are a two-step electron-beam lithography process using a three-layer resist and gate recess etching process using citric acid. An electron-beam lithography process was developed to fabricate a T-shaped gate electrode with a fine gate foot and a relatively large gate head. This was realized through the use of three-layered resist and two-step electron beam exposure and development. Citric acid-based gate recess etching is a wet etching, so it is very important to secure etching uniformity and process reproducibility. The device layout was designed by considering the electrochemical reaction involved in recess etching, and a reproducible gate recess etching process was developed by finding optimized etching conditions. Using the developed gate electrode process technology, we were able to successfully manufacture various monolithic microwave integrated circuits, including low noise amplifiers that can be used in the 28 GHz to 94 GHz frequency range.     

Ultra high transconductance 0.25 mu m gate MESFET with strained InGaAs buffer layer

The authors have successfully fabricated MBE-grown GaAs field effect transistors employing a strained MQW buffer layer. Quarter micron gate device showed transconductance as high as 1.460 mS/mm (900 mS/mm extrinsic) at a current density of 620 mA/mm. The measured f/sub c/ was 75 GHz. These high transconductances are, to the authors' knowledge, the best reported for GaAs MESFETs.<>     

High electrical performance liquid-phase HBr oxidation gate insulator of InAlAs/InGaAs metamorphic MOS-mHEMT

The InAlAs/InGaAs metal-oxide-semiconductor metamorphic high electron mobility transistors (MOS-mHEMTs) were demonstrated by using liquid-phase HBr treatment technology to form a high-quality gate insulator layer. In this study, liquid-phase HBr treatment technology was used instead of traditional plasma-assisted chemical vapor deposition (PECVD) because the proposed technology can prevent the device from plasma-induced damage. The novel HBr + ultraviolet (UV) illumination treated InGaAs provided a lower surface states such that MOS structure can be efficiently obtained. Besides, based on the atomic force microscopy (AFM) measurement, the native oxides film formed by HBr + UV illumination treatment also provided a better surface roughness compared to traditional NH₄OH and only HBr treatment solutions. It is beneficial for reducing the surface traps and lowering the leakage current in MOS-mHEMTs. Based on the flicker noise and load-pull power measurement results, HBr + UV treatment mHEMT achieved a low flicker noise at high current level and the power-added efficiency can be enhanced up to 9%. Therefore, the novel liquid phase method of HBr + UV illumination treatment exhibited a highly potential for low noise microwave power device applications.     

Delta-doping-enhanced InGaAs/InAlAs heterobarrier diodes

Modification of the effective conduction-band offset in InGaAs/InAlAs isotype heterojunctions by incorporating, during epitaxial growth, a doping dipole formed by alternate n⁺, p⁺ delta (δ-) doping is demonstrated. Greatly improved current rectification is found when the dipole polarity enhances the potential barrier