CMOS触发器在CP边沿的工作特性研究

CMOS触发器CP边沿时间与器件参数的关系,用实验展现了CP边沿时间过长时出现的异变现象,分析了传输门在CP边沿的共同导通问题,提出了CMOS触发器在CP边沿工作的电路模型,推导了CP边沿时间的计算公式,完善和深化了CMOS触发器动态工作电路理论。     

三值边沿触发器的研究

本文从实用考虑出发,利用时钟信号的竞争提出三值边沿触发器的逻辑设计,从而完整了对三轨三值触发器系列的研究。 作为多值数字系统中的关键部件,对多值存储单元的研究一直受到重视。研究表明,如果它们能用传统的集成技术与二值存储单元制作在同一芯片上,则可构成冗余态较少,可靠性较强,及电路较简单的混值计数器,这种计数器可以在系统中替代相应的二     

乏晰边沿的时序电路模型

本文对赫夫曼时序电路模型提出修正。确立了乏晰边沿集合的运算及性质。在布尔微分及乏晰边沿集合两个基础上,建立了乏晰边沿的时序电路模型。研完了乏晰毛刺的分明度量,最后提出了时序电路不分明状态的判定定理。因此,本文阐述的时序电路模型为时序电路故障测试产生算法及时序电路不分明状态的测试产生算法(逻辑正确性检查)提供了依据。     

基于MMX^TM技术的图象边沿和边沿交点的快速提取

介绍了Ｉｎｔｅｌ最新推出的ＭＭＸ＾ＴＭ技术及其在图象边沿和边沿交点提取快速算法实现中的应用。边沿提取的速度可达３０帧／秒。     

图像区域标记和边沿检测的两步法

区域是边沿的互补物，综合考虑二者有利于获得更好的图像分割算法。提出一种基于马尔可夫神经网络的区域标记和边沿检测的两步法。输入图像首先通过一个单层马尔可夫神经网进行多类别的区域标记处理，然后将区域轮廓作为初值，送入另一个神经网络进行边沿检测和修整处理。介绍了一种利用直方图分析的类别初始标记方法。对仿真图像和真实图像的实验均给出了很好的效果。     

基于Multisim软件的触发器仿真实验

RS触发器的电路简单,是构成各种集成触发器的基础电路。首先详细介绍了基本RS触发器的2种设计方法,并进行了比较分析。然后介绍由基本RS触发器设计的同步RS触发器和同步D触发器。最后介绍采用同步D触发器设计的边沿D触发器。采用Multisim软件分别对基本RS触发器、同步RS触发器、同步D触发器和边沿D触发器进行仿真,对仿真结果进行分析。通过Multisim软件进行仿真,有助于学生深入理解触发器的基本原理。     

彩色图像边沿色彩补偿检测方法

针对彩色图像边沿提取处理时,不能套用比较简单而成熟的黑白图像处理方法,本文提出的应用ＯＨＴＡＫ－Ｌ变换,将通常的（Ｒ,Ｇ,Ｂ）彩色空间转换为彩色特征（Ｉ２、Ｉ２、Ｉ３）空间,然后在（Ｉ２,Ｉ２,Ｉ３）空间进行灰度边缘分析,并以Ｉ１为主进行色彩边缘补偿,即可得到清晰且细致的边沿轮廓图。与彩色图像直接边沿提取及改变调色板变为黑白灰度图像后进行边沿提取比较,效果令是满意的。     

基于FPGA联合Sobel算法的实时图像边沿检测系统的设计与实现

边沿检测技术作为数字图像处理领域的重要一支,在目标匹配,交通管控,国防安全等多个领域有着广泛的应用,能够精确高效地实现边沿检测对于后续进行更高层次的图像识别以及图像处理有着密切的联系;为了实现实时有效的图像边沿检测提出了基于FPGA结合Sobel算法的实时图像边沿检测系统,硬件使用流水线结合并行处理的解决方案,能够有效提高图像处理的速度;算法设计采用Sobel算法,不但简化了运算同时获得了不错的检测效果;实验结果显示,系统可高效地达成实时图像边沿检测的设计目的,而且提升了图像的处理效率与边沿检测的效果,便于满足后续图像处理的要求。     

一种二维边沿检测滤波器

文章提出了一种新型二维边沿检测滤波器,利用二维滤波器模板与任意方向边沿的互相关最大值检测边沿,具有良好的噪声特性及较小的系统误差。     

基于路径边沿引导策略的蛇形机器人路径跟踪方法

为了控制蛇形机器人在路径边沿的引导下沿着期望路径运动,在基于角度对称性调节的方向控制方法的基础上,提出路径边沿引导策略.随着蛇形机器人的运动,路径的2个边沿交替作为有效边沿.利用传感器检测有效边沿,根据有效边沿获得临时目标点.临时目标点随着机器人的运动沿有效边沿不断更新.不断更新的临时目标点确定了路径的延伸方向.将临时目标点引入方向控制参数,从而使机器人根据路径边沿调节运动方向.仿真显示蛇形机器人能够在摩擦系数未知的地面上根据路径边沿调整运动方向.仿真结果验证该方法不仅能实现蛇形机器人跟踪期望路径,而且能实现蛇形机器人跟踪期望路径的中心线.     

时序逻辑电路分析与设计方法的研究及探讨

时序逻辑电路的分析与设计是《数字逻辑》课程中的重要教学内容,文章对时序逻辑电路分析与设计的方法进行了研究及探讨,包括公式法和表格法在时序逻辑电路的分析和设计过程中的应用。     

Design of dual-edge triggered flip-flops based on quantum-dot cellular automata

Quantum-dot cellular automata (QCA) technology has been widely considered as an alternative to complementary metal-oxide-semiconductor (CMOS) due to QCA’s inherent merits.Many interesting QCA-based logic circuits with smaller feature size,higher operating frequency,and lower power consumption than CMOS have been presented.However,QCA is limited in its sequential circuit design with high performance flip-flops.Based on a brief introduction of QCA and dual-edge triggered (DET) flip-flop,we propose two original QCA-based D and JK DET flip-flops,offering the same data throughput of corresponding single-edge triggered (SET) flip-flops at half the clock pulse frequency.The logic functionality of the two proposed flip-flops is verified with the QCADesigner tool.All the proposed QCA-based DET flip-flops show higher performance than their SET counterparts in terms of data throughput.Furthermore,compared with a previous DET D flip-flop,the number of cells,covered area,and time delay of the proposed DET D flip-flop are reduced by 20.5%,23.5%,and 25%,respectively.By using a lower clock pulse frequency,the proposed DET flip-flops are promising for constructing QCA sequential circuits and systems with high performance.     

多值触发器及其在时序电路设计中的应用

本文对于多值逻辑代数系统中的基本运算和实现这些基本运算的门电路，作了必要的阐述。作者将ＤＹＬ集成线性“与或“门，用来设定多值逻辑电平的基础上，提出了多值Ｄ、Ｔ、ＪＫ等触发器电路，并将这类多值触发器，作为多值逻辑器件，用于时序电路设计。     

基于虚拟可重构平台的时序电路演化设计

目前,电路进化设计是演化硬件研究的主要方向之一。而时序电路由于存在反馈环不便于进行电路描述和软件仿真。文中对时序电路的演化设计方法进行了改进,提出了专门针对时序电路演化的虚拟可重构平台,建立起电路编码与HDL代码的映射关系。应用TEXTIO和MATLAB来辅助仿真测试过程,使测试向量数量巨大、难以处理的问题得到很好地解决。最后调用ModelSim完成了FSM的演化实验。实验结果验证了基于此平台演化时序电路的可行性和有效性。     

基于改进型ECRL电路的触发器设计

分析了ECRL(Efficient Charge Recovery Logic)电路能量回收中存在的缺陷,提出了该电路的改进方法,用有限的绝热损失实现了非绝热能量的完全回收,并用Hspice对其进行了验证.同时提出了一种基于改进型ECRL电路的触发器设计方法.通过采用0.5μm BSIM3v3模型工艺的Hspice仿真,表明在降低功耗方面与现有触发器电路相比有一定程度的改善.     

Demand-driven logic simulation using a network of loosely coupled processors

Logic simulation is used extensively in the design of digital systems for the purpose of studying the behaviour of circuits under various conditions and for verifying the required performance of circuits. There is considerable interest in methods which reduce the simulation time during the design process. In this paper, we investigate how this can be achieved by simulating the action of logic circuits using a network of loosely coupled processors. Circuits modelled as directed graphs comprising clocked sequential components and (unclocked) arbitrary combinational logic gates can be partitioned into separate tasks each consisting of a sequential component with an associated network of combinational components. We present cost functions for evaluating a task subject to probabilistic assumptions about the functioning of the circuits. The circuit evaluation method used in the simulation process is significant. We apply lazy evaluation, a demand-driven evaluation strategy in which signals in the circuit are evaluated on a ‘need to do' basis, resulting in a considerable saving in circuit simulation time. We achieve distributed logic simulation using a network of workstations and show from experimental results that by using such a configuration, we essentially obtain a single computation engine which can be used to obtain speedups in circuit simulation when compared with uniprocessor simulation systems. Interprocess communications between tasks on different workstations proceed via remote procedure calls while local communications between tasks take place via shared memory. The method of partitioning used in the circuit model ensures that communications between tasks take place only at defined times in the simulation sequence.     

A three-step decomposition method for the evolutionary design of sequential logic circuits

Evolvable hardware (EHW) refers to an automatic circuit design approach, which employs evolutionary algorithms (EAs) to generate the configurations of the programmable devices. The scalability is one of the main obstacles preventing EHW from being applied to real-world applications. Several techniques have been proposed to overcome the scalability problem. One of them is to decompose the whole circuit into several small evolvable sub-circuits. However, current techniques for scalability are mainly used to evolve combinational logic circuits. In this paper, in order to decompose a sequential logic circuit, the state decomposition, output decomposition and input decomposition are united as a three-step decomposition method (3SD). A novel extrinsic EHW system, namely 3SD–ES, which combines the 3SD method with the (μ, λ) ES (evolution strategy), is proposed, and is used for the evolutionary designing of larger sequential logic circuits. The proposed extrinsic EHW system is tested extensively on sequential logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library. The results demonstrate that 3SD–ES has much better performance in terms of scalability. It enables the evolutionary designing of larger sequential circuits than have ever been evolved before.     

Automated BIST for sequential logic synthesis

An automated built-in self-test (BIST) technique for general sequential logic is described that can be used directly at all levels of testing from device testing through system diagnostics. The technique selectively replaces existing system memory elements with BIST flip-flop cells, which it then connects to form a circular chain. Data are compacted and test patterns are generated simultaneously. The approach has been incorporated in a system for behavioral model synthesis to implement BIST in VLSI devices based on standard cells and in circuit packs based on PLDs, automatically. Seven production VLSI devices have been implemented with this automated BIST approach. Area overhead was between 6% and 19% for a fault coverage of 90%+ with the BIST capability alone     

一种用于实现任意基数值时序逻辑的阈值存储电路

本文基于多值时序电路的次态方程和输出方程最小项展开式,提出了一种具有任意值输入、双轨二值输出的阈值存储电路设计方案,它和多值与或门配合,运用Disjoint代数能够设计出任意基数值时序电路.文中通过三值九进制计数器的设计,阐明了任意基数值时序电路的设计方法.     

基于连续逻辑的多值同步时序电路模块设计

本文对多值时序逻辑电路提出了一种新的设计思想:以连续逻辑中不同的逻辑电平来表示时序机状态集中的不同状态及其他参数集中的不同元素;以电容及其旁路MOS管代替触发器实现信号的暂存和抹除.由于取消了传统的以一个二进制码代表一种状态的方法,使设计过程大大简化,可以使用多值时序电路的通用模块.实现不同的时序函数只需改变模块中某几个接点,所以设计、制造和使用都很方便.