A novel dual p-/p+ poly gate CMOS VLSItechnology

A CMOS VLSI technology using p^- and p⁺ poly gates for NMOS and PMOS devices is presented. Due to the midgap work function of the p^- poly gate, the NMOS native threshold voltage is 0.7 V and, therefore, no additional threshold adjust implantation is required. The NMOS transistor is a surface-channel device with improved field-effect mobility and lower body effect due to the reduction in the channel doping concentration. In addition, the p ^- poly gate is shown to be compatible with p⁺ poly-gated surface-channel PMOS devices     

Oxynitride gate dielectrics for p+-polysilicon gate MOSdevices

Different oxynitride gate dielectrics (NH₃-nitrided, reoxidized NH₃-nitrided, N₂-annealed NH₃-nitrided, and N₂O grown oxides) are investigated for use in p⁺-polysilicon gate MOS devices. The comparison is based on flatband voltage shift as well as decrease in inversion capacitance. Results show that NH₃-nitrided and N ₂-annealed NH₃-nitrided oxides best suppress the boron penetration and, consequently, these two undesirable effects. These findings are explained on the basis of the distribution of nitrogen in various oxynitride dielectrics     

Device design for the submicrometer p-channel FET with n+polysilicon gate

CMOS has become one of the most important technologies for VLSI applications. If the conventional n⁺polysilicon gate approach is to be maintained for VLSI CMOS, the p-channel transistor will cause problems in scaling down to submicrometers due to the counter-doping that is necessary to adjust the threshold voltage to a reasonable value. The depth of the p⁺source-drain junctions will also cause short-channel effects. This paper presents in-depth analysis of the submicrometer p-channel transistor structure. The effects of the counter-doping junction depth and the source-drain junction depth on the device subthreshold characteristics are discussed. Criteria for the submicrometer p-channel transistor structure with good subthreshold characteristics are presented. A new technique for minimizing the counter-doping junction depth is also presented. Submicrometer p-channel transistors with n⁺polysilicon gate were fabricated using this new technique as well as techniques for forming very shallow p⁺-junctions. Devices with submicrometer channel lengths showed very good subthreshold characteristics, as predicted by simulations.     

Oxide thickness effect on boron diffusion in thin oxide p+ Si gate technology

Based on a network defect model for the diffusion of B in SiO₂ we propose that B diffuses via a peroxy linkage defect whose concentration in the oxide changes under different processing conditions. We show that as the gate oxide is scaled below 80 Å in thickness, additional chemical processes act to increase B diffusivity and decrease its activation energy, both as a function of the distance from the Si/SiO₂ interface. For a 15 Å oxide, the B diffusivity at 900°C would increase by a factor of 24 relative to diffusion in a 100 Å oxide     

Thin-film SOI CMOS transistors with p+-polysilicon gates

A comparison is given of the use of p⁺-polysilicon and n⁺-polysilicon as the gate material for high-performance CMOS processes in fully depleted, thin SOI (silicon on insulator) films. Experimental devices on Simox substrates are compared with numerical simulations. It is found that n-channel transistors with p-poly gates require lower channel doping levels than their n-poly counterparts, leading to higher gains and easier control of the threshold voltage. The lower electric fields in the p-poly transistor also result in improved drain breakdown characteristics. Control of the subthreshold and punch-through characteristics of the p-poly device requires the use of very thin films when there is significant fixed positive charge at the interface with the buried oxide     

A physical model for boron penetration through thin gate oxidesfrom p+ polysilicon gates

Based on numerical device and process simulation, it is shown that enhancement of the boron diffusivity by as much as 300 times in the thin gate oxide results in a very shallow exponential p-type profile in the underlying silicon substrate. The effect of fluorine and phosphorus coimplantation into the p-type polysilicon gate is modeled by changes in the boron diffusivity in the gate oxide and segregation at the polysilicon-oxide interface. An inverse PMOS short-channel behavior in which the threshold voltage becomes more negative with decreasing channel length is modeled by two-dimensional boron segregation effects caused by the poly gate oxidation     

Double-drift-region (p+pnn+) avalanche diode oscillators

The advantages of a double-drift-region avalanche diode oscillator are discussed. Conventional structures (p⁺nn⁺or n⁺pp⁺) are essentially single-drift-region devices in that transit-time delay (for IMPATT mode) and zone transit (for TRAPATT mode) occur in a single region of one impurity type. The proposed structure (p⁺pnn⁺) has two drift regions and is essentially two complementary avalanche diode oscillators in series.     

The Hooge parameters of n+-p-n and p+-n-p silicon bipolar transistors

We establish here again the fact that the Hooge parameters of NEC57807 n⁺-p-n and in GE82 p⁺-n-p silicon bipolar transistors are orders of magnitude smaller than the value 2 × 10^-3postulated earlier. In the NEC57807 devices neither the base 1/fnoise nor the collector 1/fnoise is of the diffusion-fluctuation type. In the GE82 devices the collector 1/fnoise is not of the diffusion-fluctuation type, but the base 1/fnoise is of that type. We have given, also, a theory of the effects of surface recombination fluctuations in the emitter-base space-charge region on the base noise and the collector noise and find a noise spectrum that varies asI_gammawhere 0.5 < γ < 1.6 when going from small to large currents.     

Avalanche multiplication noise characteristics in thin GaAs p+-i-n+ diodes

Avalanche noise measurements have been performed on a range of homojunction GaAs p⁺-i-n⁺ and n⁺-i-p ⁺ diodes with “i” region widths, ω from 2.61 to 0.05 μm. The results show that for ω⩽1 μm the dependence of excess noise factor F on multiplication does not follow the well-established continuous noise theory of McIntyre [1966]. Instead, a decreasing noise factor is observed as ω decreases for a constant multiplication. This reduction in F occurs for both electron and hole initiated multiplication in the thinner ω structures even though the ionization coefficient ratio is close to unity. The dead-space, the minimum distance a carrier must travel to gain the ionization threshold energy, becomes increasingly important in these thinner structures and largely accounts for the reduction in noise     

Analysis of the p+/p window layer of thin film solar cells by simulation

The application of a p⁺/p configuration in the window layer of hydrogenated amorphous silicon thin film solar cells is simulated and analyzed utilizing an AMPS-1D program. The differences between p⁺-p-i-n configuration solar cells and p-i-n configuration solar cells are pointed out. The effects of dopant concentration, thickness of p⁺-layer, contact barrier height and defect density on solar cells are analyzed. Our results indicate that solar cells with a p⁺-p-i-n configuration have a better performance. The open circuit voltage and short circuit current were improved by increasing the dopant concentration of the p⁺ layer and lowering the front contact barrier height. The defect density at the p/i interface which exceeds two orders of magnitude in the intrinsic layer will deteriorate the cell property.     

Modeling of submicrometer gate GaAs field effect transistors

Before describing the mainFet modelings today available, the main technological evolutions ofMesfet andTegfet are summarized. It is brought some information on the various physical effects that occur in the devices and that must be taken into account in the models. It is shown that the different kinds of modelings (Monte Carlo, two dimensional, one dimensional) constitute a continuous chain, where the different elements appear strictly complementary. Finally, the present situation concerning modeling ofMesfet andTegfet will be presented.     

Modeling boron diffusion in thin-oxide p+ Si gatetechnology

A network defect model suitable for use in process simulation is presented for the diffusion of B in SiO₂ and, in particular, B in the presence of F and H₂. We find that B diffuses via a peroxy linkage defect the concentration in the oxide of which changes under different processing conditions. From random walk theory it is possible then to calculate the resulting diffusion coefficients. These results are compared with measured diffusivities and empirical adjustments are made     

Bias temperature instability in scaled p+ polysilicongate p-MOSFET's

The bias temperature instability in surface-channel p⁺ polysilicon gate p-MOSFETs was evaluated. It was found that a large negative threshold voltage shift (ΔV_th,BT) is induced by negative bias temperature (BT) stress in short-channel p⁺ polysilicon gate p-MOSFETs. This Vth shift, which depends on the gate length of p-MOSFETs, is a new degradation mode. In this degradation, the negative ΔV_th,BT increases significantly with a reduction in the gate length. It was shown that this is because of the local degradation of the gate oxide near the gate edge. This degradation is caused by the electrochemical reaction between holes and oxide defects and it is enhanced by boron penetration through the gate oxide from p⁺-gate. For the bias temperature instability in p⁺ -gate p-MOSFETs, sufficient care should be taken in scaled dual-gate CMOS devices     

Anomalous reverse short-channel effect in p+ polysilicongated P-channel MOSFET

The boron-penetration-dependent Reverse Short Channel Effect (RSCE) on the threshold voltage is observed for short channel p⁺ poly-gate PMOSFET's. The RSCE is found to be more significant as the boron penetration becomes more severe. The RSCE is significant in BF ₂ doped poly-gated MOS devices and is alleviated in buffered poly-gated MOS devices. Fluorine enhanced boron diffusion in the gate oxide during high temperature process is believed to account for the RSCE, which is also confirmed by using a two-dimensional process simulator     

Modeling boron diffusion in ultrathin nitrided oxide p+Si gate technology

Based on a network defect model for the diffusion of B in SiO₂, we propose that B diffuses via a peroxy linkage defect (pld) whose concentration in the oxide changes under different processing conditions. We show that as N is added to the gate oxide (nitridation), N atoms compete with B atoms for activation through the diffusion-defect sites. The model predicts that nitridation is ineffective in stopping B penetration when BF₂ implants dope the polysilicon gate, as well as for the case of very thin gate dielectrics with B-implanted gates     

MBE grown n+-i-δ(p+)-i-n+GaAs V-groove barrier transistor

The three-terminal n⁺-i-δ(p⁺)-i-n⁺V-groove barrier transistor (VBT) has been successfully fabricated by molecular beam epitaxy (MBE). The base terminal is connected to the δ(p⁺), the thin p⁺layer, by depositing aluminum on the etched V-groove. The demonstrated device possesses high potential of ultra-high-frequency (f_{r} > 30-GHz), high-power, and low-noise capability due to carriers transporting by thermionic emission and being controlled by the base-emitter bias.     

Experimental determination of electron drift velocity in 4H-SiC p+-n-n+ avalanche diodes

4H-SiC p⁺-n-n⁺ diodes of low series resistivity (<1×10^-4 Ω·cm²) were fabricated and packaged. The diodes exhibited homogeneous avalanche breakdown at voltages U_b=250-270 V according to the doping level of the n layer. The temperature coefficient of the breakdown voltage was measured to be 2.6×10^-4 k^-1 in the temperature range 300 to 573 K. These diodes were capable of dissipating a pulsed power density of 3.7 MW/cm² under avalanche current conditions. The transient thermal resistance of the diode was measured to be 0.6 K/W for a 100-ns pulse width, An experimental determination of the electron saturated drift velocity along the c-axis in 4H-SIC was performed for the first time, It was estimated to be 0.8×10⁷ cm/s at room temperature and 0.75×10⁷ cm/s at approximately 360 K     

The effects of boron penetration on p+ polysilicon gatedPMOS devices

The penetration of boron into and through the gate oxides of PMOS devices which employ p⁺ doped polysilicon gates is studied. Boron penetration results in large positive shifts in V_FB , increased PMOS subthreshold slope and electron trapping rate, and decreased low-field mobility and interface trap density. Fluorine-related effects caused by BF₂ implantations into the polysilicon gate are shown to result in PMOS threshold voltage instabilities. Inclusion of a phosphorus co-implant or TiSi₂ salicide prior to gate implantation is shown to minimize this effect. The boron penetration phenomenon is modeled by a very shallow, fully-depleted p-type layer in the silicon substrate close to the SiO ₂/Si interface     

A comprehensive study on p+ polysilicon-gate MOSFET'sinstability with fluorine incorporation

It is reported that fluorine can jeopardize p⁺-gate devices under moderate annealing temperatures. MOSFETs with BF₂ or boron-implanted polysilicon gates were processed identically except at gate implantation. Evidence of boron penetration through 12.5-nm oxide and a large quantity of negative charge penetration (10 ¹² cm^-2) by fluorine even at moderate annealing conditions is reported. The degree of degradation is aggravated as fluorine dose increases. A detailed examination of the I-V characteristics of PMOSFET with fluorine incorporated p⁺-gate revealed that the long gate-length device had abnormal abrupt turn-on I_d-V_g characteristics, while the submicrometer-gate-length devices appeared to be normal. The abnormal turn-on I_d-V_g characteristics associated with long-gate-length p⁺-gate devices vanished when the device was subjected to X-ray irradiation and/or to a high-voltage DC stressing at the source/drain. The C-V characteristics of MOS structures of various gate dopants, processing ambients, doping concentrations, and annealing conditions were studied. Based on all experimental results, the degradation model of p⁺-gate devices is presented. The incorporation of fluorine in the p⁺ gate enhances boron penetration through the thin gate oxide into the silicon substrate and creates negative-charge interface states. The addition of H/OH species into F-rich gate oxide will further aggravate the extent of F-enhanced boron penetration by annealing out the negative-charge interface states     

Effective crosstalk isolation through p+ Si substrateswith semi-insulating porous Si

Through-the-wafer porous Si (PS) trenches have been used to provide radio frequency (RF) isolation in Si because of their semi-insulating property. Reduction of crosstalk by 70 dB at 2 GHz and 45 dB at 8 GRz is demonstrated between Al pads with 800 μm separation on p⁺Si. Crosstalk suppression increases linearly with increasing PS width to beyond 320 μm. This suppression is degraded by one order of magnitude when the Si underneath the PS trenches remains and serves as a residual path for crosstalk. These results show that PS is an excellent candidate for RF isolation in modern VLSI technology