640-Gb/s high-speed ATM switching system based on 0.25-μm CMOS,MCM-C, and optical WDM interconnection

A 640-Gb/s high-speed ATM switching system that is based on the technologies of advanced MCM-C, 0.25-μm CMOS, and optical wavelength-division-multiplexing (WDM) interconnection is fabricated for future broadband backbone networks. A 40-layer, 160×114 mm ceramic MCM forms the basic ATM switch module with 80-Gb/s throughput. It consists of 8 advanced 0.25-μm CMOS LSIs and 32 I/O bipolar LSIs. The MCM has a 7-layer high-speed signal line structure having 50-Ω strip lines, high-speed signal lines, and 33 power supply layers formed using 50-μm thick ceramic layers to achieve high capacity. A uniquely structured closed-loop-type liquid cooling system for the MCM is used to cope with its high power dissipation of 230 W. A three-stage ATM switch is made using the optical WDM interconnection between high-performance MCMs. For WDM interconnection, newly developed compact 10-Gb/s, 8-WDM optical transmitter and receiver modules are used. These modules are each only 80×120×20 mm and dissipate 9.65 W and 22.5 W, respectively. They have a special chassis for cooling, which contains high-performance heat-conductive plates and micro-fans. An optical WDM router based on an arrayed waveguide router is used for mesh interconnection of boards. The optical WDM interconnect has 640-Gb/s throughput and simple interconnection     

A CMOS Batcher and Banyan chip set for B-ISDN packet switching

A Batcher and Banyan chip set suitable for broadband packet switch applications is described. Each chip concurrently processes 32 bit-serial packet channels and is a building block for larger networks. Current chip samples have been tested at channel rates of 170 Mb/s in 1.2-μm double-metal single-poly CMOS for both the Batcher and Banyan chips. Each chip requires a 5-V supply, dissipates approximately 1.5 W, provides 5.44 Gb/s of switching capacity, can process 12.8 million asynchronous transfer mode (ATM) cells per second, and is packaged in an 84-pin leadless ceramic chip carrier (LCCC) for convenient testing. The design and implementation of the switching elements capable of supporting the high-speed bit-serial channels and the chip architectures that accommodate them are described in detail     

CMOS gigabit-per-second switching

An analysis and experimental results for a 600-Mb/s 1.2-μm CMOS space switch chip are provided. The high bit rate is achieved with a tree architecture, which is relatively insensitive to on-chip stray capacitance. Computer simulations indicate that bit rates in excess of 1 Gb/s are achievable with 1-μm CMOS and circuit/layout optimization. An obstacle to achieving high bit rate is crosstalk, which is primarily caused by chip packaging and not by the chip itself. Even the best discrete packaging technologies result in excessive crosstalk when 32 outputs switch simultaneously at 600 Mb/s. Tolerable crosstalk was achieved by limiting outputs to two per power supply pin. A major increase in bit rate can be obtained by switching bytes (8 b parallel) of information. This requires on-chip information storage and reclocking to maintain synchronization between the eight parallel bits. Experiments with a second-generation synchronous switch chip have demonstrated switching at 311 MB/s, which corresponds to an STS-48 rate of 2.488 Gb/s     

High-performance 0.10-μm CMOS devices operating at roomtemperature

The authors have fabricated 0.10-μm gate-length CMOS devices that operate with high speed at room temperature. Electron-beam lithography was used to define 0.10-μm polysilicon gate patterns. Surface-channel type p- and n-channel MOSFETs were fabricated using an LDD structure combined with a self-aligned TiSi₂ process. Channel doping was optimized so as to suppress punchthrough as well as to realize high transconductance and low drain junction capacitance. The fabricated 0.10-μm CMOS devices have exhibited high transconductance as well as a well-suppressed band-to-band tunneling current, although the short-channel effect occurred somewhat. The operation of a 0.10-μm gate-length CMOS ring oscillator has been demonstrated. The operation speed was 27.7 ps/gate for 2.5 V at room temperature, which is the fastest CMOS switching ever reported     

A 250-Mb/s, 700-mW, 32-highway×8-b S/P converter LSI withcross-access memory

A multihighway serial/parallel (S/P) converted LSI chip suitable for the broadband Integrated Services Digital Network (B-ISDN) node interface is presented. The chip, fabricated with 0.8-μm BiCMOS technology, handles 32-highway×8 b of S/P, P/S conversion at up to 250 Mb/s and has a power dissipation of 700 mW. The chip features cross-access memory and a current-cut-type CMOS/ECL interface circuit. Each of these features is described and evaluated. A newly developed BiNMOS-type D-flip-flop (D-FF) is used to speed up the cross-access memory and is compared to a CMOS D-FF     

Technology Aspects for System 12 Broadband ISDN

Although the enhancement of System 12, SEL's digital switching system, for ISDN services is virtually complete, further development work is being carried out to allow broadband switching for videophone services, videoconferencing, and the distribution of radio and television programs. This paper describes an appropriate approach to the evolution Of System 12 toward the broadband ISDN (B-ISDN), emphasizing the crosspoint and technology aspects of the broadband switch. Test results on a broadband switch VLSI circuit for 140 Mbit/s in a 2μm CMOS technology are presented.     

A 50-Mbit/s CMOS monolithic optical receiver

A general-purpose CMOS optical receiver that operates at data rates from 1 to 50 Mb/s has been fabricated in a 1.75-μm CMOS process. The technology choice resulted in a high level of integration compared with similar bipolar technology receivers. The measured minimum signal current for a 10^-9 bit error rate at 50 Mb/s is 48-nA r.m.s. Automatic gain control gives the receiver an electrical input dynamic range of greater than 60 dB. The outputs are TTL (transistor-transistor logic)-compatible and the chip dissipates less than 500 mW when switching at maximum speed. The die area is 16 mm² . A comprehensive noise analysis of the receiver front end provides insight into the design tradeoffs of optical receiver preamplifiers. A wideband precision amplifier used in the linear channel is discussed in detail. A simple method for recovering low-frequency signal information lost in AC coupling is described     

A 3.3-V, 10-b, 25-MSample/s two-step ADC in 0.35-μm CMOS

This paper describes the design of a two-step analog-to-digital converter (ADC). By using techniques such as improved switching and offset compensated amplifiers, the high-speed two-step architecture can be expanded toward high resolution. The ADC presented here achieves 9 ENOB with a spurious-free dynamic range of more than 72 dB, at a sample rate of 25 MSample/s. The ADC is realized in a 0.35-μm mainstream CMOS process without options such as double poly. It measures 0.66 mm ² and dissipates 195 mW from a 3.3-V power supply     

Time resolution of NMOS sampling switches used on low-swing signals

A number of recently reported CMOS line receivers and downconversion mixers are based on sampling. A key component in these designs is the NMOS sampling switch. It can sample a very high bandwidth signal, several GHz for a 0.8-μm transistor. We present an expression for the aperture time for an NMOS switch when the input has low swing. The switch can, under this condition, be modeled as a device that determines a weighted average over time of the input signal. The weight function is derived. The aperture time function shows that the maximum theoretical time resolution for a switch in 0.8-μm standard CMOS is 21 ps (~48 Gb/s). SPICE simulations agree with the theory. Transient two-dimensional (2-D) device simulations do not contradict the predicted results. Experiments on a switch made in a 0.8-μm standard CMOS process show successful sampling of every thirty second bit of a 5-Gb/s data stream     

A 250-Mb/s 32×32 CMOS crosspoint LSI for ATM switchingsystems

A 32×32 crosspoint LSI and a time-slot controlled asynchronous-transfer-mode (ATM) switch architecture utilizing the LSI are presented. The ATM switch, which is classified as an input-buffer-type ATM switch, enables 99% throughput and broadcasting capability. The crosspoint LSI is characterized by the bit-map oriented and pipelined connection control method which can switch and broadcast 160-Mb/s ATM cells, 32×32 switch cells which have less parasitic capacitance, and emitter-coupled-logic (ECL) compatible interfaces which are compatible with a 160-MHz broadband ISDN data rate. The LSI has been fabricated by a 1-μm CMOS process. The chip size is 7.4 mm×7.4 mm. According to the evaluation, operation at 250 Mb/s is confirmed. 1.2-W power consumption is observed at 160-Mb/s operating condition     

Cutoff frequency and propagation delay time of 1.5-nm gate oxideCMOS

The high-frequency AC characteristics of 1.5-nm direct-tunneling gate SiO₂ CMOS are described. Very high cutoff frequencies of 170 GHz and 235 GHz were obtained for 0.08-μm and 0.06-μm gate length nMOSFETs at room temperature. Cutoff frequency of 65 GHz was obtained for 0.15-μm gate length pMOSFETs using 1.5-nm gate SiO₂ for the first time. The normal oscillations of the 1.5-nm gate SiO₂ CMOS ring oscillators were also confirmed. In addition, this paper investigates the cutoff frequency and propagation delay time in recent small-geometry CMOS and discusses the effect of gate oxide thinning. The importance of reducing the gate oxide thickness in the direct-tunneling regime is discussed for sub-0.1-μm gate length CMOS in terms of high-frequency, high-speed operation     

A 12-ns ECL I/O 256 K×1-bit SRAM using a 1-μm BiCMOStechnology

An ECL (emitter-coupled-logic) I/O 256K×1-bit SRAM (static random-access memory) has been developed using a 1-μm BiCMOS technology. The double-level-poly, double-level-metal process produces 0.8-μm CMOS effective gate lengths and polysilicon emitter bipolar transistors. A zero-DC-power ECL-to-CMOS translation scheme has been implemented to interface the ECL periphery circuits to the CMOS decode and NMOS matrix. Low-impedance bit-line loads were used to minimize read access time. Minimization of bit-line recovery time after a write cycle is achieved through the use of a bipolar/CMOS write recovery method. Full-die simulations were performed using HSPICE on a CRAY-1     

An 18-Mb, 12.3-GB/s CMOS pipeline-burst cache SRAM with 1.54Gb/s/pin

An 18-Mbit CMOS pipeline-burst cache SRAM achieves a 12.3-Gbyte/s data transfer rate with 1.54-Gbit/s/pin I/O's. The SRAM is fabricated on a 0.18-μm CMOS technology. The 14.3×14.6-mm² SRAM chip uses a 5.59-μm², six-transistor cell. Circuit techniques used for achieving high bandwidth include fully self-timed array architecture, segmented hierarchical sensing with separated global read/write bitlines in different metal layers, a high-speed data-capture technique, a reduced-swing output buffer, and a high-sensitivity, high-bandwidth input buffer     

A multimode PCM transceiver chip for 1.544-Mbit/s digitaltelecommunications

A 1.25-μm CMOS VLSI device that converts the popular 1.544-Mb/s T1 format used in digital telecommunications to a 4.096-Mb/s system format is described. The transmit and receive functions are implemented with a RAM, a 3088-bit shift register, and 33 K transistors     

U-grooved SIT CMOS technology with 3 fJ and 49 ps (7 mW, 350 fJ)operation

Static induction transistor (SIT) CMOS is analyzed by a circuit simulation method. According to the results, the propagation delay time of the SIT CMOS could be represented as the ratio of the load capacitance to the transconductance. The U-grooved structure plays an important role in the fabrication of MOS SIT with large transconductance and small parasitic capacitance. U-grooved SIT CMOS has been fabricated by anisotropic plasma etching, and its switching speed has been evaluated by a 31-stage ring oscillator. A minimum ρ-τ product of 3 fJ/gate has been obtained for a design rule of 1-μm channel length. A minimum propagation delay time of 49 ps/gate has also been obtained at a dissipation power of 7 mW/gate, which corresponds to a ρ-τ product of 350 fJ/gate     

A 10-Gb/s (1.25 Gb/s×8)4×2 0.25-μm CMOS/SIMOX ATMswitch based on scalable distributed arbitration

This paper presents the design and implementation of a scalable asynchronous transfer mode switch. We fabricated a 10-Gb/s 4×2 switch large-scale integration (LSI) that uses a new distributed contention control technique that allows the switch LSI to be expanded. The developed contention control is executed in a distributed manner at each switch LSI, and the contention control time does not depend on the number of connected switch LSI's. To increase the LSI throughput and reduce the power consumption, we used 0.25-μm CMOS/SIMOX (separation by implanted oxygen) technology, which enables us to make 221 pseudo-emitter-coupled-logic I/O pins with 1.25-Gb/s throughput. In addition, power consumption of 7 W is achieved by operating the CMOS/SIMOX gates at -2.0 V. This consumption is 36% less than that of bulk CMOS gates (11 W) at the same speed at -2.5 V. Using these switch LSI's, an 8×8 switching multichip module with 80-Gb/s throughput was fabricated with a compact size     

A fully integrated CMOS receiver front-end for optic GigabitEthernet

A fully integrated fiber-optic receiver chip in a CMOS technology is presented. The design was done in a low-cost mixed-signal analog pure CMOS technology with 0.35-μm gate length. It incorporates every building block needed for standard fiber-optic receiver application, e.g., transimpedance amplifier, postamplifier, signal detect, and several control circuits. The chip works without any external components, such as capacitors usually needed to ensure the broadband operation down to several tens of kilohertz. Three designs were processed for typical data applications between 155 Mb/s and 1.25 Gb/s. The difference in the designs can be created by changing only one metal mask and programming some bandwidth and noise-relevant components on the chip. The results in sensitivity, dynamic range, and other behaviors are fully compliant with the relevant standards, such as SONET or IEEE 802.3 (Gigabit Ethernet) and future IEEE 1394 plastic optical fiber (POF) communication     

Low-power bandgap references featuring DTMOSTs

This paper describes two CMOS bandgap reference circuits featuring dynamic-threshold MOS transistors. The first bandgap reference circuit aims at application in low-voltage, low-power ICs that tolerate medium accuracy. The circuit runs at supply voltages down to 0.85 V while consuming only 1 μW; the die area is 0.063 mm² in a standard digital 0.35-μm CMOS process. The second bandgap reference circuit aims at high accuracy operation (σ=0.3%) without trimming. It consumes approximately 5 μW from a 1.8-V supply voltage and occupies 0.06 mm² in a standard 0.35-μm CMOS process     

Design techniques for low-voltage high-speed digital bipolarcircuits

This paper describes design techniques for multigigahertz digital bipolar circuits with supply voltages as low as 1.5 V. Examples include a 2/1 multiplexer operating at 1 Gb/s with 1.2 mW power dissipation, a D-latch achieving a maximum speed of 2.2 GHz while dissipating 1.4 mW, two exclusive-OR gates with a delay less than 200 ps and power dissipation of 1.3 mW, and a buffer/level shifter having a delay of 165 ps while dissipating 1.4 mW. The prototypes have been fabricated in a 1.5-μm 12-GHz bipolar technology. Simulations on benchmarks such as frequency dividers and line drivers indicate that, for a 1.5-V supply, the proposed circuits achieve higher speed than their CMOS counterparts designed in a 0.5-μm CMOS process with zero threshold voltage     

A balanced 0.9-μm CMOS transconductance-C filtertunable over the VHF range

A balanced transconductance-C biquad implemented in the digital subset of a 0.9-μm CMOS process operates at frequencies up to 450 MHz and Q factors from a nominal value near 1 to approximately 100 with 30-40-dB dynamic range. By switching in capacitors and adjusting control voltages it can be tuned to below 30 MHz, demonstrating the capability of operating over the entire VHF range. Active area is 0.029 mm² and power consumption is 8-12 mW with a 5-V power supply