A grinding-based manufacturing method for silicon wafers: generation mechanisms of central dimples on ground wafers

Silicon wafers are the fundamental building blocks for most integrated circuits. The lapping-based manufacturing method currently used to manufacture the majority of silicon wafers will not be able to meet the ever-increasing demand for flatter wafers and lower prices. A grinding-based manufacturing method has been investigated experimentally to demonstrate its potential to manufacture flat silicon wafers at a lower cost. It has been demonstrated that the site flatness on the ground wafers (except for a few sites at the wafer center) could meet the stringent specifications for future silicon wafers. This paper, as a follow up, addresses one of the reasons for the poor flatness at the wafer center: central dimples on ground wafers. A finite element model is developed to illustrate the generation mechanisms of central dimples. Then, effects of influencing factors (including Young's modulus and Poisson's ratio of the grinding wheel segment, dimensions of the wheel segment, grinding force, and chuck shape) on the central dimple sizes are studied. Pilot experimental results will be presented to substantiate the predicted results from the finite element model. This provides practical guidance to eliminate or reduce central dimples on ground wafers.     

Fine grinding of silicon wafers: designed experiments

Silicon wafers are the most widely used substrates for semiconductors. The falling price of silicon wafers has created tremendous pressure to develop cost-effective processes to manufacture silicon wafers. Fine grinding possesses great potential to reduce the overall cost for manufacturing silicon wafers. The uniqueness and the special requirements of fine grinding have been discussed in a paper published earlier in this journal. As a follow-up, this paper presents the results of a designed experimental investigation into fine grinding of silicon wafers. In this investigation, a three-variable two-level full factorial design is employed to reveal the main effects as well as the interaction effects of three process parameters (wheel rotational speed, chuck rotational speed and feed-rate). The process outputs studied include grinding force, spindle motor current, cycle time, surface roughness and grinding marks.     

Fine grinding of silicon wafers: a mathematical model for the wafer shape

Over 90% of semiconductors are built on silicon wafers. The fine grinding process has great potential to produce very flat wafers at a low cost. Four papers on fine grinding have been previously published by the authors. The first paper discussed its uniqueness and special requirements. The second one presented the results of a designed experimental investigation. The third and fourth papers presented mathematical models for the chuck shape and the grinding marks, respectively. As a follow up, this paper develops a mathematical model for the wafer shape. After the model is described, its practical applications in wafer manufacturing are discussed.     

Finite element analysis for grinding of wire-sawn silicon wafers: a designed experiment

Silicon is the primary semiconductor material used to fabricate microchips. The quality of microchips depends directly on the quality of starting silicon wafers. A series of processes are required to manufacture high quality silicon wafers. Surface grinding is one of the processes used to flatten the wire-sawn wafers. A major issue in grinding of wire-sawn wafers is the reduction and elimination of wire-sawing induced waviness. This paper presents the results of a finite element analysis for grinding of wire-sawn silicon wafers. In this investigation, a four-factor two-level full factorial design is employed to reveal the main effects as well as the interaction effects of four factors (wafer thickness, waviness wavelength, waviness height and grinding force) on effectiveness of waviness reduction. The implications of this study to manufacturing are also discussed.     

ELID grinding of silicon wafers: A literature review

Silicon wafers are the most widely used substrates for fabricating integrated circuits. There have been continuous demands for higher quality silicon wafers with lower prices, and it becomes more and more difficult to meet these demands using current manufacturing processes. In recent years, research has been done on electrolytic in-process dressing (ELID) grinding of silicon wafers to explore its potential to become a viable manufacturing process. This paper reviews the literature on ELID grinding, covering its set-ups, wheel dressing mechanism, and experimental results. It also discusses the technical barriers that have to be overcome before ELID grinding can be used in manufacturing.     

An experimental investigation into soft-pad grinding of wire-sawn silicon wafers

Silicon is the primary semiconductor material used to fabricate microchips. A series of processes are required to manufacture high-quality silicon wafers. Surface grinding is one of the processes used to flatten wire-sawn wafers. A major issue in grinding of wire-sawn wafers is reduction and elimination of wire-sawing induced waviness. Results of finite element analysis have shown that soft-pad grinding is very effective in reducing the waviness. This paper presents an experimental investigation into soft-pad grinding of wire-sawn silicon wafers. Wire-sawn wafers from a same silicon ingot were used for the study to ensure that these wafers have similar waviness. These wafers were ground using two different soft pads. As a comparison, some wafers were also ground on a rigid chuck. Effectiveness of soft-pad grinding in removing waviness has been clearly demonstrated.     

Fine grinding of silicon wafers: effects of chuck shape on grinding marks

Silicon wafers are used for production of most microchips. Various processes are needed to transfer a silicon ingot into wafers. With continuing shrinkage of feature sizes of microchips, more stringent requirement is imposed on wafer flatness. Fine grinding of silicon wafers is a patented technology to produce super flat wafers at a low cost. Six papers on fine grinding were previously published in this journal. The first paper discussed its uniqueness and special requirements. The second one presented the results of a designed experimental investigation. The third and fourth papers presented the mathematical models for the chuck shape and the grinding marks, respectively. The fifth paper developed a mathematical model for the wafer shape and the sixth paper studied machine configurations for spindle angle adjustments. This paper is a follow up of the above-mentioned work. A mathematical model to predict the depth of grinding marks for any chuck shape will be first developed. With the developed model, effects of the chuck shape (as well as the wheel radius) on the depth of grinding marks will be studied. Finally, results of pilot experiments to verify the model will be discussed.     

Fine grinding of silicon wafers: a mathematical model for the chuck shape

Fine grinding of silicon wafers is a patented technology to manufacture super flat semiconductor wafers cost-effectively. Two papers on fine grinding were previously published in this journal, one discussed its uniqueness and special requirements, and the other presented the results of a designed experimental investigation. As a follow up, this paper presents a study aiming at overcoming one of the technical barriers that have hindered the widespread application of this technology, namely, the difficulty and uncertainty in chuck preparation. Although the chuck shape is critically important in fine grinding, there are no standard procedures for its preparation. Furthermore, the information on the relation between the set-up parameters and the resulting chuck shape is not readily available. In this paper, a mathematical model for the chuck shape is first developed. Then the model is used to predict the relations between the chuck shape and the set-up parameters. Finally, the results of the pilot experiments to verify the model are discussed.     

A study on surface grinding of 300 mm silicon wafers

Most of today's IC chips are made from 200 mm or 150 mm silicon wafers. It is estimated that the transition from 200 mm to 300 mm wafers will bring a die cost saving of 30–40%. To meet their customers' needs, silicon wafer manufacturers are actively searching for cost-effective ways to manufacture 300 mm wafers with high quality. This paper presents the results of a study on surface grinding of 300 mm silicon wafers. In this study, a three-factor two-level full factorial design is employed to reveal the main effects as well as the interaction effects of three process parameters (wheel rotational speed, chuck rotational speed and feedrate). The process outputs studied include spindle motor current, surface roughness, grinding marks and depth of subsurface cracks.     

Grinding wheels for manufacturing of silicon wafers: A literature review

Grinding is an important process for manufacturing of silicon wafers. The demand for silicon wafers with better quality and lower price presents tremendous challenges for the grinding wheels used in the silicon wafer industry. The stringent requirements for these grinding wheels include low damage on ground surfaces, self-dressing ability, consistent performance, long wheel lives, and low prices. This paper presents a literature review on grinding wheels for manufacturing of silicon wafers. It discusses recent development in abrasives, bond materials, porosity formation, and geometry design of the grinding wheels to meet the stringent requirements.     

Fine grinding of silicon wafers

Silicon wafers are used for the production of most microchips. Various processes are needed to transfer a silicon crystal ingot into wafers. As one of such processes, surface grinding of silicon wafers has attracted attention among various investigators and a limited number of articles can be found in the literature. However, no published articles are available regarding fine grinding of silicon wafers. In this paper, the uniqueness and the special requirements of the silicon wafer fine grinding process are introduced first. Then some experimental results on the fine grinding of silicon wafers are presented and discussed. Tests on different grinding wheels demonstrate the importance of choosing the correct wheel and an illustration of the proper selection of process parameters is included. Also discussed are the effects of the nozzle position and the flow rate of the grinding coolant.     

Simultaneous double side grinding of silicon wafers: a literature review

Silicon wafers are the most widely used substrates for fabricating integrated circuits (ICs). The quality of ICs depends directly on the quality of silicon wafers. A series of processes are required to manufacture high quality silicon wafers. Simultaneous double side grinding (SDSG) is one of the processes to flatten the wire-sawn wafers. This paper reviews the literature on SDSG of silicon wafers, covering the history, machine development (including machine configuration, drive and support systems, and control system), and process modeling (including grinding marks and wafer shape). It also discusses some possible topics for future research.     

Waviness removal in grinding of wire-sawn silicon wafers: 3D finite element analysis with designed experiments

Silicon wafers are used to fabricate more than 90% of integrated circuits. Surface grinding has been used to flatten wire-sawn silicon wafers. A major issue in grinding of wire-sawn wafers is that conventional grinding cannot effectively remove the waviness induced by wire-sawing process. Soft-pad grinding is a promising method to effectively remove waviness. This paper presents the results of three-dimensional (3D) finite element analysis of soft-pad grinding of wire-sawn silicon wafers. In this investigation, a four-factor two-level full factorial design is employed to reveal main effects as well as interaction effects of four factors (Young’s modulus, Poisson’s ratio, and thickness of the soft pad, and waviness wavelength of the wafer) on the effectiveness of waviness reduction. Implications of this study to manufacturing are also discussed.     

Experimental and simulation study for ultrathin (∼100 μm) mono crystalline silicon solar cell with 156×156 mm2 area

A reduction in silicon material consumption in the photovoltaic industry is required for cost reduction. Using crystalline silicon wafers of less than 120 microns of thickness is a promising way for cost and material reduction in the solar cell production. The standard thickness of crystalline silicon solar cells is currently around 180 microns. If the wafers are thinner than 100 microns in the silicon solar cells, the amount of silicon will be reduced by almost half, which should result in prominent cost reduction. With this aim, many groups have worked with thin crystalline silicon wafers. However, most of them have studied with small size substrates. In this paper, we present the electrical characteristics for thin single crystalline silicon solar cells of 100 and 115 μm thickness and 156×156 mm² area manufactured through a conventional process. We have achieved 17.2% conversion efficiency with a 115 μm silicon substrate and 16.8% with a 100 μm substrate. This enables the commercialization of the thin crystalline silicon solar cells with high conversion efficiency. We also suggest issues to be solved in thin crystalline silicon solar cell manufacturing.     

Theoretical analysis on the effects of crystal anisotropy on wiresawing process and application to wafer slicing

Most of the crystals sliced using wiresaw are anisotropic to an extent. The effect of crystal anisotropy on the process of slicing using wiresaw is studied and presented in this paper. A method is proposed to determine the direction of approach (DOA) which will give a better surface finish and reduce deviation from the desired surface normal by maintaining symmetry in material removal rates on the two sides of the wire. The effect of cleavage anisotropy on wiresaw slicing is also studied. If the DOA is perpendicular to a cleavage direction, then the longitudinal direction of the wire aligns with the cleavage direction which increases the tendency of wafer breakage, resulting in lower yield of the wafers. This can be easily avoided by choosing an appropriate DOA. Theoretical analysis is carried out using the proposed methods for slicing silicon wafers. Recommendations are made for three most commonly sliced orientations of silicon: (100), (110) and (111). DOA can be any direction for (100) and (110) wafers from the symmetry point of view but preferred DOAs do exist for these wafers from cleavage point of view. For (111) crystal there are exactly six DOAs with symmetry. However, these six DOAs do not lie in the preferred zones suggested by cleavage criterion. It is suggested that in such situations the symmetry criterion should be given precedence over the cleavage criterion during wiresawing process, as the semiconductor industry has strict tolerances in place for surface normal deviation and flatness.     

Origin,modeling and suppression of grinding marks in ultra precision grinding of silicon wafers

A phenomenon commonly encountered in grinding of silicon wafers is the grinding marks, which are difficult to remove by subsequent polishing process, and have been a great obstacle to the manufacture of silicon wafers with higher flatness. In this paper, the grinding marks formation mechanism was clarified, a grinding marks formation model and an angular wavelength model were developed, and a grinding marks suppression method was proposed. A series of grinding experiments were carried out to verify the developed models and investigate the effect of the wafer rotational speed, the wheel rotational speed, the infeed rate, the axial run out of the cup wheel and the spark out time. The results show that: (1) grinding marks are waviness generated on silicon wafers caused by non-uniform material removal circumferentially due to the axial run out of the cup wheel; (2) grinding marks present multiple angular wavelengths characteristics; (3) the angular wavelength of grinding marks is a one-variable function of the rotational speed ratio of the wheel to the wafer; and (4) grinding marks could be suppressed significantly by properly selecting the rotational speed ratio.     

Fine grinding of silicon wafers: a mathematical model for grinding marks

The majority of today’s integrated circuits are constructed on silicon wafers. Fine-grinding process has great potential to improve wafer quality at a low cost. Three papers on fine grinding were previously published in this journal. The first paper discussed its uniqueness and special requirements. The second one presented the results of a designed experimental investigation. The third paper developed a mathematical model for the chuck shape, addressing one of the technical barriers that have hindered the widespread application of this technology: difficulty and uncertainty in chuck preparation. As a follow up, this paper addresses another technical barrier: lack of understanding on grinding marks. A mathematical model to predict the locus of the grinding lines and the distance between two adjacent grinding lines is first developed. With the developed model, the relationships between grinding marks and various process parameters (wheel rotational speed, chuck rotational speed, and wheel diameter) are then discussed. Finally, results of pilot experiments to verify the model are discussed.     

半导体硅片制备技术及产业现状

介绍半导体硅片制备技术及理论，分析目前全球硅片的产业概况、产业历史发展趋势及特点；结合我国目前的实际情况，论述国内大力发展硅片产业面临的机遇、挑战及存在的问题。      

金属铜辅助化学刻蚀对金刚线切割多晶硅的制绒

针对金刚线切割多晶硅制绒后硅片反射率偏高且切割纹难以去除等问题,采用酸性湿法刻蚀预处理再结合低成本的金属铜辅助化学刻蚀成功的实现了金刚线切割多晶硅片表面制绒。研究结果表明,随着酸腐蚀时间的增加,金刚线切割多晶硅片表面切割纹、粗糙度得到有效改善。倒金字塔结构的引入能够有效地降低硅片表面的反射率。当酸洗预处理时间为5 min,金属铜辅助化学刻蚀时间为15 min时,样品表面倒金字塔结构最均匀,且在300~1 100 nm波长范围内,获得最低平均反射率3.32%。同时优越的减反效果和去除切割纹能力,使得制绒后金刚线切割多晶硅片有望实现高效率的太阳能电池。     

Abrasive electrochemical multi-wire slicing of solar silicon ingots into wafers

To meet the growing demands of the global photovoltaic (PV) industry, preparing large scale and ultra-thin solar wafers becomes one of the key issues. This paper presents the preparatory investigations of slicing solar silicon ingot into wafers by an abrasive electrochemical method based on a multi-wire saw system. The anodic passivation on silicon can be controlled by applying an anodic potential during the mechanical slicing process, which improves the surface integrity and material removal rate remarkably. This new hybrid machining method has no influence on subsequent cleaning of wafers and preparing the solar cells, and the average photoelectric transformation efficiency is >17.5%.