Low temperature characterization of silicon CMOS devices

A brief review of the main physical results concerning the low temperature characterization of Si CMOS devices is presented. More specifically, the carrier mobility law, saturation velocity, short channel effects, impact ionization phenomenon, hot carrier effects and parasitic leakage current are discussed.     

Carrier lifetimes in silicon epitaxial layers deposited on oxygen-implanted substrates

Carrier lifetimes in silicon epitaxial layers deposited on high-dose oxygen-implanted wafers have been obtained from measurements of diode storage times. A figure of 1.25 ?S was obtained for diodes in the implanted area, compared with 1.75 ?S for diodes outside the implanted area on the same wafer. This marginal degradation of lifetime indicates that the dielectrically isolated structure should be able to support bipolar and dynamic logic devices.     

Crystalline oxide-based devices on silicon substrates

We have developed a process to grow epitaxial SrTiO₃ (STO) on Si. This STO/Si substrate can then be used as a pseudo substrate for the further deposition of many other oxides that are closely lattice matched to STO. The STO is grown by molecular-beam epitaxy (MBE) with a subsequent oxide layer deposited either by MBE or sol-gel deposition. The pseudo substrate has been used to demonstrate ferroelectric devices and piezoelectric devices. Ferroelectric capacitors using epitaxial BaTiO₃ (BTO) show a memory window of 0.5 V; however, the retention time for these devices is short because of the depolarization field caused by the silicon-oxide interface layer used to improve the band alignment of the BTO/Si interface. Surface acoustic wave (SAW) resonators using epitaxial Pb(Zr,Ti)O₃ show excellent response with a coupling coefficient of 4.6% and a velocity of 2,844 m/s.     

Junction parameters for silicon devices characterization

An innovative method for device characterization is developed to qualify microelectronic devices. The method is based on parameter extraction from the junction I–V characteristics. Their evolution during electrical aging and ionizing radiation experiments allows an evaluation of the magnitude of the degradation. Results obtained with commercial samples show a signature of both manufacturer and technological processes. This method is easy to implement in a control process for device characterization.     

3D CMOS devices in recrystallized silicon

A 2 μm scale three-dimensional CMOS process has been developed which allows the fabrication of MOS devices in two independent active device layers. NMOS transistors have been fabricated in the substrate and CMOS devices, including inverters and ring oscillators, in a thin laser-recrystallized polysilicon layer. The processing parameters were determined carefully in order to obtain a monocrystalline top layer and to avoid any damage to the underlying devices already existing.     

Optimization of SIMOX for VLSI by electrical characterization

A comprehensive electrical characterization study which was conducted to optimize the fabrication of SIMOX substrates for VLSI is discussed. The oxygen implantation was carried out using medium-current and high-current implanters. The wafers were annealed at 1275°C and 1300°C to produce high-quality, precipitate-free material. The effect of dose, the effect of multiple implantation (by sequentially implanting and annealing), and the effect of the anneal ambient gas and the capping layer during annealing were studied. MOSFETs of various geometries with a gate oxide of ~20 nm were fabricated by a CMOS process incorporating the addition of a thin epitaxial Si layer. A general evaluation of each transistor was conducted by studying its static characteristics. The interface states, bulk traps, and carrier generation phenomena were studied. Good-quality interfaces were obtained. Better implantation control reduced contamination and suppressed deep traps below the detection limit. Multiple implantation resulted in superior material quality. as evidenced by very long generation lifetime values (> 100 μs)     

Optical and electrical characterization of GaN layers grown on silicon and sapphire substrates

Characterization of the structural, optical and electrical properties of GaN layers grown by two epitaxial techniques (ECR-MBE and MOCVD) using different substrates (vicinal Si111 and sapphire) has been performed. The quality of the samples grown by MOCVD seems to be influenced by the nitrogen source used for the growth. Unintentionally doped MBE samples with n-type concentrations around 10¹⁸ cm⁻³ and Hall mobility of 15 cm² (V s)⁻¹ were studied. GaN films doped with Mg and grown using AlN buffer layers have also been analyzed to study the influence of the thickness of the buffer layer on the optical properties of the GaN epilayer. In the samples with low Mg doping, a thin AlN buffer layer improved the optical quality of the film. In general, all the MBE samples doped with Mg were highly resistive, probably due to a low activation or high ionization energy of the Mg acceptors. Technological issues related to the formation of ohmic contacts on GaN layers are also presented.     

Picosecond GaAs photoconductors on silicon substrates for localintegration with silicon devices and circuits

A fabrication procedure for local integration of GaAs photoconductive devices with processed silicon circuits is discussed. The process allows isolated regions of GaAs to be epitaxially grown by MBE at temperatures which are compatible with already processed silicon circuits with first-level metallization. GaAs photoconductors with 15-μm gap lengths fabricated on silicon substrates have exhibited >16-mA sampling-oscilloscope-limited responses, with electrical pulse widths less than 20 ps as determined by autocorrelation measurements     

The effect of post-oxygen-implant annealing temperature on the channel mobilities of CMOS devices in oxygen-implanted silicon-on-insulator structures

The effects of post-oxygen-implant annealing temperature on the characteristics of MOSFET's in oxygen-implanted silicon-on-insulator (SOI) substrates are studied. The results show significant improvements in the electron and hole mobilities near the silicon/buried-oxide interface and in the electron mobility of the front-gate n-channel transistors in SOI substrates with higher post-oxygen-implant annealing temperature. The improvements in the transistor characteristics hence are attributed to the annihilation of oxygen precipitates and the reduction of defect density in the residual silicon film. By comparing the ring oscillators fabricated in SOI substrates annealed at 1150°C and 1250°C after oxygen implantation, a speed improvement of 15 percent is observed in substrates annealed at higher temperature.     

Characterization of interface defects in oxygen-implanted silicon films

Defects in ungated n- or p-type and gated p-type resistors have been characterized by photoinduced transient spectroscopy (PITS). These resistors were fabricated with p-type separation by implanted oxygen (SIMOX) wafers with a single-energy 200-keV oxygen implant to a total fluence of 1.8 × 10¹⁸ cm⁻². One wafer, used for gated resistor fabrication was implanted at 595°C and sequentially annealed at 1325°C for 4 h in argon (plus 0.5% oxygen) followed by 4 h in nitrogen (plus 0.5% oxygen). Another wafer, used for ungated resistor fabrication, was implanted at 650°C and annealed at 1275°C for 2 h in nitrogen (plus 0.5% oxygen). The photoconductive response of these resistors to a 1-μs long visible light pulse, measured at temperatures in the 80-to 170-K range, shows different persistent photoconductive effects due to trapped minority carriers that are somewhat linked to the thermal anneal given to the SIMOX wafers. Our results indicate that more damage is present in the wafer annealed at 1275°C than in the one annealed at 1325°C. We model the photoconductive response in terms of a perpendicular built-in field created in the conductive film by trapped charge located at or near the interface with the buried oxide. Defects distributed throughout the conductive film body or located at the interface with the gate oxide are not expected to contribute significantly to the PITS signature, because of the fabrication of the gate oxide with standard metal-oxide semiconductor technology. We estimate the average trap density at the back interface to be in the 10¹¹ cm² range.     

Precise characterization of long-distance mismatch of CMOS devices

A new test structure is presented for the characterization of long-distance mismatch of complimentary metal-oxide-semiconductor (CMOS) devices. A single circuit is used to characterize both transistors and resistors. High resolution is achieved by applying a four-terminal method with regulated reference potential to compensate for parasitic resistance effects. Measured data are presented for 0.5-, 0.35-, and 0.25-μm CMOS processes to demonstrate the performance of this approach. In particular, the long distance matching behavior is compared to that of neighboring devices. Examples for linear and nonlinear distance dependencies are shown. The long-distance mismatch has to be taken into account in circuit designs with short channel transistors and with narrow resistors     

Recent advances in thin-film silicon devices on sapphire substrates

The growth of silicon films on insulating substrates, their fabrication into active devices, and the advantages of such devices, especially for fast memory applications, were previously reported. Recent advances in these devices are described, including techniques of material growth and characterization, fabrication procedures, and device results. Thin-film resistors and capacitors operating at UHF have been prepared. With improvements in the material and device processing, bipolar transistors with current gains of 20-40 and useful operation between 500 and 1000 MHz were fabricated. MOS triodes and tetrodes which operate at the same frequency range and silicon-gate MOSFETs (SIGFETs), with voltage gains between 50-150 having negligible feedback capacitances (less than 0.02 pF/electrode), have been made. Thresholds of 1.5 and 2.5 V for p- and n-type devices were obtained. Application of these devices for microwave ICs and subnanosecond switching networks are described.     

A CPW T-resonator technique for electrical characterization ofmicrowave substrates

An impedance independent method is proposed using a finite ground coplanar waveguide (CPW) T-resonator to electrically characterize microwave materials. Silicon-based CPW T-resonators are designed and measured, with calibrated data agreeing well with other methods up to 30 GHz. Uncalibrated measurements produce dielectric constant and attenuation results within 3.7% and 25%, respectively, of those obtained with calibration. Hence, the CPW T-resonator can be used to provide rapid and accurate characterization of microwave substrates with unknown dielectric properties     

Midwave-infrared negative luminescence properties of HgCdTe devices on silicon substrates

We have investigated the negative luminescence properties of a midwave-infrared (MWIR) HgCdTe photodiode (λ_co = 5.3 μm at 295 K) grown on a silicon substrate. The internal negative luminescence efficiencies measured using a self-referencing optical technique were 88% throughout the 3–5 μm spectral region and nearly independent of temperature in the 240–300 K range. This corresponds to an apparent temperature reduction of 53 K at room temperature and 35 K at 240 K. Efficiencies measured by an electrical modulation technique were consistent with the measured internal efficiencies and the measured reflectivity of the device. This is the highest efficiency and largest apparent reduction in temperature reported to date, and slightly higher than that measured earlier for photodiodes grown on CdZnTe despite a longer cut-off wavelength. These results provide further indication that the HgCdTe/Si photovoltaic device technology is capable of combining high quality with high yield.     

Structure and electrical characteristics of silicon field emissionmicroelectronic devices

Field emission current was measured from arrays of wet chemically etched silicon cold-cathode diodes. Two types of cathode tips were measured both as-etched and after sharpening by low-temperature oxidation. The field enhancement increase resulting from tip sharpening is less than expected from simulation. The currents measured follow a Fowler-Nordheim characteristic and are temperature insensitive from 130 to 360 K. Turn-on voltage is near 4 V, a value much less than measured from most other field emission sources. With a 920-nm anode-cathode spacing, a minimum 0.2-μA current per cathode was found. Telegraph noise of about 1% at 20 V was observed. These sharpened silicon tips are a viable cold cathode for vacuum microelectronics and other electron device applications     

A novel low temperature integration of hybrid CMOS devices on flexible substrates

In this work we demonstrate a novel integration approach to fabricate CMOS circuits on plastic substrates (poly-ethylene naphthalate, PEN). We use pentacene and amorphous silicon (a-Si:H) thin-film transistors (TFTs) as p-channel and n-channel devices, respectively. The maximum processing temperature for n-channel TFTs is 180 °C and 120 °C for the p-channel TFTs. CMOS circuits demonstrated in this work include inverters, NAND, and NOR gates. Carrier mobilities for nMOS and pMOS after the CMOS integration process flow are 0.75 and 0.05 cm²/V s, respectively. Threshold voltages (V_t) are 1.14 V for nMOS and −1.89 V for pMOS. The voltage transfer curve of the CMOS inverter showed a gain of 16. Correct logic operation of integrated flexible NAND and NOR CMOS gates is also demonstrated. In addition, we show that the pMOS gate dielectric is likely failing after electrical stress.     

Measurement and modeling of circuit speed of CMOS on oxygen-implanted SOI

The dependence of the stage delay of CMOS ring oscillators on the voltage applied to the underlying silicon substrate has been investigated for SOI substrates formed by high-dose oxygen ion implantation. Improvements in speed of up to 30 percent are produced when the silicon under the isolating oxide is depleted. This situation occurs naturally for zero applied voltage when the substrate is lightly doped p-type and gives the oxygen-implanted SOI similar speed performance to other forms of SOI with thicker isolation layers. The increased speed is in good agreement with predictions made using SPICE simulation and modeled circuit capacitances.     

Characterization of CMOS devices for VLSI

CMOS bulk and SOS technologies are discussed for VLSI with emphasis on static and dynamic characteristics of two-input NAND gates. Optimum performance (minimum figure of merit FM = tpdPd) is obtained for a CMOS/SOS two-input NAND gate (FO = 2, CL= 22 fF) with an electrical channel length L = 0.75 µm, channel width W = 5.0 µm, and oxide thickness Xo= 450 Å with VDD= 3.0 V, to yield tpd= 400 ps and Pd= 250 µW (tpdPd= 100 fJ) at room temperature. Bulk technology performs within a factor of 2 of SOS for tpdand Pd. CMOS technologies offer subnanosecond propagation delays, similar to ECL bipolar, at the low submilliwatt power levels of CMOS. An analytical expression for tpddescribes the performance of two-input NAND gates in terms of device modeling and fabrication parameters. Such an expression provides a hierarchial modeling approach to characterize minicells for VLSI.     

Laser thermal processing of amorphous silicon gates to reduce poly-depletion in CMOS devices

One major challenge in advanced CMOS technology is to have adequate dopant activation at the polycrystalline silicon (poly-Si) gate/gate oxide interface to minimize the poly-Si depletion effect. In this paper, laser thermal processing (LTP) was employed to fabricate single or dual-layer poly-Si-gated MOS capacitors with ultrathin gate oxides. Capacitance-voltage data show that the carrier concentration at the poly-Si gate/gate oxide interface increases substantially when the devices are subjected to LTP prior to a rapid thermal anneal (RTA). Thus, LTP readily reduces the poly-depletion thickness in MOS devices. For p/sup +/-gated capacitors, this is achieved with boron penetration that is equivalent to the control sample with 1000/spl deg/C, 5 s RTA (without LTP). In addition, results from secondary ion mass spectrometry indicate that the concentration of dopants near the critical gate/gate oxide interface increases significantly after a post-LTP anneal, in good agreement with the electrical data. Time-dependent dielectric breakdown studies show that the gate oxide reliability is not degraded even after LTP at high fluences.