The characteristics of CMOS devices in oxygen-implantedsilicon-on-insulator structures

The characteristics of CMOS devices fabricated in oxygen-implanted silicon-on-insulator (SOI) substrates with different oxygen doses are studied. The results show that transistor junction leakage currents are improved by orders of magnitude when the oxygen dose is decreased from 2.25×10¹⁸ cm^-2 to 1.4×10¹⁸ cm^-2 . The floating-body effect, i.e. transistor turn-on at lower gate voltage with dramatic improvement in subthreshold slope when the drain voltage is increased, is enhanced by the reduction in leakage current and hence the oxygen dose. In SOI substrates implanted with 1.4×10¹⁷ cm^-2 oxygen dose and annealed at 1150°C, back-channel mobilities are decreased by several orders of magnitude compared to the mobilities in the precipitate-free silicon film. These device characteristics are correlated with the microstructure at the silicon-buried-oxide interface, which is controlled by oxygen implantation and post-oxygen-implantation anneal     

A CV technique for measuring thin SOI film thickness

A technique is developed to measure silicon-on-insulator (SOI) silicon device film thickness using a MOSFET. The method is based on CV measurements between gate and source/drain at two different back-gate voltages. The SOI devices used in this study were n⁺ polysilicon gate n-channel MOSFETs fabricated with modified submicrometer CMOS technology on SIMOX (separation by implanted oxygen) wafers. The SIMOX wafers were implanted with a high dose of oxygen ions (10¹⁸ cm^-2) at 200 keV and subsequently annealed at 1230°C. The NMOS threshold boron implant dose is 2×10¹² cm^-2. This method is simple, nondestructive, and no special test structure is needed. Using this technique, SOI film thickness mapping was made on a finished wafer and a thickness variation of ±150 Å was found     

Pre-alloying implants with indium as an enabling technology to extend titanium salicide towards 0.1-μm linewidths

Pre-amorphisation implants (PAI) are the most promising technique to extend the use of TiSi₂ towards 0.1 μm. We report an implant strategy using indium, employing its favourable alloying properties towards silicon, titanium and the dopants. Its implementation in a 0.18-μm CMOS technology gave full C54–TiSi₂ transformation on poly lines. Additionally the NMOS contact resistances were found to be largely reduced. Data on unpatterned monitor wafers show indium to reduce the C54–TiSi₂ transformation temperature by at least 50°C, whereas the reduction found when using arsenic as implant species is 25°C.     

Properties of nitrogen-implanted SOI substrates

Properties of nitrogen-implanted silicon-on-insulator (SOI) substrates prepared by implanting different doses of 200 keV nitrogen into 50-70 Ω-cm, p-type silicon substrates at a temperature of 500°C were studied. The distribution of nitrogen was studied using Auger electron spectroscopy. The electrical properties of the active overlayer were studied using Hall-effect measurements and capacitance-voltage depth profile analysis. The insulating integrity of the buried nitride was studied by directly measuring the leakage current from top to bottom through the substrate. Additionally, electric field strength and surface roughness measurements were performed. Nitrogen concentrations in the buried layer increased from below to above the stoichiometric value for Si₃N₄ for increasing dose in the range studied. Nitrogen-related n-type doping is observed in all samples examined, and the magnitude of the doping increased with the increasing implant dose. Insulating buried nitride layers are formed only in samples implanted with very high doses     

Use of transient enhanced diffusion to tailor boron out-diffusion

We report experimental results demonstrating the use of transient enhanced diffusion (TED) caused by silicon implant for “tuning” boron out-diffusion. The effect was measured as a function of the silicon implant dose and anneal temperature, and a range of boron junction depth movement from almost none up to 81 nm was observed with increasing TED at 750°C. The diffused profiles could be approximated by using a modified solubility limit model to describe the enhanced boron diffusion and clustering. However, by using a more sophisticated continuum model based on atomistic calculations, excellent agreement with the measured profiles could he obtained. In addition, the fit to the measured data yields the fraction of boron present in BI₂ precursor clusters after silicon implant as a function of the silicon implant dose. Two possible applications of the TED “tuning” are discussed, with device simulations which show that the effect is sufficiently large to tune the base width of a bipolar device from being depleted to that suitable for a high performance device     

Gate engineering for deep-submicron CMOS transistors

Gate depletion and boron penetration through thin gate oxide place directly opposing requirements on the gate engineering for advanced MOSFET's. In this paper, several important issues of deep-submicron CMOS transistor gate engineering are discussed. First, the impact of gate nitrogen implantation on the performance and reliability of deep-submicron CMOSFET's is investigated. The suppression of boron penetration is confirmed by the SIMS profiles, and is attributed mainly to the diffusion retardation effect in bulk polysilicon by the presence of nitrogen. The MOSFET' I-V characteristics, MOS capacitor quasi-static C-V curves, SIMS profiles, gate sheet resistance, and oxide Q_bd are compared for different nitrogen implant conditions. A nitrogen dose of 5×10¹⁵ cm^-2 is found to be the optimum choice at an implant energy of 40 keV in terms of the overall electrical behavior of CMOSFET's. Under optimum design, gate nitrogen implantation is found to be effective in eliminating boron penetration without degrading performance of either p⁺ gate p-MOSFET and n⁺ gate n-MOSFET. Secondly, the impact of gate microstructure on the performance of deep-submicron CMOSFET's is discussed by comparing poly and amorphous silicon gate deposition technologies. Thirdly, poly-Si_1-xGe_x is presented as a superior alternative gate material. Higher dopant activation efficiently results in higher active-dopant concentration near the gate/SiO₂ interface without increasing the gross dopant concentration. This plus the lower annealing temperature suppress the dopant penetration. Phosphorus-implanted poly-Si_1-xGe_x is gate is compared with polysilicon gate in this study     

The effect of dose rate and implant temperature on transient enhanced diffusion in boron implanted silicon

The effect of ion implantation dose rate and implant temperature on the transient enhanced diffusion (TED) of low energy boron implants into silicon was investigated. The implant temperature was varied between 5 and 40°C. The beam current was varied from 0.035 to 0.35 mA/cm². Three different defect regimes were investigated. The first regime was below the formation of any extended defects (5 keV B⁺ 2 × 10¹⁴/cm²) visible in the transmission electron microscope. The second regime was above the {311} formation threshold (2×10¹⁴/cm²) but below the subthreshold (type I) dislocation loop formation threshold. The final regime was above both the {311} and dislocation loop formation threshold (10 keV 5×10¹⁴/cm²). TED for these conditions is shown to be over after annealing at 750°C for 15–30 min. Secondary ion mass spectroscopy results for the three different damage regimes indicate that there is no measurable effect of dose rate or implant temperature on TED of boron implanted silicon for any of the damage regimes. It should be emphasized that the dose and energy of the boron implants is such that none of these implants approached the amorphization threshold. Above amorphization dose rate and implant temperature have dramatic effects on TED, but it appears that below the amorphization threshold there is little effect. These results suggest that for a given energy it is the ion dose not the extent of the implant damage that determines the extent of TED in boron implanted silicon.     

A comparative study of CMOS processes for VLSI applications

A comparative study of simulated circuit performance has been made in order to determine the optimum process parameters for p-well CMOS with feature sizes of between 1 and 2 µm. it has been found that for the process considered, best speed, Power, and packing density are achieved with a substrate concentration of between 3 × 10¹⁵and 10¹⁶cm^-3and an operating voltage which is as low as possible. Higher speed can be attained at the expense of considerably more power dissipation through the use of a higher rail voltage. Silicon-on-insulator CMOS has been considered as an alternative to p-well CMOS. This technology can be expected to out-perform small geometry bulk silicon CMOS if recent improvements in material quality can be maintained.     

The effect of 1300-1380°C anneal temperatures and materialcontamination on the characteristics of CMOS/SIMOX devices

The characteristics of CMOS transistors fabrication on silicon implanted with oxygen (SIMOX) materials were measured as a function of the silicon superficial layer contamination levels. In addition, postimplant anneal temperatures of 1300°C, 1350°C, and 1380°C were examined. It is found that the transistor leakage currents as well as the integrity of the gate oxide and implanted SIMOX oxide are functions of the carbon content in the starting material. Leakage currents below 1.0×10^-12 A/μm of channel width have been measured when the carbon concentration is reduced to 2×10¹⁸/cm². In addition, the integrity of the transistor gate dielectric, SIMOX implanted oxide, and oxygen precipitate density are seen to be a function of the postimplant anneal temperature. A gate dielectric breakdown field of 10 MV/cm has been achieved when the postimplant temperature is increased to 1380°C     

A thermal van der Pauw test structure

A micromachined thermal van der Pauw test structure is reported. Similar in principle to the conventional electrical van der Pauw Greek cross test structures, it enables the in-plane thermal sheet conductivities of thin films to be determined. The microstructure was fabricated using a commercial CMOS application-specific integrated circuit process followed by anisotropic silicon etching. It consists of a cross-shaped sandwich of the dielectric CMOS layers isolated from the bulk silicon by four narrow suspension arms. Integrated polysilicon resistors make it possible to generate controlled amounts of heat power and to measure local temperature changes to determine the thermal response of the structure. The measurement principle exploits the analogy between the two-dimensional (2-D) heat flow in thin film samples and the electrical current pattern in thin film conductors. A thermal sheet resistance of 1.87×10⁵ K/W was extracted from the complete sandwich of the dielectric CMOS layers. This resistance is equivalent to an average in-plane thermal conductivity of the dielectric layer sandwich of κ=1.44 W m^-1 K^-1. Thermal finite element simulations showed that the radiative heat loss from the structure has a negligible effect on the extracted κ value     

Deposition and characterization of Pb TiO3 thin films on silicon wafers using metalorganic sources

Ferroelectric PbTiO₃ thin films were deposited on bare silicon and Pt/SiO₂/Si substrates by metalorganic chemical vapor deposition in a temperature range from 270 to 550°C. The deposition of a single phase PbTiO₃ thin film did not occur on bare silicon substrates. Instead a double layer of lead-silicate and PbTiO₃ was formed owing to a serious diffusion of lead and oxygen ions into silicon substrates. But on Pt/SiO₂/Si substrates, a single phase PbTiO₃ oriented parallel to a-and c-axis was grown at a substrate temperature as low as 350°C even without a high temperature post-annealing. To get an optimal film, a precise control of input gas composition and also a deposition in a low temperature range from 350 to 400°C are necessary.     

Fully symmetric cooled CMOS on (110) plane

A cooled CMOS device using dual-polysilicon gates, (110) Si substrates, lightly doped drains with doping concentrations of 10¹⁴ cm^-2, and no channel implant is described. It is found that the peak mobility of a p⁺ polysilicon gate pMOS transistor on a (110) plane is 1.6 times larger than that on a (100) plane at 77 K. This pMOS transistor si very promising for use at 77 K because of its steeper subthreshold slope and higher hole mobility. The design has realized fully symmetrical cooled CMOS devices with 0.8-μm gates in which saturation currents and transductances of both n and pMOS transistors have been almost equalized. This fully symmetric cooled CMOS increases the ring oscillator speed by a factor of 1.2 and allows flexible CMOS circuit design that allows effective use of NOR gates     

On the resistivity of TiSi2: The implication for low-temperature applications

The electrical resistivity of TiSi2formed on polysilicon implanted with phosphorus and arsenic and on n⁺and p⁺diffusions implanted with arsenic and boron was measured in the 4.2-300 K temperature range. It is found that in all cases, the resistivity is reduced by a factor of 3-4 when TiSi2is cooled from room to liquid-nitrogen temperature. Sheet resistance as low as 1 Ω/sq. at liquid-nitrogen temperature can be easily achieved for self-aligned thin TiSi2layers over polysilicon and diffusion regions, which is very attractive for low-temperature CMOS applications. The residual resistivity ratio, which is a measure of the electron mean free path, decreases with growing surface concentration of dopants, regardless of doping species. The analysis of thickness effects in terms of surface scattering and of grain boundary resistivity models, suggests that degradation of sheet resistance Rswith increased implantation dose is due only partly to the difficulty in forming thick enough TiSi2at high doses, and that dopant impurities segregated at the grain boundaries can account for the observed increase.     

Low-temperature (⩽550°C) fabrication of poly-Si thin-filmtransistors

High performance n- and p-channel thin-film transistors (TFTs) have been fabricated in polycrystalline silicon films using a self-aligned-gate process without exceeding 550°C. This process features the use of polycrystalline Si_0.5Ge_0.5 for the gate material and high-dose H⁺ implantation for grain-boundary passivation so that shorter process times can be used. Low threshold voltages of 2.8 and -0.2 V, and high field-effect mobilities of 35 and 28 cm²/V-s, where achieved by the NMOS and PMOS devices, respectively. The performance of these devices is comparable to that of previously reported devices fabricated using process temperatures up to 600°C, and is adequate for large-area-display peripheral driver circuits. The significant reduction in maximum process temperature makes this process advantageous for the fabrication of CMOS circuits on large-area glass substrates     

An advanced MOS-IC process technology using local oxidation ot oxygen-doped polysilicon films

An O-POS (oxygen-doped polysilicon) film, deposited directly on silicon, is oxidized locally to create an active gate area. The electrical properties for the active gate area are the same as conventional p- and n-channel MOS devices, but the field area has an extremely high threshold voltage for both p- and n-type silicon substrates. The electrical properties in metal/oxidized O-POS/silicon and metal/oxide/O-POS/silicon structures have been investigated while varying the O-POS film thickness, oxygen concentration, local oxidation time, and silicon substrate resistivity. According to these basic studies, it is proposed that the high density of trapping centers existing in O-POS film is responsible for the high field threshold voltage. A applications of this process technology, a silicon-gate CMOS integrated circuit, and a high voltage n-channel MOS device are discussed.     

Effects of oxygen on crystallization of amorphous silicon films and polysilicon TFT characteristics

Oxygen ions were implanted into the amorphous silicon film deposited at 540°C in order to study the effects of oxygen on the solid phase crystallization of silicon films. The resulting films were investigated using transmission electron microscopy, x-ray diffraction (XRD), and also by measuring the electrical characteristics of polycrystalline silicon thin film transistors (TFTs) fabricated in the crystallized films. The development of {111} texture as a function of annealing time is similar to films implanted with Si, with higher oxygen samples showing more texture. Transmission electron microscopy shows that the grain size of completely crystallized films varies little with oxygen concentration. The electrical performances of TFTs are found to degrade with increasing oxygen dose. The trap state density increases from 5.6 × 10¹²/cm² to 9.5 × 10¹²/cm² with increasing oxygen dose. It is concluded that for a high performance TFT, oxygen incorporation in the Si film should be kept to 10¹⁹/cm³ or less.     

High value implanted resistors for microcircuits

Boron ion implantation has been used to fabricate high sheet resistance p-type junction resistors in silicon substrates. Thermally grown SiO2and conventional photolithography were employed to define the resistor geometries. Ion doses in the range 0.5 × 10¹³to 10 × 10¹³ions/cm²with energies ranging from 30 to 55 keV followed by anneal at 950°C were used. The temperature coefficient of resistance (TCR), voltage coefficient of resistance (VCR), junction Characteristics, and noise level of these resistors have been studied for sheet resistances ρx, from 0.8 to 11 kΩ/square. Over this range of sheet resistances the TCR increases smoothly from approximately 800 to 4000 PPM/°C with the lower TCR corresponding to the lower sheet resistance. For 3 kΩ square implanted resistors, the variation of resistance with temperature closely matches that found for a standard boron base and resistor (B&R) diffusion having a sheet resistance of 140 Ω/square. The junction leakage and the noise level of the implanted resistors can be made comparable to that obtained for diffused resistors. The implanted resistor exhibits a positive VCR, which increases with increasing sheet resistance as a result of depletion-layer pinch-off action from the substrate. Details of the implant conditions and process control are discussed. Experimental results demonstrating the compatibility of the resistor implantation process with microcircuits using low current, high β diffused bipolar transistors are presented.     

p-Channel TFT's using magnetron-sputtered Ta2O5films as gate insulators

Metal-gate thin-film transistors (TFT's) have been fabricated in layers of laser-recrystallized polycrystalline silicon on fused quartz substrates at processing temperatures below 625°C. Tantalum pentoxide (Ta2O5) was used as a gate insulator instead of a conventional thermally grown silicon dioxide (SiO2). Ta2O5gate insulator was deposited onto the recrystallized silicon layer at room temperature, using an RF-magnetron sputtering system. The reactive ion etching method, using CF4as a reactive gas, was employed in patterning deposited Ta2O5. These TFT's have exhibited p-channel depletion-mode characteristics with a threshold voltage of 2.5 V and a transconductance of 70 µS at Vg= - 2 V. An on-off current ratio exceeding 10⁵has been obtained.     

High efficiency polycrystalline silicon solar cells by continuous plasma deposition and laser recrystallization

Solar cells of up to 12% efficiency have been fabricated on laser recrystallized fine grain polycrystalline silicon films produced by high pressure plasma (hpp) aided hydrogen reduction of trichlorosilane. The hpp system was operated in a continual mode to produce microcrystalline silicon films continually using finite size temporary molybdenum substrates. The major improvement over previous devices of this type is in the elimination of oxygen contamination during laser recrystallization. This resulted in a reduction in the dark excess junction current and improvement in minority carrier diffusion length. The devices are found to be diffusion limited, with diffusion current coefficients in the range of 3 × 10^-12to 5 × 10^-12A/cm²when the base resistivity was 0.4 to 0.5 Ω-cm p-type.     

Threshold voltage shift of n-channel Si-gate MOSFET's

The relationship between the threshold voltage shift of the n-channel Si-gate MOSFET and the implant dose of boron ions has been examined theoretically and experimentally when these ions are implanted with an energy of 60 keV through a gate oxide of 1200 Å into a p-type silicon substrate of the acceptor concentration of 7 × 10¹⁴/cm³. The effect of high-temperature treatment after ion implantation on the threshold voltage shift has been considered. The good agreement between the theory and the experiment verifies that the model used is reasonable. The threshold voltage shift with the dose is expressed by about 5 × 10^-12V.cm²below a dose of 5 × 10¹¹ions/cm². Above this value, the increase of the threshold voltage shift becomes slow and the slope takes the value of about 2 × 10^-12V.cm²due to the maximum surface depletion layer.