A Functional Decomposition Method for Redundancy Identification and Test Generation

We present a new combinational circuit automatic test-pattern generation (ATPG)acceleration method called EST that detects equivalent search states, which are saved for later use. The search space is learned and characterized using E-frontiers, which are circuit cut-sets induced by theimplication stack contents. The search space is reduced by matchingthe current search state against previously-encountered search states(possibly from prior faults), and this reduces the length of thesearch. A second contribution is a calculus of redundant faults, which enables EST to make many more mandatoryassignments before search than is possible by prior algorithms, byeffectively using its knowledge of prior faults proven to beredundant. This accelerates ATPG for subsequent faults. Thesemethods accelerate the TOPS algorithm 33.3 times for thehard-to-test faults in the ISCAS 85 benchmarks, and the SOCRATES algorithm 5.6 times for the same hard-to-test faults, with little memory overhead.     

Test Generation for Crosstalk-Induced Faults: Framework and Computational Results

Due to technology scaling and increasing clock frequency, problems due to noise effects lead to an increase in design/debugging efforts and a decrease in circuit performance. This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital combinational circuits. These noise effects can propagate through a circuit and create a logic error in a latch or at a primary output. We have developed a mixed-signal test generator, called XGEN, that incorporates classical static values as well as dynamic signals such as transitions and pulses, and timing information such as signal arrival times, rise/fall times, and gate delay. In this paper we first discuss the general framework of the test generation algorithm followed by computational results. Comparison of results with SPICE simulations confirms the accuracy of this approach.     

Low-Profile Air-Filled Antenna for Next Generation Wireless Systems

In this study, a novel design of insensitive antenna with improved radiation performance is designed and investigated. The antenna exhibits excellent performance in terms of impedance-matching, radiation and total efficiencies, even though it is designed and fabricated using high loss substrate (FR) with compact dimension. An L-shaped metal-ring resonator has been used as a main resonator of the antenna to operate at 18.5 GHz. In order to improve the antenna performance, a part of substrate with L-shaped configuration has been removed and a metal ring structure is inserted. By using this technique, we can improve the efficiency characteristic of the antenna and eliminate the effect of high-loss FR-4 substrate. The center frequency of the designed antenna can be controlled by adjusting the values of the antenna parameters. Since the main substrate of the resonator is the air, the antenna is insensitive for different types of antenna substrates. It has the return loss characteristic less than ?10 dB in the frequency range of 17.5–19.5 GHz (more than 10% fractional bandwidth). The antenna has a very compact size with good radiation behavior and could be used in phased array antennas for next generation systems.     

New Techniques for Deterministic Test Pattern Generation

This paper presents new techniques for speeding up deterministic test pattern generation for VLSI circuits. These techniques improve the PODEM algorithm by reducing number of backtracks with a low computational cost. This is achieved by finding more necessary signal line assignments, by detecting conflicts earlier, and by avoiding unnecessary work during test generation. We have incorporated these techniques into an advanced ATPG system for combinational circuits, called ATOM. The performance results for the ISCAS85 and full scan version of the ISCAS89 benchmark circuits demonstrated the effectiveness of these techniques on the test generation performance. ATOM detected all the testable faults and proved all the redundant faults to be redundant with a small number of backtracks in a short amount of time.     

智能化生产测试解决方案实现下一代智能化光网络

在网络发展过程中,元器件生产厂商在推动技术发展的同时需要不断降低成本,这是在当前市场中保持竞争优势的唯一方式。影响光器件成本结构的一个重要因素是测试成本,它最多可以占到光器件成本的40％。安捷伦光通信测试解决方案体现了光纤技术的发展,数量日益增多的各种元器件要求通用的光器件测试解决方案。光器件测试解决方案必须面对的新的挑战是强力支持元器件生产中降低成本的目标。智能测试解决方案对下一代生产车间的主要贡献在于现生产环境自动化、降低测试成本、同时增强光通信测试精确、快速、可靠测量的优势。     

On the Use of Multiple Hops in Next Generation Wireless Systems

Traditional cellular networks provide a centralized wireless networking paradigm within the wireless domain with the help of fixed infrastructure nodes such as Base Stations (BSs). On the other hand, Ad hoc wireless networks provide a fully distributed wireless networking scheme with no dependency on fixed infrastructure nodes. Recent studies show that the use of multihop wireless relaying in the presence of infrastructure based nodes improves system capacity of wireless networks. In this paper, we consider three recent wireless network architectures that combine the multihop relaying with infrastructure support – namely Integrated Cellular and Ad hoc Relaying (iCAR) system, Hybrid Wireless Network (HWN) architecture, and Multihop Cellular Networks (MCNs), for a detailed qualitative and quantitative performance evaluation. MCNs use multihop relaying by the Mobile Stations (MSs) controlled by the BS. iCAR uses fixed Ad hoc Relay Stations (ARSs) placed at the boundaries to relay excess traffic from a hot cell to cooler neighbor cells. HWN dynamically switches its mode of operation between a centralized Cellular mode and a distributed Ad hoc mode based on the throughput achieved. An interesting observation derived from these studies is that, none of these architectures is superior to the rest, rather each one performs better in certain conditions. MCN is found to be performing better than the other two architectures in terms of throughput, under normal traffic conditions. At very high node densities, the variable power control employed in HWN architecture is found to be having a superior impact on the throughput. The mobility of relay stations significantly influences the call dropping probability and control overhead of the system and hence at high mobility iCAR which uses fixed ARSs is found to be performing better. This work was supported by Infosys Technologies Ltd., Bangalore, India and the Department of Science and Technology, New Delhi, India. B. S. Manoj received his Ph.D degree in Computer Science and Engineering from the Indian Institute of Technology, Madras, India, in July 2004. He has worked as a Senior Engineer with Banyan Networks Pvt. Ltd., Chennai, India from 1998 to 2000 where his primary responsibility included design and development of protocols for real-time traffic support in data networks. He had been an Infosys doctoral student in the Department of Computer Science and Engineering at the Indian Institute of Technology-Madras, India. He is a recipient of the Indian Science Congress Association Young Scientist Award for the Year 2003. Since the beginning of 2005, he has been a post doctoral researcher in the Department of Electrical and Computer Engineering, University of California, San Diego. His current research interests include ad hoc wireless networks, next generation wireless architectures, and wireless sensor networks. K. Jayanth Kumar obtained his B.Tech degree in Computer Science and Engineering in 2002 from the Indian Institute of Technology, Madras, India. He is currently working towards the Ph.D degree in the department of Computer Science at the University of California, Berkeley. Christo Frank D obtained his B.Tech degree in Computer Science and Engineering in 2002 from the Indian Institute of Technology, Madras, India. He is currently working towards the Ph.D. degree in the department of Computer Science at the University of Illinois at Urbana-Champaign. His current research interests include wireless networks, distributed systems, and operating systems. C. Siva Ram Murthy received the B.Tech. degree in Electronics and Communications Engineering from Regional Engineering College (now National Institute of Technology), Warangal, India, in 1982, the M.Tech. degree in Computer Engineering from the Indian Institute of Technology (IIT), Kharagpur, India, in 1984, and the Ph.D. degree in Computer Science from the Indian Institute of Science, Bangalore, India, in 1988. He joined the Department of Computer Science and Engineering, IIT, Madras, as a Lecturer in September 1988, and became an Assistant Professor in August 1989 and an Associate Professor in May 1995. He has been a Professor with the same department since September 2000. He has held visiting positions at the German National Research Centre for Information Technology (GMD), Bonn, Germany, the University of Stuttgart, Germany, the University of Freiburg, Germany, the Swiss Federal Institute of Technology (EPFL), Switzerland, and the University of Washington, Seattle, USA. He has to his credit over 120 research papers in international journals and over 100 international conference publications. He is the co-author of the textbooks Parallel Computers: Architecture and Programming, (Prentice-Hall of India, New Delhi, India), New Parallel Algorithms for Direct Solution of Linear Equations, (John Wiley & Sons, Inc., New York, USA), Resource Management in Real-time Systems and Networks, (MIT Press, Cambridge, Massachusetts, USA), WDM Optical Networks: Concepts, Design, and Algorithms, (Prentice Hall, Upper Saddle River, New Jersey, USA), and Ad Hoc Wireless Networks: Architectures and Protocols, (Prentice Hall, Upper Saddle River, New Jersey, USA). His research interests include parallel and distributed computing, real-time systems, lightwave networks, and wireless networks. Dr.Murthy is a recipient of the Sheshgiri Kaikini Medal for the Best Ph.D. Thesis from the Indian Institute of Science, the Indian National Science Academy (INSA) Medal for Young Scientists, and Dr. Vikram Sarabhai Research Award for his scientific contributions and achievements in the fields of Electronics, Informatics, Telematics & Automation. He is a co-recipient of Best Paper Awards from the 1st Inter Research Institute Student Seminar (IRISS) in Computer Science, the 5th IEEE International Workshop on Parallel and Distributed Real-Time Systems (WPDRTS), and the 6th and 11th International Conference on High Performance Computing (HiPC). He is a Fellow of the Indian National Academy of Engineering.     

THERMODEL: A Tool for Thermal Model Generation, and Application for MEMS

This paper presents a tool and a method for the generation of reduced order thermal models, in order to assure modeling the effect of the package on the thermal behavior of the packaged device. The method is generic, and can be based either on the simulated or on the measured thermal transient response of the real packages. It is based on the generation of the time constant density spectrum of the thermal response function, from which we automatically generate a reduced order thermal model in the form of an RC ladder network model. Beyond presenting the generic methodology experimental results are also presented, based both on the simulation and measurement of MEMS elements and packages.     

基于分布估计算法的组合电路测试生成

基于遗传算法生成的测试矢量集的故障覆盖率要低于确定性方法．本文分析指出造成这种现象的一个可能原因在于，组合电路测试生成过程中存在高阶、长距离模式，从而导致遗传算法容易陷人局部极值或早熟收敛．为此，本文首次提出使用分布估计算法生成测试矢量．该方法使用联合概率分布捕捉电路主输人之间的关联性。从而避免了高阶、长距离模式对算法的影响，缓解了算法早熟收敛问题．针对ISCAS-85国际标准组合电路集的实验结果表明，该方法能够获得较高的故障覆盖率．     

时序电路测试生成新算法研究

为解决同步时序电路的测试难题,提高时序电路测试生成效率,进行了时序电路测试生成算法的研究,将粒子群优化算法应用在时序电路的测试生成中。为验证PSO算法性能,首先将其用于函数优化,能获得较好的优化结果。之后建立自动测试生成离散粒子群速度—位置模型,针对国际标准时序电路的验证结果表明,与同类算法相比,该算法可以获得较高的故障覆盖率和较小的测试矢量集。     

基于LXI的干扰控制及信号产生设备自动测试系统设计

干扰控制及信号产生设备指标类型多样,当前的测试方式流程繁杂,人工工作量大。干扰控制及信号产生设备的自动测试系统提供了高精度的测试环境,简化了测试流程,提高了测试可靠性与效率。介绍了基于LXI的干扰控制及信号产生设备自动测试系统的实施方案。     

Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test Tools

Cell Fault Model (CFM) is a well-adopted functional fault model used for cell-based circuits. Despite of the wide adoption of CFM, no test tool is available for the estimation of CFM testability. The vast majority of test tools are based on the single stuck-at fault model.In this paper we introduce a method to calculate the CFM testability of a cell-based circuit using any single stuck-at fault based test tool. Cells are substituted by equivalent cells and Test Generation and Fault Simulation for CFM are emulated by Test Generation and Fault Simulation for a set of single stuck-at faults of the equivalent cells. The equivalent cell is constructed from the original cell with a simple procedure, with no need of knowledge of gate-level implementation, or its function. With the proposed methodology, the maturity and effectiveness of stuck-at fault based tools is used in testing of digital circuits, with respect to Cell Fault Model, without developing new tools.     

Delay Test Generation: A Hardware Perspective

An important problem one faces during design of a built-in self-test(BIST) based delay test is the selection of a proper generator toapply the test vectors. This problem is due to the need of applyinga pair of patterns to detect any given delay fault. The secondvector has to be launched against the logic immediately following thefirst vector. This timing requirement places severe restrictions onthe kind of hardware suitable for the task, especially in built-inself-test applications where the generator must reside on chip.This paper studies the various options one has in designing the delay test vector generator. Both scan and non-scan designs are addressed. Thedifferent options are measured based on their performance, cost, and flexibility.     

一种基于模块化仪器的轴角转换器自动测试系统

提出了一种基于模块化仪器轴角转换器自动测试系统的设计与实现。该测试系统应用高精度轴角测试仪器,研究解决了模块化仪器应用,完成了硬件电路结构设计、软件功能及界面设计。该系统具有角精度测试、电压量测试、电流量测试、测试数据记录及保存等功能。经测试表明：单通道最大误差0.005°,电压、电流量测试分辨率6.5位,可广泛应用于各型轴角转换器的性能指标测试。     

下一代网络中业务感知模型研究

下一代网络（NGN）是业务驱动的网络,提供具有不同QoS要求的IP业务是NGN需要解决的关键问题,感知网络中的各种业务流对NGN的管理和安全具有重要意义。本文通过以对VoIP和P2P为代表的下一代网络业务有效识别、控制和管理技术的研究,从业务识别、业务管理等方面提出了网络业务识别系统,设计出应用于下一代网络的业务感知模型,能有效解决下一代网络由于缺乏应用层业务感知而导致的网络管理、网络安全等问题。     

基于用户行为的网站推荐系统模型

网上营销的难点是如何寻找潜在客户。识别用户行为是一个复杂的过程,建议采用二维模型来寻找相关的项目,然后推荐给用户。但太多不相干的建议转化为用户信息过载问题。本研究的目的是在每个维度中找出已被用户搜索的项目／对象,最受好评的每个维度中的项目可给予建议。要做到这一点,我们采用张量,它可以有效地模拟多维Web日志中的用户搜索数据,然后确定在每一个搜索维度上的用户模型。所有的评估均基于真实数据集,这清晰地显示出比其他广泛使用的向量和矩阵方法的有效性。     

面向航天嵌入式电子系统的测试语言研究

测试语言主要分2类:面向仪器的测试语言和面向信号的测试语言。通过分析2种测试语言的优缺点,结合我国航天嵌入式电子系统测试系统的特点,提出一种基于虚拟仪器的面向航天嵌入式电子系统的测试语言,该语言主要借鉴ATLAS的关键语句,将其解释为测试框架配置文件和测试文档;同时还描述该测试语言的程序格式和执行机制。     

测试用例自动生成方法的现状及研究

软件测试数据生成在软件系统开发费用中占很大比重。如果该过程能自动实现,则会极大地减少软件开发的周期和费用。测试用例的生成工作包含选定被测任务、分析输入数据、确定其取值并分析对应的输出数据。其中分析对应的输出数据是决定测试是否成功的关键环节。测试用例选取的一个中心原则,就是以用最少的测试用例找到尽可能多的错误。目前的工具尚不能完成自动生成测试用例这个环节,往往是只能采用人工选取的方法。按所采用的方法和研究对象的不同,将测试用例自动生成方法主要分为5类:基于有限状态集的测试,基于标注的转换系统的测试,针对面向模型的需求规格说明的测试,针对面向对象软件的测试,以及运用模型检查生成测试用例的方法。在简单介绍前4种方法之后,重点对模型检查的方法进行详细的分析和探讨。     

下一代网络中的业务融合模式

随着全业务运营的需要以及技术的发展,通信业务的融合成为业界的焦点问题。业务融合需要解决固网移动融合、传统通信与因特网业务融合两个方面的问题,这需要从终端能力、网络融合两个方面入手,平衡开放性与可运营性之间的冲突。从可运营的角度来看,统一认证授权是业务融合的基础条件,网络组件化、终端开放化是业务融合的技术解决方案。     

用于协议一致性测试序列生成的状态规范化算法

这篇论文提出了一种方法，把ＥＦＳＭ描述协议的广泛性和ＦＳＭ测试序列生成方法的成熟性有机的结合起来，较圆满地解决了测试序列的可执行性、观察性、控制性问题，同时兼顾了数据流和控制流的全面测试。这种方法是基于两边靠拢的思想，一方面将非确定性的ＥＦＳＭ向确定性的ＤＦＳＭ规范化，另一方面修改ＦＳＭ的测试序列生成算法，使之能够同时测试数据流，也即能够处理输入、输出原语的参数问题。在本文中讲述了第一步的工作，提出了由ＥＦＳＭ到ＤＦＳＭ的规范化算法和其概念的严格定义，建立了用于算法描述和实现的ＥＦＳＭ向图概念。同时选择了一个较能完全体现ＥＦＳＭ特点的Ｑ．９２１协议讲述了其实现