Electro-chemical mechanical polishing of silicon carbide

In an effort to improve the silicon carbide (SiC) substrate surface, a new electro-chemical mechanical polishing (ECMP) technique was developed. This work focused on the Si-terminated 4H-SiC (0001) substrates cut 8° off-axis toward 〈1120〉. Hydrogen peroxide (H₂O₂) and potassium nitrate (KNO₃) were used as the electrolytes while using colloidal silica slurry as the polishing medium for removal of the oxide. The current density during the polishing was varied from 10 μA/cm² to over 20 mA/cm². Even though a high polishing rate can be achieved using high current density, the oxidation rate and the oxide removal rate need to be properly balanced to get a smooth surface after polishing. A two-step ECMP process was developed, which allows us to separately control the anodic oxidation and removal of formed oxide. The optimum surface can be achieved by properly controlling the anodic oxidation current as well as the polishing rate. At higher current flow (>20 mA/cm²), the final surface was rough, whereas a smoother surface was obtained when the current density was in the vicinity of 1 mA/cm². The surface morphology of the as-received wafer, fine diamond slurry (0.1 μm) polished wafer, and EMCP polished wafer were studied by high-resolution atomic force microscopy (AFM).     

A novel method for etching trenches in silicon carbide

In this paper, a novel trench etching technique for silicon carbide is described. In this technique, ion implantation is used to first create an amorphous silicon carbide region. The amorphous layer is then etched away by wet chemical etching. Trenches of 0.3 to 0.8 μ have been obtained using a single implantaion/etching step. It has been demonstrated that deeper trenches can be obtained by repeating the implantation/etching step with platinum as a masking material. The etched surface was found to be smooth when compared with reactive ion etched surfaces reported for silicon carbide.     

Surface morphology of silicon carbide epitaxial films

Silicon carbide (SiC) semiconductor technology has been advancing rapidly, but there are numerous crystal growth problems that need to be solved before SiC can reach its full potential. Among these problems is a need for an improvement in the surface morphology of epitaxial films that are grown to produce device structures. Because of advantageous electrical properties, SiC development is shifting from the 6H to the 4H polytype. In this study of both 6H and 4H-SiC epilayers, atomic force microscopy and other techniques were used to characterize SiC epilayer surface morphology. Observed features included isolated growth pits a few micrometers in size in both polytypes and triangles (in 4H only) approximately 50 um in size for epilayers 3 um in thickness. Also observed in some epilayers were large steps with heights greater than 20 nm. We found that there are significant differences between the morphology of 6H and 4H epilayers grown under identical conditions. We were able to improve surface morphology by avoiding conditions that lead to excess silicon during the initial startup of the growth process. However, the observed morphological defect density in both 6H and 4H epilayers was still the order of 10⁴ cm^-2 and varied widely from run to run. As expected, we found that morphological defects in the SiC substrates play a role in the formation of some epilayer surface features.     

Preparation of ultrasmooth and defect-free 4H-SiC(0001) surfaces by elastic emission machining

In this work, elastic emission machining (EEM), which is a precise surface-preparation technique using chemical reactions between the surfaces of work and fine powder particles, is applied to the flattening 4H-SiC (0001) surface. Prepared surfaces are observed and characterized by optical interferometry, atomic force microscopy (AFM), and low-energy electron diffraction (LEED). The obtained images show that the processed surface has atomic-level flatness, and the subsurface damage and surface scratches of the preprocessed surface are almost entirely removed.     

Reactive ion etching of trenches in 6H-SiC

In this paper, we report the reactive ion etching (RIE) of trenches in 6H-silicon carbide using SF₆/O₂. The plasma parameters: etchant composition, gas flow rate, chamber pressure, and radio frequency power were optimized to obtain a maximum etch rate of 360Å/min. The etch rate of SiC was found to exhibit a direct correlation with the dc self bias except when the O₂ percentage was varied. Trenches were fabricated using the optimized conditions. It was found that the trench surface was extremely rough due to the aluminum micromasking effect. To overcome this effect, a Teflon^TM sheet was used to cover the cathode during the experiment. The trenches fabricated using this modification were found to have smooth etched surfaces and sidewalls. The angle of anisotropy of these trenches was approximately 80° which is suitable for device applications.     

Surface roughening in ion implanted 4H-silicon carbide

Silicon carbide (SiC) devices have the potential to yield new components with functional capabilities that far exceed components based on silicon devices. Selective doping of SiC by ion implantation is an important fabrication technology that must be completely understood if SiC devices are to achieve their potential. One major problem with ion implantation into SiC is the surface roughening that results from annealing SiC at the high temperatures which are needed to activate implanted acceptor ions, boron or aluminum. This paper examines the causes and possible solutions to surface roughening of implanted and annealed 4H-SiC. Samples consisting of n-type epilayers (5 × 10¹⁵ cm⁻³, 4 μm thick) on 4H-SiC substrates were implanted with B or Al to a total dose of 4 × 10¹⁴ cm⁻² or 2 × 10¹⁵ cm⁻², respectively. Roughness measurements were made using atomic force microscopy. From the variation of root mean square (rms) roughness with annealing temperature, apparent activation energies for roughening following implantation with Al and B were 1.1 and 2.2 eV, respectively, when annealed in argon. Time-dependent activation and surface morphology analyses show a sublinear dependence of implant activation on time; activation percentages after a 5 min anneal following boron implantation are about a factor of two less than after a 40 min anneal. The rms surface roughness remained relatively constant with time for anneals in argon at 1750°C. Roughness values at this temperature were approximately 8.0 nm. Annealing experiments performed in different ambients demonstrated the benefits of using silane to maintain good surface morphology. Roughnesses were 1.0 nm (rms) when boron or aluminum implants were annealed in silane at 1700°C, but were about 8 and 11 nm for B and Al, respectively, when annealed in argon at the same temperature.     

A review of manufacturing technologies for silicon carbide superjunction devices

Superjunction technology is believed to reach the optimal specific on-resistance and breakdown voltage trade-off.It has become a mainstream technology in silicon high-voltage metal oxide semiconductor field effect transistor devices.Numer-ous efforts have been conducted to employ the same concept in silicon carbide devices.These works are summarized here.     

Chemical contribution of oxygen to silicon carbide plasma etching kinetics in a distributed electron cyclotron resonance (DECR) reactor

This paper deals with the influence of the oxygen additive on the fluorinated plasma etch rate of silicon carbide. The assumption according to which the oxygen has a direct contribution to silicon carbide etching, by chemical reaction with carbon atoms, is generally reported in the literature. Our etching experiments are performed in a distributed electron cyclotron resonance reactor, on both 3C- and 6H-SiC. An SF₆/O₂ gas mixture (avoiding the presence of C species in the plasma), fluorine saturation conditions and constant ion bombardment energy and flux are used, allowing the study of O₂ contribution exclusively. In these conditions, our results demonstrate the neutrality of O₂ on SiC etching mechanisms. These results will be discussed reinfored both by several other experimental observations.     

A comparative study of micropipe decoration and counting in conductive and semi-insulating silicon carbide wafers

Micropipes are considered to be one of the most serious defects in silicon carbide (SiC) wafers affecting device yield. Developing a method to count and map micropipes accurately has been a challenging task. In this study, the different etching behavior of conductive and semi-insulating wafers in molten potassium oxide (KOH) is compared. Micropipes and closed-core screw dislocations exhibit different morphology after etching and can be easily distinguished with a polishing process. Based on a new sample preparation procedure and a digital imaging technique, a novel method of efficiently and reliably mapping and counting micropipes in both conductive and semi-insulating SiC wafers is developed.     

Temperature measurement in a silicon carbide light emitting diode by raman scattering

Raman spectra of the transverse-optic phonon mode from a light-emitting layer of a SiC diode have been measured. The phonon peak broadens and shifts to lower frequency with the rise of temperature when the injected current is increased. The frequency shift was compared with a result for bulk reference measured separately at various temperatures. We found that the temperature of the light-emitting layer reached 350°C at a current density of ∼200 A/cm².     

Effect of hydrogen etching and subsequent sacrificial thermal oxidation on morphology and composition of 4H-SiC surfaces

The effects of solvent cleaning, hydrogen etching, and additional oxidation treatment of 4H-SiC off-axis surfaces were investigated. The morphology of the resulting surfaces was observed by atomic force microscopy (AFM), and the chemical composition was studied by x-ray photoelectron spectroscopy (XPS). It is confirmed that simple cleaning and hydrofluoric acid (HF) etching procedures do not yield smooth surfaces, although the surfaces show mainly SiC-like bonds. High-temperature hydrogen etching can effectively remove polishing scratches, leading to a very smooth morphology, but it leaves some residual graphitic-bound carbon behind. It is shown that a subsequent oxidation step not only removes residual graphite on the hydrogen-etched surface but also produces the same chemical composition on all treated surfaces.     

Nanoscale characterization of the silicon dioxide-silicon carbide interface using elemental mapping by energy-filtered transmission electron microscopy

Energy-filtered transmission electron microscopy (EFTEM) was used to study 6H-SiC/SiO₂ interfaces produced by thermal oxidation as a function of the oxidation conditions. Elemental maps of C and Si were used to calculate C-to-Si concentration profiles across the interfaces. Enhanced C/Si concentrations (up to ∼ 35%) were observed at distinct regions in samples oxidized at 1100°C for 4 h in a wet ambient. The data from a number of randomly selected regions indicate that re-oxidation at 950°C for 3 h significantly reduced, but did not eliminate, the amount of excess interfacial carbon.     

铜辅助化学腐蚀条件对多孔硅的影响

以铜(Cu)作为催化剂,采用两步化学腐蚀法成功制 备了微纳米多孔硅(PS)。本文方法成本低廉、操 作简易。系统研究了腐蚀液中H₂O₂浓度、Si衬底掺杂浓度、腐蚀液温度和腐 蚀时间对PS表 面形貌和腐蚀深度的影响,并得到最佳制备参数。高、低掺Si衬底所采用的最佳配比腐蚀液 中的H₂O₂浓度分 别达到0.70mol/L和0.24mol/L。在 25℃腐蚀液中,腐蚀2h得到约200nm深的纳米级孔洞 ,其表面反射率在 宽波段内降低到5%以下;而在50℃腐蚀液中,经过2～ 4h的腐蚀,可得到14～41μm深的结构稳定的微纳 米级孔洞。文中还对Cu辅助腐蚀与其他金属辅助腐蚀(MACE)作了对比,分析了Cu辅助腐蚀获 得锥状孔洞的原因和机理。     

A silicon carbide LOCOS process using enhanced thermal oxidation by argon implantation

A process is described for creating local oxidation of silicon structure (LOCOS) structures in silicon carbide using enhanced thermal oxidation by argon implantation. Thicker oxides were created in selective regions by using multiple energy argon implants at a dose of 1 × 10¹⁵ cm⁻² prior to thermal oxidation. Atomic force microscopy was used to analyze the fabricated LOCOS structure.     

Comparison of diamond wire cut and silicon carbide slurry processed silicon wafer surfaces after acidic texturisation

Our work focuses on the acidic etching of silicon wafers, cut via diamond wire (DW) or silicon carbide slurry process (SP). The DW and SP as-cut wafer surface structures have a significant impact on the evolution of the two resultant and different etched morphologies. The time-dependent development of the surface morphology for mono- and multi-crystalline wafers is compared and analyzed via etch rates, reflectivity measurements and confocal microscopy. The as-cut structure of the differently sawn wafers defines a template where the etch attack preferentially occurs and predetermines the texturisation of the etched surface. Based on the experimental results it is possible to lower the reflectivity of the SP-sawn wafers by varying the acidic mixture. On the contrary, the DW-sawn wafers obtain only a small enlargement of the folded surface area during acidic texturisation and no influence of different acidic etch solutions on the reflectivity values was found. To create homogeneously texturized DW-sawn wafers of low reflectivity, an adaptation of the sawing process as well as the development of new etchants and new etch conditions is necessary.     

Atomic scale engineering of nanostructures at silicon carbide surfaces

The atomic scale ordering and properties of cubic silicon carbide surfaces are investigated by room and high-temperature scanning tunneling microscopy. In this review, we will focus on the Si-terminated β-SiC(100) surfaces only. Self-formation of Si atomic lines and dimer vacancy chains on the β-SiC(100) surface is taking place at the phase transition between the 3×2 (Si-rich) and c(4×2) surface reconstructions. Using a rigorous protocol in surface preparation, it is possible to build very long, very straight and defect free Si atomic lines, forming a very large superlattice of massively parallel lines. These self-organized atomic lines are driven by stress. They have unprecedented characteristics with the highest thermal stability ever achieved for nanostructures on a surface (900 °C) and the longest atomic lines ever built on a surface (micrometer scale long). Investigating their dynamics, we learn that their dismantling at high-temperature results from collective and individual mechanisms including one-by-one dimer removal. Overall, this is a model system especially suitable for nanophysics and nanotechnologies.     

Mixed phase silicon thin films grown at high rate using 60 MHz assisted VHF-PECVD technique

Mixed phase amorphous and nanocrystalline silicon (a-Si:H and nc-Si:H) thin films were deposited by VHF-PECVD (60 MHz) using Argon (Ar) as the diluent of silane. These amorphous and crystalline silicon thin films were deposited by varying the argon dilution (f_Ar) from 10–97.5% while keeping other process parameters constant. The effects of argon dilution on deposition rate, structural and optical properties of micro/nanocrystalline silicon thin films are studied. It has been observed that the films deposited from f_Ar 10–70% showed the deposition rate >20 Å/s with the highest deposition rate achieved of ~25 Å/s. Structural characterization has been performed by micro-Raman analysis and Atomic force microscopy. Raman shift towards higher wave number (515 cm⁻¹) with increase of f_Ar indicates variation in crystallinity of silicon films. HRTEM studies revealed the distribution of grain size and the degree of crystallinity. Optical absorption spectroscopy confirmed the increase in band gap of the materials from 1.5 to 2.1 eV.     

Time-dependent degradation of AlGaN/GaN heterostructures grown on silicon carbide

The AlGaN/GaN heterostructure field-effect transistors (HFETs) were grown on 4H-SiC substrates by metal-organic chemical-vapor deposition (MOCVD) with a range of Al compositions (30–35%) and AlGaN barrier thicknesses. Films with higher strains exhibited a time-dependent degradation of the two-dimensional electron gas (2DEG) that varied from days to weeks. Atomic force microscopy (AFM) measurements of the degraded films revealed a hexagonal cracking pattern with an increase in the medium-scale surface roughness. The localized strain relaxation of AlGaN barriers and increased roughness of the AlGaN/GaN interface and AlGaN surface result in a broad shoulder at the lower angle of the AlGaN peak and a loss of satellite fringes in the (0006) reflection x-ray diffraction (XRD) curve. This degradation raises serious questions with regard to reliability and survivability of AlGaN HFETs and may complicate device fabrication.     

A simple method for high yield fabrication of sharp silicon tips

A simple, high yield, method for the fabrication of sharp silicon tips is described. A triangular etch mask design is used to ensure that the tip forms with a single point. An anisotropic wet etch gives rise to a tip that continues to “self-sharpen” after the etch mask is released. The tip geometry comprises three converging {1 1 3} planes towards the apex with {3 1 3} planes forming at the base. The apex of each tip typically has a radius of curvature of <5 nm, which can be reduced to <2 nm by a subsequent oxide sharpening process. Tips of this kind have been successfully integrated into the fabrication of atomic force microscopy probes.