An analytic method to determine GaAs FET parasitic inductances anddrain resistance under active bias conditions

An analytic technique to determine the parasitic inductances, source resistance, and drain resistance of the FET equivalent circuit is presented in this paper. The method exploits the frequency dependence of the extracted circuit parameters to determine the parasitic inductances and drain resistance from S-parameters measured over frequency for one active bias condition. Given a value for the parasitic gate resistance R _g, all of the other equivalent-circuit parameters are uniquely extracted. The method is fast and robust, making it suitable for in-line statistical process tracking, as well as device modeling. A process tracking example for a 12-wafer 1864-device sample and FET modeling results up to 40 GHz are also presented     

Simple method to determine the main Gunn domain parameters

A simple analytical method to determine the maximum field, outside field and excess voltage of a stable domain is put forward for any values of the carrier concentration, sample length and bias. This method provides good agreement with the exact solutions, for both stable-domain and transient processes in Gunn diodes.     

An interconnect model for arbitrary terminations based on scattering parameters

An interconnect model, using the equivalent circuits derived from either the recursive or the nonrecursive evaluations of the convolution integral, is presented to show how arbitrary terminations can be efficiently handled in the high-frequency simulation environment. To achieve robustness in the recursive case, the impulse response is partitioned and Prony's method is applied to extract the exponentials. With the experimental data provided by scattering parameters, the model can be formulated for nonuniform lines, MCM connectors, etc. The equivalent circuit comprises of physically realizable elements available in general-purpose circuit simulators such as SPICE, and simulation performance for several case studies shows the applicability of this model to high-frequency circuit simulation and design.     

An improved method to determine MOSFET channel length

An accurate and simple method to determine channel length and parasitic drain/source series resistance is presented. This method is based on measured data of two identical devices with different channel lengths. Because of its simplicity, the technique is suitable for use in automatic parameter testing systems.     

一种高精度解析提取太阳电池参数的新方法

基于太阳电池光生电流远大于反向饱和电流、并 联电阻远大于串联电阻以及光生电流 近似等于负的短路电流3个边界条件,结合太阳电池在短路点、开路点和最大功率点处的极值 表述, 提出了一种解析求解太阳电池光生电流、反向饱和电流、理想因子、并联电阻和串联电阻5个电性参 数的方法,并研究了方法的特点。通过与文献实验数据的对比表明,本文方法不仅具有正确 性,而且 适用于各种条件下的各种类型电池;通过实验表明,本文方法具有较高的计算精 度和速度,误差在2%以下,时间小于0.2s。     

A new extraction method to determine bias-dependent source seriesresistance in GaAs FET's

A new method is proposed to determine bias-dependent source resistances for GaAs field-effect transistors (FET's). This method, which is a cold-FET measurement technique, utilizes the relations between the real part of the two-port impedances transformed from the measured S-parameters and their algebraic derivatives. It is based on the fact that the algebraic derivatives of the two-port resistances result in the simple form at the normal cold-FET condition. A bias-independent gate resistance is extracted at the pinched-off cold-FET condition to fulfill necessary and sufficient conditions in extraction. The proposed method is a direct measurement because only algebraic calculation is required, and it is general enough to need only one assumption of the laterally symmetric channel-doping profile. The deleterious results of dispersion (frequency dependence) and negative value in source resistances at the pinched-off cold-FET condition are explained by the effects of the leakage current and the on-wafer pad parasitics, respectively. The problem of deviation of α₂₁ and α₁₂ from 0.5 at the normal cold-FET condition is also resolved by deembedding the on-wafer pad parasitics. This method allows one to extract bias-dependent source resistances for GaAs FET's     

An efficient approach for power delivery network design with closed-form expressions for parasitic interconnect inductances

Investigation of a dc power delivery network, consisting of a multilayer PCB using area fills for power and return, involves the distributed behavior of the power/ground planes and the parasitics associated with the lumped components mounted on it. Full-wave methods are often employed to study the power integrity problem. While full-wave methods can be accurate, they are time and memory consuming. The cavity model of a rectangular structure has previously been employed to efficiently analyze the simultaneous switching noise (SSN) in the power distribution network. However, a large number of modes in the cavity model are needed to accurately simulate the impedance associated with the vias, leading to computational inefficiency. A fast approach is detailed herein to accelerate calculation of the summation associated with the higher-order modes. Closed-form expressions for the parasitics associated with the interconnects of the decoupling capacitors are also introduced. Combining the fast calculation of the cavity models of regularly shaped planar circuits, a segmentation method, and closed-form expressions for the parasitics, an efficient approach is proposed herein to analyze an arbitrary shaped power distribution network. While it may take many hours for a full-wave method to do a single simulation, the proposed method can generally perform the simulation with good accuracy in several minutes. Another advantage of the proposed method is that a SPICE equivalent circuit of the power distribution network can be derived. This allows both frequency and transient responses to be done with SPICE simulation.     

An on-chip, interconnect capacitance characterization method withsub-femto-farad resolution

A simple, accurate method of measuring interconnect capacitances is presented. The test structure has excellent resolution, needs only DC measurements, and is compact enough for scribe-line implementation. These qualities make it suitable for measurement-based, interconnect capacitance characterization in a comparable fashion to current characterization efforts for MOSFET devices. The entire characterization scheme is demonstrated for a production 0.5 μm, three-level metal technology. The method not only provides an accurate assessment of actual capacitance variation but provides valuable feedback on the variability of physical parameters such as interlevel dielectric (ILD) thickness and drawn width reductions for process control as well     

An approach to determine small-signal model parameters for InP-based heterojunction bipolar transistors

A new method for the extraction of the small-signal model parameters of InP-based heterojunction bipolar transistors (HBT) is proposed. The approach is based on the combination of the analytical and optimization technology. The initial values of the parasitic pad capacitances are extracted by using a set of closed-form expressions derived from cutoff mode S-parameters without any test structure, and the intrinsic elements determined by using the analytical method are described as functions of the parasitic elements. An advanced design system is then used to optimize only the parasitic parameters with very small dispersion of initial values. Good agreement is obtained between simulated and measured results for an InP HBT with 5/spl times/5 /spl mu/m/sup 2/ emitter area over a wide range of bias points up to 40 GHz.     

Optimization study of VLSI interconnect parameters

In this paper, we present the results of optimizing interconnect parameters to satisfy chip-level targets in future device generations. The optimization approach used is based on existing system-level models and can optimize the number of wire levels, speed, chip size, and power in sequence, with the optimization variables being all interconnect parameters such as pitches, thicknesses, etc. We also study the trade-offs resulting from various interconnect process limitations and choices. The findings of this study, in brief, are: 1) while the thickness of the interlayer dielectric (ILD) can be scaled without adverse effects on speed so that the hole aspect ratio is held constant at about 3.0 across generations, it is important to provide extremely thick ILD films in excess of 4 pm in the upper wire levels, 2) while the maximum wire thickness can be safely held to about 2 μm in the upper wire levels, extremely thin wires of less than 0.1 pm thickness will soon be needed in the lower wire levels to reduce capacitance, 3) while wire resistivity reduction is desirable it is much more important to reduce the ILD dielectric constant aggressively, and 4) chip size constraints can impact the speed extremely and need to considered carefully. These results can be used to construct an optimal interconnect technology roadmap and can be an invaluable aid in guiding interconnect process development     

110 GHz铟磷异质结双极晶体管小信号模型参数提取方法

介绍了一种可以用于频率高达110GHz的InP基HBT小信号模型模型参数提取方法, 并且在所提出的模型中考虑了基极馈线的趋肤效应.该方法将直接提取和优化技术相结合, 将本征参数描述为寄生电阻的系列函数进行后续优化.实验结果表明在2～110GHz频率范围内S参数吻合很好.     

Material electromagnetic parameters extraction using SVM method

The method extracting the electromagnetic parameters from scattering coefficients was studied in this paper. The Support Vector Machine (SVM) method is used to solve the inverse problem of parameters extraction. The mapping relationship is set up by calculating a large number of S parameters from the samples with different permittivity by using transmission line theory. The simulated data set is used as training data set for SVM. After the training, the SVM is used to predict the permittivity of material from the scattering coefficients.     

一种对三维芯片中硅通孔进行完整建模与寄生参数提取的有效方法

针对三维芯片中硅通孔（through-silicon via, TSV）的准确电学建模问题,本文提出了一种电阻电容（RC）电路模型以及相应的有效参数提取技术。该电路模型同时考虑了半导体效应与静电场影响,适合于低频与中频的电路信号范围。该方法采用一种基于悬浮随机行走（floating random walk, FRW）算法的静电场电容提取技术,然后将它与刻画半导体效应的MOS电容结合,形成等效电路模型。与Synopsys公司软件Sdevice所采用的对静电场/半导体效应进行完整仿真的方法相比,本文方法计算效率更高,并且也能处理一般的TSV电路版图。对多个含TSV的结构进行了计算实验,结果验证了本文方法在从10KHz到1GHz频率范围内的建模准确性,也显示出它相比Sdevice方法最多有47倍的加速比。     

New method for extraction of MOSFET parameters

A new method for the extraction of the MOSFET parameters is presented in this letter. The method, which relies on combining drain current and output conductance characteristics, enables reliable values of the threshold voltage V_th, mobility μ₀ and the mobility attenuation coefficient &thetas; to be obtained. Extracted results have been shown in good agreement with that of the second-derivative method, showing the validity of our presented method     

An image feature-based method to efficiently determine inter-coding depth in HEVC

The quad-tree based picture partition scheme in High Efficiency Video Coding (HEVC) results in a more substantial increase in computational complexity than those incurred by its predecessor video coding standards because of the need in this scheme to determine the best coding unit (CU) partitions. In this paper, we propose a method to effectively reduce the computational complexity of inter-prediction coding in the HEVC standard. The relative displacement of the largest coding unit (LCU) at the corresponding position between adjacent frames is tested through optical flow (motion estimation). The texture intensity of the LCU at the given time is tested if the condition that determines the coding depth in advance cannot be satisfied. The depth of the coding unit (CU) can be determined in advance beyond the xCompressCU function by using our proposed method, which does not require the calculation of the rate-distortion (RD) cost for each level of depth, and thus reduces the circular traversal times of the xCompressCU function. Experimental results proved that our proposed method is effective, as it reduced the computational complexity of an encoder by 53.2% on average, and had a slight influence on coding performance.     

An efficient structural approach to board interconnect diagnosis

In this paper we present an efficient structural approach for diagnosing board interconnects using boundary-scan. Whereas existing diagnosis approaches assume only wired-AND or wired-OR bridging fault model, we consider a more complex bridging short fault model in a CMOS circuit environment. The diagnostic test set is generated on the basis of graph theoretic technique and the adjacency fault model is adopted. By using the structural information of the wiring layout, the test length can be reduced. Both one-step and two-step diagnosis algorithms are given. They guarantee the complete diagnosis of multiple interconnect faults with no aliasing or confounding. The algorithms have been evaluated by simulation on several benchmark layouts and randomly generated layouts. Simulation results show that more than 50% reduction in the number of tests can be achieved for two-step diagnosis when the fault rate is very small, such as in a matured product line. This can significantly save the diagnosis cost for boundary-scan testing.     

A new method to extract diode parameters under the presence of parasitic series and shunt resistance

A simple method is presented for extracting the diode ideality factor and saturation current in the presence of significant series and parallel parasitic resistances. Additionally, the values of both resistances can be determined. The method is compared to conventional direct optimization, which fails when both resistances are simultaneously significant.     

An efficient formulation for substrate parasitic extraction accounting for nonuniform current distribution

In this paper, a new formulation for the extraction of substrate parasitics is derived that can account for the nonuniform current distribution on contacts without contact subdivision. This method is orders of magnitude faster than the original Green's function method. The speedup is achieved by a significantly reduced matrix size combined with the application of the discrete sine transform. The method is accurate, and is well suited for large problems.     

An influence of parasitic parameters on electromagnetic disturbance emission in voltage converters

In this paper it is estimated an influence of parasitic parameters of elements in converters of different topologies on a spectral components of conducted electromagnetic interference. Scalability of obtained results allows to estimate expected levels of electromagnetic interferences (EMI) from considered converters types, and hence, develop more efficient interference-suppression filters (ISF) for switching-type power supplies (STPS) with less development cost. Results are obtained for frequency band of 0–30 MHz.     

Simple method to determine microwave phase

The Kramers-Kronig transform is used to calculate the phase of a reflection coefficient once the frequency dependence of its magnitude is measured. The calculated values agree quite satisfactorily with the measured results, thus making it feasible to use this method in practice to determine microwave phase.