Operation Principles of 0.18-$muhboxm$Four-Transistor CMOS Image Pixels With a Nonfully Depleted Pinned Photodiode

The operation principles of the four-transistor (4-TR) pixel CMOS image sensor, fabricated by 0.18-mum technology, were investigated by pixel-level characterization utilizing a single-pixel test pattern. It was found that the pixel's dark current level is strongly influenced by the gate bias (V_TX(on)) of the transfer (TX) transistor at a fixed supply voltage (V_DD). The largest dark current occurred at a conventional bias condition of V_TX(on)=V_DD=2.5V, but the dark current level was reduced by less than one-third at V_TX(on)=2.1V without degrading the pixel's charge transfer capabilities. Attributed to the dark current reduction, the fixed-pattern noise (FPN) of pixel was also decreased by up to 13.3 dB. These improvements can be explained by the more effective reset of pinned photodiode (PPD) at V_TX(on)=2.1V, especially in the pixel with V_DD of 2.5 V or lower in which the full depletion of PPD becomes more and more difficult. In this bias condition, namely nonfully depletion PPD condition, the TX transistor was proven to operate in the "deepest depletion" mode by effectively suppressing the electron injection from floating diffusion node to channel. Moreover, various driving signals to the TX transistor were applied to do more detailed physical analysis of the pixel operation. Since the dark current and FPN are main bottlenecks in most CMOS image sensors, the proposed method is expected to efficiently improve the performance of 4-TR CMOS image pixels under 2.5 V or lower operational voltages     

Application of Plasma-Doping (PLAD) Technique to Reduce Dark Current of CMOS Image Sensors

Plasma doping (PLAD) was applied to reduce the dark current of CMOS image sensor (CIS), for the first time. PLAD was employed around shallow trench isolation (STI) to screen the defective sidewalls and edges of STI from the depletion region of photodiode. This technique can provide not only shallow but also conformal doping around the STI, making it a suitable doping technique for pinning purposes for CISs with sub-2-mum pixel pitch. The measured results show that temporal noise and dark signal deviation as well as dark level decrease     

Investigation of a Sequential Three-Dimensional Process for Back-Illuminated CMOS Image Sensors With Miniaturized Pixels

A new 3-D CMOS image sensor architecture is presented as a potential candidate for submicrometer pixels. To overcome the scaling challenge related to miniaturized pixel design rules, far beyond traditional 3-D stacking alignment capabilities, a sequential construction is applied. This paper gives a technical overview of this 3-D scheme and validates a part of its building blocks. As a consequence of a sequential process, the thermal budget is limited to ensure bottom device immunity. Subsequently, high-quality SOI film transfer above the first layer by direct bonding and etch back is demonstrated. Finally, the low-temperature processing of HfO₂/TiN fully depleted silicon-on-insulator readout transistors is detailed and evaluated from a low frequency noise point of view.     

Statistical Noise Analysis of CMOS Image Sensors in Dark Condition

The statistical noise analysis of the CMOS image sensors in the dark condition has been performed with a newly developed 3-D technology computer-aided design framework. The noise histograms of the correlated double sampling output, due to the random distribution of the oxide traps in the source follower MOSFET, have been evaluated. In this framework, the random telegraph signal noise is accurately characterized in the device level, and the numerical efficiency for the statistical analysis is achieved by employing the Green's function method based on the drift-diffusion model. As an application, one million samples of the source follower MOSFET have been simulated, and the effect of the channel width, the channel length, and the oxide trap density on the noise histogram has been investigated.     

CMOS图像传感器的研究新进展

随着超大规模集成技术的发展,CMOS图像传感器显示出了强劲的发展趋势.简要介绍了CMOS图像传感器的发展历程,在分析CCD和CMOS图像传感器工作原理的基础上,对比了CMOS图像传感器与CCD的特点.重点描述了国外CMOS图像传感器的最新商业化产品状况,同时给出了一些产品的性能参数,最后展望了CMOS图像传感器的未来发展趋势.     

Optimum Design of Conversion Gain and Full Well Capacity in CMOS Image Sensor With Lateral Overflow Integration Capacitor

An optimum design theory to clarify a possible limit of achieving both high conversion gain (CG) and full well capacity (FWC) at the same time in a CMOS image sensor with a lateral overflow integration capacitor (LOFIC) in a pixel is discussed. The possible limit of both high CG and high FWC is theoretically derived from a signal-to-noise-ratio (SNR) formula at a switching point from a low light signal (S1) to a bright one (S2). Based on this theory, a 1/4-in VGA-format 5.6-mum-pixel-pitch CMOS image sensor has been fabricated through a 0.18-mum 2P3M CMOS technology. A high-quality wide-dynamic-range image sensing has been demonstrated with no significant visible noise, achieving over 32 dB of SNR for an 18% gray card.     

用于百万像素级CMOS图像传感器的10位50MS/s流水线ADC设计

高速高精度ADC是CMOS图像传感器中的重要部分。随着工艺的进步,低功耗设计已经吸引了很多人的注意。为了在没有降低表现的情况下控制功耗,在本设计采用相同结构放大器共用相同的偏置电路技术,并且采用了共源共栅补偿技术来降低功耗。噪声和不匹配也是流水线ADC中重要的误差源,因此采用了Matlab对这两者进行了仔细的计算和系统仿真。在本文中,提出了一个10位50MS/s的 流水线ADC核心。这个设计可以用于大像素规模的CMOS图像传感器。本设计在表现和功耗上取得了很好的平衡。     

用于百万像素级CMOS图像传感器的10位50MS/s流水线ADC设计

噪声和不匹配是流水线ADC中的重要误差源,采用Matlab软件对它们进行了计算和系统仿真.为了在没有降低表现的情况下控制功耗,采用了相同结构放大器共用相同的偏置电路技术,并且采用了共源共栅补偿技术来降低功耗.还设计并且测试了一个可用于大像素规模CMOS图像传感器系统的10位50MS/s流水线ADC原型.根据测试结果,当采样频率为50MHz时功耗仅为42mW,SINAD为45.69dB.设计在表现和功耗上取得了很好的平衡.     

CMOS亚阈偏置恒流源的分析与设计

由于IC芯片设计普遍采用全局偏置技术,偏置电路的稳定性对整个电路的性能有较大影响。文中利用MOS管工作在亚阈值区的偏置判断条件,分析了一种基于VT的工作在亚阈值区的偏置电流源,能够满足提供较小工作电流、低功耗的要求,同时对电源变化敏感度极低,在电源电压0.7 V~5 V变化时输出电流仅变化不到0.9%。整个电路采用CSMC 0.6μm双层多晶硅双层金属标准工艺实现,采用Cadence Spectre进行模拟仿真,仿真结果证明了该电流源具有低功耗和高电源抑制比特性。     

动态图像显示屏虚拟组合像素技术及其算法实现

针对图像信息显示屏的动态图像显示效果,提出了一种全新的具有虚拟组合的像素排列方法,按照该排列方法,1个具有M×N个物理像素的动态显示屏可以得到约8×M×N分辨率的显示效果.通过实验研究还提出了一种算法及其逻辑结构,能将计算机输出的图像原始数据根据相应算法予以处理后,得到与屏幕上相对应像素的组合值.显示屏数据的提取和处理是流水线结构,处理是实时的,且通过此算法处理后图像带宽减少了2/3,图像的显示效果提高了近8倍.     

新型GaAs/AlGaAs量子阱红外探测器暗电流特性

对基于GaAs/AlGaAs系子带间吸收的一种新型量子阱红外探测器,采用Poisson方程和Schrodinger方程,计算了新器件结构的能带结构、电子分布特性,在此基础上采用热离子发射、热辅助遂穿模型对器件的暗电流特性进行了模拟,计算结果与器件实测的暗电流特性吻合得很好,说明热离子发射、热辅助遂穿机制是形成器件暗电流的主要构成机制,增加垒高、降低阱中掺杂浓度及降低工作温度是抑制器件暗电流的主要途径,计算结果对进一步优化器件的设计将起到重要的理论指导作用．     

新型GaAs/AlGaAs量子阱红外探测器暗电流特性

对基于 Ga As/ Al Ga As系子带间吸收的一种新型量子阱红外探测器 ,采用 Poisson方程和 Schrodinger方程 ,计算了新器件结构的能带结构、电子分布特性 ,在此基础上采用热离子发射、热辅助遂穿模型对器件的暗电流特性进行了模拟 ,计算结果与器件实测的暗电流特性吻合得很好 ,说明热离子发射、热辅助遂穿机制是形成器件暗电流的主要构成机制 ,增加垒高、降低阱中掺杂浓度及降低工作温度是抑制器件暗电流的主要途径 ,计算结果对进一步优化器件的设计将起到重要的理论指导作用 .     

Analysis of Dark Signal Degradation Caused by 1 MeV Neutron Irradiation on Backside-Illuminated CMOS Image Sensors

The purpose of this work is to investigate the influence of the epitaxial layer thickness of Backside-illuminated CMOS image sensors (BSI CISs) on dark signal b...     

CMOS图像传感器光电二极管模型

为了更好的对CMOS图像传感器中光电二极管的光电转换物理现象进行研究,需要建立正确合适的光电二极管数学物理模型。通过少数载流子稳态连续方程建立光电二极管的一维物理模型,求解方程后,代入参数在MATLAB中对两层结构的n+/p-sub型和n-well/p-sub型,以及三层结构的p+/n-well/p-sub型二极管进行了计算模拟,得到了3种二极管响应率与波长的关系曲线。最后将结果与实际值进行了对比分析,确认了模型能够在一定程度上反映实际的物理情况。     

MOVCD生长GaAs/AlGaAs量子阱红外探测器暗电流特性研究

用金属有机物化学气相沉积法(MOCVD)生长了GaAs/AlGaAs量子阱材料,分别制备了300μm×300μm台面,峰值波长8.5μm,外电极压焊点面积80μm×80μm,内电极压焊点面积20μm×20μm的单元测试样品。用变温液氦制冷机测试系统对两个样品进行50～300K的变温测试,分析了器件在不同偏压条件下的暗电流特性。发现该量子阱红外探测器的背景限温度为50K。不同生长次序中GaAs与AlGaAs界面的不对称性,以及掺杂元素的扩散导致了正负偏压下的I/V曲线呈不对成性。探测器电极压焊点面积大小与位置的不同对暗电流有一定的影响。     

TDI图像传感器横向抗晕栅极电压与满阱容量关系研究

时间延时积分CMOS图像传感器(TDI-CIS)具有优良的微光探测能力,可应用于航空探测及卫星遥感等领域。然而,在入射光强较强时,TDI-CIS容易出现光晕(Blooming)现象,影响观测效果。首先分析了光晕产生的机理;然后基于两种传统的抗晕结构,设计出一种具有沿垂直方向布局的长方形横向抗晕栅的TDI-CIS;通过成像实验发现横向抗晕栅极电压与抗晕效果及满阱容量(FWC)之间呈负相关关系;最后通过实验得到所设计TDI-CIS的最优抗晕栅极电压值为2.1V。     

A CMOS Image Processing Sensor for the Detection of Image Features

A compact CMOS vision sensor for the detection of higher level image features, such as corners, junctions (T-, X-, Y-type) and linestops, is presented. The on-chip detection of these features significantly reduces the data amount and hence facilitates the subsequent processing of pattern recognition. The sensor performs a series of template matching operations in an analog/digital mixed mode for various kinds of image filtering operations including thinning, orientation decomposition, error correction, set operations, and others. The analog operations are done in the current domain. A design procedure, based on the formulation of the transistor mismatch, is applied to fulfill both accuracy and speed requirements. The architecture resembles a CNN-UM that can be programmed by a 30-bit word. The results of an experimental 16 × 16 pixel chip demonstrate that the sensor is able to detect features at high speed due to the pixel-parallel operation. Over 270 individual processing operations are performed in about 54 μsec. Masatoshi Nishimura was born in 1962 in Japan. He received his B.S. degree in mathematical engineering and information physics from the University of Tokyo in 1984. In 2001 he received his Ph.D. in Electrical Engineering from the University of Pennsylvania. His Ph.D. research focused on biologically inspired algorithms for the feature detection in visual images. Except for the three years he spent at University of Pennsylvania, he has been working for Sankyo since 1984, where he has been involved in the research and development of medical instruments including a microchip for capillary electrophoresis. He is currently working in the field of bioinformatics. Jan Van der Spiegel received his Masters and Ph.D. degrees in Electrical Engineering from the University of Leuven, Belgium, in 1974 and 1979, respectively. He joined the University of Pennsylvania in 1981 where he is currently a Professor of Electrical and Systems Engineering and the director of the Center for Sensor Technologies. He was the chairman of the Department of Electrical Engineering from 1998 to 2002 and the interim chairman of the Electrical and Systems Engineering department at the University of Pennsylvania from 2002 to 2004. His research interests are in mixed-mode VLSI design, biologically based sensors and sensory information processing systems, micro-sensor technology, and analog-to-digital converters. He is the author of over 150 journal and conference papers and holds 4 patents. He is a Fellow of the IEEE (2002) and the recipient of the IEEE Third Millennium Medal, the UPS Foundation Distinguished Education Chair and the Bicentennial Class of 1940 Term Chair. He received the Christian and Mary Lindback Foundation, and the S. Reid Warren Award for Distinguished Teaching. He was also Editor of Sensors and Actuators A for North and South America from 1983 to 2004.     

Scaling and Pixel Crosstalk Considerations for CMOS Image Sensor

With the scaling development of the minimum lithographic size, the scaling trend of CMOS imager pixel size and fill factor has been computed according to the Moore rule. When the CMOS minimum lithographic feature scales down to 0.35 μm,the CCD imagepixel size is not so easy to be reduced and but the CMOS image pixel size benefits from the scaling minimum lithographic feature. However, when the CMOS technology is downscaled to or under 0.35μm,the fabrication of CMOS image sensors will be limited by the standard CMOS process in both ways of shallow trench isolation and source/drain junction, which results in pixel crosstalk. The impact of the crosstalk on the active pixel CMOS image sensor is analyzed based on the technology scaling. Some suppressed crosstalk methods have been reviewed. The best way is that combining the advantages of CMOS and SOI technology to fabricate the image sensors will reduce the pixel crosstalk.     

CMOS图像传感器的发展及应用

比较了CMOS图像传感器与CCD图像传感器的优缺点，分析了CMOS图像传感器的结构、研制现状、应用及市场前景。指出随着CMOS传感器技术的发展，CMOS图像传感器可以代替CCD图像传感器，并预见了其发展趋势。     

Organic Photodetectors and their Application in Large Area and Flexible Image Sensors: The Role of Dark Current

Organic photodetectors (OPDs) have gained increasing interest as they offer cost‐effective fabrication methods using low temperature processes, making them particularly attractive for large area image detectors on lightweight flexible plastic substrates. Moreover, their photophysical and optoelectronic properties can be tuned both at a material and device level. Visible‐light OPDs are proposed for use in indirect‐conversion X‐ray detectors, fingerprint scanners, and intelligent surfaces for gesture recognition. Near‐infrared OPDs find applications in biomedical imaging and optical communications. For most applications, minimizing the OPD dark current density (J_d) is crucial to improve important figures of merits such as the signal‐to‐noise ratio, the linear dynamic range, and the specific detectivity (D*). Here, a quantitative analysis of the intrinsic dark current processes shows that charge injection from the electrodes is the dominant contribution to J_d in OPDs. J_d reduction is typically addressed by fine‐tuning the active layer energetics and stratification or by using charge blocking layers. Yet, most experimental J_d values are higher than the calculated intrinsic limit. Possible reasons for this deviation are discussed, including extrinsic defects in the photoactive layer and the presence of trap states. This provides the reader with guidelines to improve the OPD performances in view of imaging applications.