A better understanding of CMOS latch-up

Both lumped-element two-transistor circuit model and two-dimensional finite-element analyses are used to study the latch-up phenomena in CMOS structures. The equivalent circuit model offers a simple view on latch-up, while 2-D modeling provides more physics and quantitative understanding of latch-up. A generalized criterion for p-n-p-n latch-up is derived based on the equivalent circuit. 2-D modeling confirms the latch-up triggering condition described by the criterion. Furthermore, 2-D simulation models the entire latch-up process, including the dynamic triggering stage, and determines the intrinsic steady-state I - V characteristics of p-n-p-n devices.     

Three-dimensional distribution of CMOS latch-up current

This paper presents experimental evidence of relevant three-dimensional (3-D) effects in CMOS latch-up obtained by means of novel multicontact test structures. It is also shown that "quasi-" two-dimensional (2-D) experimental data in good agreement with numerical simulations can be achieved only by limiting the analysis to the central sections of wide experimental devices.     

Transient characteristics of latch-up in bulk CMOS

Transient characteristics of the latch-up turn-on process in bulk CMOS are investigated. A measurement technique that evaluates the threshold trigger pulse current of latch-up and also observes latch-up turn-on transient waveforms is established. Through the comparison between experimental data and precise circuit simulation results, the main factors that determine transient latch-up characteristics are clarified as the base-emitter diffusion capacitors.     

An efficient numerical model of CMOS latch-up

A one-dimensional numerical model of latch-up in bulk CMOS structures is presented. The model simulates the triggering and sustaining regimes of the parasitic SCR, yielding results nearly equivalent to those obtained using two-dimensional analysis, but with two orders of magnitude-lower computational cost. The model is used to obtain the SCR switching characteristics of typical CMOS based on two-dimensional impurity cross sections, and parameter sensitivities are examined.     

Numerical analysis of heavy ion particle-induced CMOS latch-up

Heavy ion particle-induced CMOS latch-up is analyzed using a two-dimensional transient numerical simulator. The charge funneling effect during the carrier collection process is found to lower the parasitic bipolar emitter-base potential barrier. This parasitic bipolar action is the main factor initiating latch-up. Latch-up susceptibility is then examined as a parameter of the heavy ion particle incident condition.     

An analytic model of holding voltage for latch-up in epitaxial CMOS

For epitaxial CMOS in the latched state, the region between the anode and the cathode is conductivity modulated. In this case, the two-transistor model for the silicon-controlled rectifier (SCR) is not valid. However, a simplified analysis is possible because the well-substrate junction is obliterated by carriers. With this approach an analytic model is developed which can predict the holding voltage and its dependence on design parameters. The model is capable of predicting quantitatively the improvement in holding voltage with increased n+ -to-p+ spacing, thinner epi, substrate backbias, shallow trench, and silicided junctions and higher epi doping. The model explains a previously observed scaling law for the holding voltage.     

Temperature dependence of latch-up phenomena in scaled CMOS structures

In this paper the temperature dependence of latch-up in a VLSI CMOS technology is studied. Both steady-state and pulse-induced dynamic trigger characteristics are presented showing a marked increase in latch-up resistance with decreasing temperature; in particular, a latch-up free condition is met for several structures at temperatures ranging between 100 and 200 K. The results of measurements of parasitic bipolar parameters and shunting resistances at different temperatures are reported, and their values are related to latch-up characteristics.     

Optically induced latch-up and other effects in CMOS UVEPROMs

Photographic flash-gun equipment used close to uncovered CMOS UVEPROMs can induce a variety of different failure modes including: (a) destructive latch-up, (b) transients in the output logic levels and in the supply current and (c) a nonde structive `output latching? effect. The mode of failure observed depends on the level of illumination used and on the logic state of the output pins.     

Temperature dependence of latch-up characteristics in LDD CMOS devices

The incremental rate of the latch-up holding current (Ih) with decreasing temperature is larger in the bulk substrate than in the epitaxial substrate. The substrate dependence is mainly due to the difference in the temperature coefficients of the material resistivity. Although Ihincreases significantly with decreasing temperature, the latch-up triggering voltage (Vtrig) in an inverter remains relatively constant, posing a limit for VLSI device miniaturization at low temperatures.     

Correlations between CMOS latch-up characteristics and substrate structure parameters

A structure-oriented model based on a simplified two-dimensional numerical analysis has been developed to calculate the substrate spreading resistance of a parasitic SCR latch-up path in a CMOS circuit. This model establishes the correlation between the major latch-up characteristics parameters (holding voltage, holding current and triggering current) and the structure parameters in the substrate. The correlations thus obtained have been used to predict the effects of layout and structural changes in the substrate on the latch-up characteristics through the application of this model. It has been verified that the calculated results are in good agreement with both the experimental results of the fabricated devices and the simulation results based on the exact two-dimensional numerical analysis.     

An explicit multi-exponential model for semiconductor junctions with series and shunt resistances

An alternative explicit multi-exponential model is proposed to describe multiple, arbitrary ideality factor, conduction mechanisms in semiconductor junctions with parasitic series and shunt resistances. This Lambert function based model allows the terminal current to be expressed as an explicit analytical function of the applied terminal voltage, in contrast to the implicit-type conventional multi-exponential model. As a result this model inherently offers a higher computational efficiency than conventional models, making it better suited for repetitive simulation and parameter extraction applications. Its explicit nature also allows direct analytic differentiation and integration. The model’s applicability has been assessed by parameter extraction and subsequent playback using synthetic and experimental diode forward I-V characteristics.     

Cost-effective smart power CMOS/DMOS technology: design methodology for latch-up immunity

To answer to the need of a cost effective smart power technology, an original design methodology that permits implementing latch-up free smart power circuits on a very simple CMOS/DMOS technology is proposed. The basic concept used to this purpose is letting float the wells of the MOS transistors most susceptible to initiate latch-up. The efficiency of the design methodology is experimentally shown.     

Approximate analytical expression for equation of ideal diode with series and shunt resistances

A simple and continuous analytical approximation for the equation of an ideal diode with a series resistance and shunt conductance is proposed. When compared to the exact numerical solution, the approximate expression produces relative errors smaller than 3%, for any values of series resistance and shunt conductance.<>     

The impact of trench isolation on latch-up immunity in bulknonepitaxial CMOS

Numerical simulations have been used to show that two-dimensional effects can improve the latch-up immunity of deep trench-isolated, bulk, nonepitaxial CMOS. It is observed that the holding voltage is strongly influenced by trench dimensions and layout, which affect the two-dimensional spreading resistance of the conductivity-modulated well and substrate regions, which also changes the parasitic bipolar current gain. To increase the holding voltage, design parameters that are unique to deep trench isolation have been identified. The theoretical understanding that has been obtained can be exploited to design latch-up-free submicrometer CMOS at high packing densities without using expensive epitaxial substrates     

Analysis of latch-up neighborhood effects in VLSI CMOS input and output stages

The influence of electron and hole injection from neighboring structures on the latch-up hardness of an inverter in non-epitaxial CMOS is measured on specially designed test structures and compared with the results of two-dimensional numerical simulation provided by the program BAMBI. An analysis of the basic effects is given and remedial measures to avoid neighborhood effects are described.     

An efficient method for calculating the d.c. triggering currents in CMOS latch-up

The substrate and well resistances have been calculated from the structure parameters of the fabricated CMOS structures. Based on the ideal diode model and the calculated resistances, the d.c. triggering currents for CMOS latch-up due to the voltage undershoot and overshoot on the parasitic emitters have been calculated. The calculated d.c. triggering currents have been compared with experimental measurements and good agreement has been obtained. Therefore, the proposed method is efficient in calculating the d.c. triggering currents.     

The transient analysis of latch-up in CMOS transmission gate induced by laser

An analytical model of transient latch-up in CMOS transmission gate induced by laser is established. The time-dependent current characteristics of the parasitic silicon controlled rectifier (SCR) under different injected photocurrent are illustrated. The model analyzes the trigger conditions for latch-up and describes the dynamic process varying with time. The photocurrent threshold causing latch-up under different pulse widths and repetition frequencies is obtained, which agrees well with the experimental results reported in the literature.     

A physical model for the correlation between holding voltage andholding current in epitaxial CMOS latch-up

A new physical model concerning the holding points for latch-up in epitaxial CMOS structures is established by combining the lateral p-i-n high level injection and the vertical BJT base push-out formula. The model matches adequately the correlation between holding voltage and holding current extensively measured from different combinations of temperatures, epitaxial layer thicknesses, and anode-to-cathode spacings. This is also the case for the two-dimensional device simulations. A quantitative analysis based on the model consistently judges the crucial role of the vertical BJT base push-out width in producing the observed correlation. The potential merits of the model in extended applications are outlined     

Measuring partial thermal resistances in a heat-flow path

The paper presents techniques of measuring partial steady state thermal resistance values in a heat flow path with the help of thermal transient measurements and the subsequent numerical evaluation. The method is based on the further evaluation of the structure functions of the heat flow path. After presenting the theoretical background of the evaluation two different practical examples are presented to demonstrate the use of the method. The first example presents a series of experiments on how to use the method to detect die attach and/or soldering failures in packaged devices. The second example demonstrates that the method can be applied to measure the very small R/sub th/ values of thin conducting layers. Various practical solutions are discussed and demonstrated by simulations. The chances and the limits of the methodology are discussed in detail in the conclusion section.