Device circuit co‐design to reduce gate leakage current in VLSI logic circuits in nano regime

In this paper, nanoscale metal–oxide–semiconductor field‐effect transistor (MOSFET) device circuit co‐design is presented with an aim to reduce the gate leakage curren t in VLSI logic circuits. Firstly, gate leakage current is modeled through high‐k spacer underlap MOSFET (HSU MOSFET). In this HSU MOSFET, inversion layer is induced in underlap region by the gate fringing field through high‐k dielectric (high‐k) spacer, and this inversion layer in the underlap region acts as extended source/drain region. The analytical model results are compared with the two‐dimensional Sentaurus device simulation. Good agreement is obtained between the model and Sentaurus simulation. It is observed that modified HSU MOSFET had improved off current, subthreshold slope, and drain‐induced barrier lowering characteristics. Further, modified HSU MOSFET is also analyzed for gate leakage in generic logic circuits. Copyright © 2015 John Wiley & Sons, Ltd.     

1/f Noise: threshold voltage and ON-current fluctuations in 45 nm device technology due to charged random traps

Discrete impurity effects in terms of their statistical variations in number and position in the inversion and depletion region of a MOSFET, as the gate length is aggressively scaled, have recently been investigated as being a major cause of reliability degradation observed in intra-die and die-to-die threshold voltage variation on the same chip resulting in significant variation in saturation drive (on) current and transconductance degradation—two key metrics for benchmark performance of digital and analog integrated circuits. In this paper, in addition to random dopant fluctuations (RDF), the influence of random number and position of interface traps lying close to Si/SiO₂ interface has been examined as it poses additional concerns because it leads to enhanced experimentally observed fluctuations in drain current and threshold voltage. In this context, the authors of this article present novel EMC based simulation study on trap induced random telegraph noise (RTN) responsible for statistical fluctuation pattern observed in threshold voltage, its standard deviation and drive current in saturation for 45 nm gate length technology node MOSFET device. From the observed simulation results and their analysis, it can be projected that with continued scaling in gate length and width, RTN effect will eventually supersede as a major reliability bottleneck over the already present RDF phenomenon. The fluctuation patterns observed by EMC simulation outcomes for both drain current and threshold voltage have been analyzed for the cases of single trap and two traps closely adjacent to one another lying in the proximity of the Si/SiO₂ interface between source to drain region of the MOSFET and explained from analytical device physics perspectives.     

An analytic drain current model for long‐channel undoped gate stack surrounding‐gate MOSFETs including interface fixed charges

On the basis of the exact solution of Poisson's equation and Pao–Sah double integral for long‐channel bulk MOSFETs, a continuous and analytic drain current model for the undoped gate stack (GS) surrounding‐gate (SRG) metal–oxide–semiconductor field‐effect transistor (MOSFET) including positive or negative interface fixed charges near the drain junction is presented. Considering the effect of the interface fixed charges on the flat‐band voltage and the electron mobility, the model, which is expressed with the surface and body center potentials evaluated at the source and drain ends, describes the drain current from linear region to saturation region through a single continuous expression. It is found that the surface and body center potentials are increased/decreased in the case of positive/negative interface fixed charges, respectively, and the positive/negative interface fixed charges can decrease/increase the drain current. The model agrees well with the 3D numerical simulations and can be efficiently used to explore the effects of interface fixed charges on the drain current of the gate stack surrounding‐gate MOSFETs of the charge‐trapped memory device. Copyright © 2013 John Wiley & Sons, Ltd.     

Analysis and modeling of unipolar junction transistor with excellent performance: a novel DG MOSFET with $${N}^{+}{-}{P}^{-}$$ junction

We propose herein a new dual-gate metal–oxide–semiconductor field-effect transistor (MOSFET) with just a unipolar junction (UJ-DG MOSFET) on the source side. The UJ-DG MOSFET structure is constructed from an \({N}^{+}\) region on the source side with the rest consisting of a \({P}^{-}\) region over the gate and drain, forming an auxiliary gate over the drain region with appropriate length and work function (named A-gate), converting the drain to an \({N}^{+}\) region. The new structure behaves as a MOSFET, exhibiting better efficiency than the conventional double-gate MOSFET (C-DG MOSFET) thanks to the modified electric field. The amended electric field offers advantages including improved electrical characteristics, reliability, leakage current, \({I}_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio, gate-induced drain leakage, and electron temperature. Two-dimensional analytical models of the surface potential and electric field over the channel and drain are applied to investigate the drain current in the UJ-DG MOSFET. To confirm their accuracy, the MOSFET characteristics obtained using the 2D Atlas simulator for the UJ-DG and C-DG are analyzed and compared.     

Gate leakage behavior of source/drain-to-gate non-overlapped MOSFET structure

In this paper, novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time. The gate leakage behavior of novel MOSFET structure has been investigated with help of compact analytical model and Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended source/drain region. It is found that optimal source/drain-to-gate non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and drain induced barrier lowering characteristic with a slight degradation in source/drain series resistance and effective gate capacitance.     

The statistics of NBTI-induced V/sub T/ and /spl beta/ mismatch shifts in pMOSFETs

Negative bias temperature instability (NBTI) is a pFET degradation mechanism that can result in threshold voltage shifts up to 100 mV or more, even in very thin oxide devices. Since analog circuits that utilize matched pairs of devices, such as current mirrors and differential pairs, generally depend on V/sub T/ matching considerably better than this, NBTI-induced V/sub T/ mismatch shift may represent a serious reliability concern for CMOS analog applications. Furthermore, induced /spl beta/ mismatch shift (affecting drain current level at a fixed gate overdrive voltage) may also impact drain current and transconductance mismatch. In this paper, experimental results of the statistics and scaling properties of NBTI-induced V/sub T/ and /spl beta/ mismatch shifts in saturation, and models describing these results, are presented.     

寄生电感对于功率MOSFET开关特性的影响

分散在MOSFET栅极、源极、漏极的寄生电感由于封装以及印制电路板（PCB）走线,改变了MOSFET的开关特性。通过仿真分析对比,指出MOSFET寄生电感存在如下特性：源极电感对栅极驱动形成负反馈,导致开关速度变慢,采用开尔文连接,可以将栅极回路与功率回路解耦,提高驱动速度;在米勒效应发生时刻需要合理地降低栅极电感来降低栅极驱动电流;漏极电感通过米勒电容影响MOSFET的开通速度,在关断时刻导致电压应力增加;在并联的回路当中,非对称的布局将导致MOSFET之间的动态不均流;当MOSFET在开关过程中,环路电感与MOSFET自身的结电容产生振荡时,可以在电路增加吸收电容减小环路电感,改变振荡特性。     

Two-dimensional analytical model of threshold voltage and drain current of a double-halo gate-stacked triple-material double-gate MOSFET

We have developed a two-dimensional analytical model for the channel potential, threshold voltage, and drain-to-source current of a symmetric double-halo gate-stacked triple-material double-gate metal–oxide–semiconductor field-effect transistor (MOSFET). The two-dimensional Poisson’s equation is solved to obtain the channel potential. For accurate modeling of the device, fringing capacitance and effective surface charge are considered. The basic drift–diffusion equation is used to model the drain-to-source current. The midchannel potential of the device is used instead of the surface potential in the current modeling, considering the fact that the punch-through current is not confined only to the surface in a fully depleted MOSFET. An expression for the pinch-off voltage is derived to model the drain current in the saturation region accurately. Various short-channel effects such as drain-induced barrier lowering, gate leakage, threshold voltage, and roll-off have also been investigated. This structure shows excellent ability to suppress various short-channel effects. The results of the proposed model are validated against data obtained from a commercially available numerical device simulator.     

功率MOSFET的高温特性及其安全工作区分析

简述了功率MOSFET的结构特点及工作原理,从理论上分析了温度对阈值电压、跨导、导通电阻、漏极饱和电流及击穿电压等关键参数的影响.采用ISE软件模拟了不同温度下器件的导通特性和阻断特性,给出了这些参数随温度变化的曲线.最后,分析了温度对功率MOSFET安全工作区的影响,为功率MOSFET的设计和使用提供了参考.     

Investigation of multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) sub‐50 nm MOSFET: A novel design

In this paper, a two‐dimensional (2D) analytical sub‐threshold model for a novel sub‐50 nm multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) MOSFET is presented and investigated using ATLAS device simulator to counteract the large gate leakage current and increased standby power consumption that arise due to continued scaling of SiO₂‐based gate dielectrics. The model includes the evaluation of surface potential, electric field along the channel, threshold voltage, drain‐induced barrier lowering, sub‐threshold drain current and sub‐threshold swing. Results reveal that MLGEWE‐RC MOSFET design exhibits significant enhancement in terms of improved hot carrier effect immunity, carrier transport efficiency and reduced short channel effects proving its efficacy for high‐speed integration circuits and analog design. Copyright © 2008 John Wiley & Sons, Ltd.     

Electrostatic discharge effects in ultrathin gate oxide MOSFETs

The effects of destructive and nondestructive electrostatic discharge (ESD) events applied either to the gate or drain terminal of MOSFETs with ultrathin gate oxide, emulating the occurrence of an ESD event at the input or output IC pins, respectively, were investigated. The authors studied how ESD may affect MOSFET reliability in terms of time-to-breakdown (TTBD) of the gate oxide and degradation of the transistor electrical characteristics under subsequent electrical stresses. The main results of this paper demonstrate that ESD stresses may modify the MOSFET current driving capability immediately after stress and during subsequent accelerated stresses but do not affect the TTBD distributions. The damage introduced by ESD in MOSFETs increases when the gate oxide thickness is reduced.     

1200V碳化硅MOSFET与硅IGBT器件特性对比性研究

搭建了输出特性测试电路、漏电流测试电路、双脉冲测试电路和Buck电路,对1 200 V SiC MOSFET和Si IGBT的输出特性、漏电流、开关特性和器件损耗进行了对比研究,分析了SiC MOSFET的主要优缺点。分析结果表明,SiC MOSFET在高温条件下依然拥有稳定的阻断能力;在同样的工作条件下,SiC MOSFET损耗更小,适合在高频率、大功率场合下使用;SiC MOSFET的跨导低,导通电阻大,所以门极驱动电压需要比较大的摆幅(-5/+20 V);由于开关速度很快,SiC MOSFET对线路杂散参数更加敏感。     

MOSFET开关过程的研究及米勒平台振荡的抑制

设计功率MOSFET驱动电路时需重点考虑寄生参数对电路的影响。米勒电容作为MOSFET器件的一项重要参数,在驱动电路的设计时需要重点关注。重点观察了MOSFET的开通和关断过程中栅极电压、漏源极电压和漏源极电流的变化过程,并分析了米勒电容、寄生电感等寄生参数对漏源极电压和漏源极电流的影响。分析了栅极电压在米勒平台附近产生振荡的原因,并提出了抑制措施,对功率MOSFET的驱动设计具有一定的指导意义。     

Characterization of defect density created by stress in the gate to?drain overlap region using GIDL current model in n-channel MOSFET

In this paper we study the impact of stress on gate induced drain leakage (GIDL) current variations in MOS transistors, which manifested by tunneling in the gate to drain overlap region. The oxide thickness of n-channel transistor used is 8.5?nm. We show that this phenomenon is accentuated in high stress accumulation V _g=?3?V, V _d=3?V, but more less for stress V _g=V _d=3?V. In both cases, any constraint corresponds to an increase in accumulated charges in the transistor and hence the current GIDL.     

Potential‐based threshold voltage and subthreshold swing models for junctionless double‐gate metal‐oxide‐semiconductor field‐effect transistor with dual‐material gate

On the basis of quasi‐two‐dimensional solution of Poisson's equation, an analytical threshold voltage model for junctionless dual‐material double‐gate (JLDMDG) metal‐oxide‐semiconductor field‐effect transistor (MOSFET) is developed for the first time. The advantages of JLDMDG MOSFET are proved by comparing the central electrostatic potential and electric field distribution with those of junctionless single‐material double‐gate (JLSMDG) MOSFET. The proposed model explicitly shows how the device parameters (such as the silicon thickness, oxide thickness, and doping concentration) affect the threshold voltage. In addition, the variations of threshold voltage roll‐off, drain‐induced barrier lowering (DIBL), and subthreshold swing with the channel length are investigated. It is proved that the device performance for JLDMDG MOSFET can be changed flexibly by adjusting the length ratios of control gate and screen gate. The model is verified by comparing its calculated results with those obtained from three‐dimensional numerical device simulator ISE. Copyright © 2015 John Wiley & Sons, Ltd.     

Intrinsic reliability projections for a thin JVD silicon nitridegate dielectric in P-MOSFET

A comprehensive study of the intrinsic reliability of a 1.4-nm (equivalent oxide thickness) JVD Si₃N₄ gate dielectric subjected to constant-voltage stress has been conducted. The stress leads to the generation of defects in the dielectric. As a result, the degradation in the threshold voltage, subthreshold swing, gate leakage current, and channel mobility has been observed. The change in each of these parameters as a function of stress time and stress voltage is studied. The data are used to project the drift of a MOSFET incorporating JVD nitride at a low operating voltage of 1.2 V in 10 years. Based on these projections, we conclude that the increase in the Si₃N₄ gate dielectric leakage current does not pose a serious threat to device performance. Instead, the degradation in the threshold voltage and channel mobility can become the factor limiting the device reliability     

Shielded channel double-gate MOSFET: a novel device for reliable nanoscale CMOS applications

In this paper, the unique features exhibited by a novel double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) in which the front gate consists of two side gates to 1) electrically shield the channel region from any drain voltage variation and 2) act as an extremely shallow virtual extension to the source/drain are presented. This structure exhibits significantly reduced short-channel effects (SCEs) when compared with the conventional DG MOSFET. Using two-dimensional (2-D) and two-carrier device simulation, the improvement in device performance focusing on threshold voltage dependence on channel length, electric field in the channel, subthreshold swing, and hot carrier effects, all of which can affect the reliability of complementary metal oxide semiconductor (CMOS) devices, was investigated.     

Nanoscale circuit implementation using tri-metal gate engineered nanowire MOSFET with gate stack for analog/RF applications

In this work, the potential benefit of tri-metal gate engineered nanowire MOSFET with gate stack for analog/RF applications is developed and presented. A systematic, quantitative investigation of main figure of merit for the device is carried out to demonstrate its improved RF/analog performance. The results show an improvement in drain current, \(I_{\mathrm{on}} /I_{\mathrm{off}}\) ratio, transconductance, unity-gain frequency (\(f_{\mathrm{T}}\)), maximum oscillation frequency (\(f_{\mathrm{max}}\)) providing superior RF performance as compared to single and dual-metal gate stack nanowire MOSFET. The suitability of the device for analog/RF applications is also analyzed by implementing the device in a low-noise amplifier circuit, and the S-parameter values are estimated.     

Analytical and Numerical Investigation of Noise in Nanoscale Ballistic Field Effect Transistors

The current of ballistic nanoscale MOSFETs is expected to exhibit shot noise, essentially because the electron distribution is very far from equilibrium. Here, we derive an analytical expression of shot noise in fully ballistic MOSFETs and show how it can be computed on the basis of numerical simulations of the DC electrical properties. We show that the power spectral density of shot noise of the drain current is strongly suppressed as an effect of both Pauli exclusion and electrostatic interaction. The amount of such suppression depends on the device structure, and in particular on the gate capacitance. Results on shot noise of the gate current are also shown, since such the leakage current might be significant in nanoscale MOSFETs, for small equivalent oxide thickness.