The science and technology of magnetoresistive tunneling memory

Rapid advances in portable communication and computing systems are creating an increasing demand for nonvolatile random access memory that is both high-density and highspeed. Existing solid-state technologies are unable to provide all of the needed attributes in a single memory solution. Therefore, a number of different memories are currently being used to achieve the multiple functionality requirements, often compromising performance and adding cost to the system. A new technology, magnetoresistive random access memory (MRAM) based on magnetoresistive tunneling, has the potential to replace these memories in various systems with a single, universal solution. The key attributes of MRAM are nonvolatility, high-speed operation. and unlimited read and write endurance. This technology is enabled by the ability to deposit high-quality, nanometer scale tunneling barriers that display enhanced magnetoresistive response. In this article we describe several fundamental technical and scientific aspects of MRAM with emphasis on recent accomplishments that enabled our successful demonstration of a 256-Kb memory chip     

High‐Performance Solution‐Processed Organo‐Metal Halide Perovskite Unipolar Resistive Memory Devices in a Cross‐Bar Array Structure

Resistive random access memories can potentially open a niche area in memory technology applications by combining the advantages of the long endurance of dynamic random‐access memory and the long retention time of flash memories. Recently, resistive memory devices based on organo‐metal halide perovskite materials have demonstrated outstanding memory properties, such as a low‐voltage operation and a high ON/OFF ratio; such properties are essential requirements for low power consumption in developing practical memory devices. In this study, a nonhalide lead source is employed to deposit perovskite films via a simple single‐step spin‐coating method for fabricating unipolar resistive memory devices in a cross‐bar array architecture. These unipolar perovskite memory devices achieve a high ON/OFF ratio up to 10⁸ with a relatively low operation voltage, a large endurance, and long retention times. The high‐yield device fabrication based on the solution‐process demonstrated here will be a step toward achieving low‐cost and high‐density practical perovskite memory devices.     

Engineering the spectral and temporal properties of a GHz-bandwidth heralded single-photon source interfaced with an on-demand,broadband quantum memory

Photonics offers a route to fast and distributed quantum computing in ambient conditions, provided that photon sources and logic gates can be operated deterministically. Quantum memories, capable of storing and re-emitting photons on demand, enable quasi-deterministic operations by synchronizing stochastic events. Interfaced source–memory systems are thus a key building block in photonics-based quantum information processors. We discuss the design of the single-photon source in this type of light–matter interface and present an experimental system based on a Raman-type quantum memory. In addition to the spectral purity of the produced heralded single photons, we find that their temporal distinguishability also becomes important due to the implicit temporal binning derived from photon storage in the memory. When aiming to operate the source–memory system at high repetition rates, a practical compromise between both of these requirements needs to be found. Our implemented photon source system demonstrates such a solution and enables passive stability, high brightness in a single-pass configuration, high purity as well as good mode matching to our Raman memory.     

Tunnel junctions with multiferroic barriers

Multiferroics are singular materials that can exhibit simultaneously electric and magnetic orders. Some are ferroelectric and ferromagnetic and provide the opportunity to encode information in electric polarization and magnetization to obtain four logic states. However, such materials are rare and schemes allowing a simple electrical readout of these states have not been demonstrated in the same device. Here, we show that films of La(0.1)Bi(0.9)MnO(3) (LBMO) are ferromagnetic and ferroelectric, and retain both ferroic properties down to a thickness of 2 nm. We have integrated such ultrathin multiferroic films as barriers in spin-filter-type tunnel junctions that exploit the magnetic and ferroelectric degrees of freedom of LBMO. Whereas ferromagnetism permits read operations reminiscent of magnetic random access memories (MRAM), the electrical switching evokes a ferroelectric RAM write operation. Significantly, our device does not require the destructive ferroelectric readout, and therefore represents an advance over the original four-state memory concept based on multiferroics.     

MgO-Based Tunnel Junction Material for High-Speed Toggle Magnetic Random Access Memory

We report the first demonstration of a magnetoresistive random access memory (MRAM) circuit incorporating MgO-based magnetic tunnel junction (MTJ) material for higher performance. We compare our results to those of AlOx-based devices, and we discuss the MTJ process optimization and material changes that made the demonstration possible. We present data on key MTJ material attributes for different oxidation processes and free-layer alloys, including resistance distributions, bias dependence, free-layer magnetic properties, interlayer coupling, breakdown voltage, and thermal endurance. A tunneling magnetoresistance (TMR) greater than 230% was achieved with CoFeB free layers and greater than 85% with NiFe free layers. Although the TMR with NiFe is at the low end of our MgO comparison, even this MTJ material enables faster access times, since its TMR is almost double that of a similar structure with an AlO$_ x$barrier. Bit-to-bit resistance distributions are somewhat wider for MgO barriers, with sigma about 1.5% compared to about 0.9% for AlO$_ x$. The read access time of our 4 Mb toggle MRAM circuit was reduced from 21 ns with AlO$_ x$to a circuit-limited 17 ns with MgO.     

A Novel Reference Scheme for Reading Passive Resistive Crossbar Memories

A great effort today is concentrated on the development of resistive hysteretic materials and their related memory architecture. Resistive memories have a promising future to replace all current memory technologies to present an all-in-one memory solution. Passive resistive memories are of a special importance, since they can be scaled into the nanometer range without losing their functionality. This work is concerned with a novel scheme for generating reference voltages for the read operation. The scheme can be used with any passive crossbar based memory, regardless of the materials used for the implementation of the memory elements     

Beyond MRAM, CMOS/MTJ Integration for Logic Components

Spintronics is a new discipline in which the spin of the electron is used as an additional degree of freedom besides its electrical charge to build innovative electronic components. Magnetic materials can be used as spin polarizer/analyzer in association with semiconductors or insulators, resulting in hybrid CMOS/magnetic architectures. Magnetic Tunnel Junctions (MTJ) are the basic elements of a new kind of memory, called MRAM (Magnetic Random Access Memory). Besides MRAM, it has recently been shown that by combining MTJ and CMOS components, one can also develop new functionalities for logic devices. This paper aims at giving a general overview of these novel hybrid magnetic/CMOS architectures and the design tools required for their design.     

Proposal of a Novel Pole Type Structures in Perpendicular MRAM for High Gb/Chip

This paper proposes a novel MRAM using perpendicular magnetic tunnel junction device for high capacity. Conventional MRAM has weak points to realize high capacity in the design structure of the cell, one of which is that using simple current injection system can generate only weak switching field. As a solution, we propose a novel MRAM that has two additional poles in this paper. Proposed novel MRAM has a strong switching field owing to two poles added on both sides of the free layer, just like perpendicular magnetic recording heads. In this paper, analysis of the switching field and useful designs for high Gb/Chip are presented. This research was done using three dimensional FEM with injected current density of $8times 10^{7}$ A/cm$^{2}$ –$6times 10^{8}$ A/cm$^{2}$ .      

Optoelectronic-cache memory system architecture

We present an investigation of the architecture of an optoelectronic cache that can integrate terabit optical memories with the electronic caches associated with high-performance uniprocessors and multiprocessors. The use of optoelectronic-cache memories enables these terabit technologies to provide transparently low-latency secondary memory with frame sizes comparable with disk pages but with latencies that approach those of electronic secondary-cache memories. This enables the implementation of terabit memories with effective access times comparable with the cycle times of current microprocessors. The cache design is based on the use of a smart-pixel array and combines parallel free-space optical input-output to-and-from optical memory with conventional electronic communication to the processor caches. This cache and the optical memory system to which it will interface provide a large random-access memory space that has a lower overall latency than that of magnetic disks and disk arrays. In addition, as a consequence of the high-bandwidth parallel input-output capabilities of optical memories, fault service times for the optoelectronic cache are substantially less than those currently achievable with any rotational media.     

Evolutionary Metal Oxide Clusters for Novel Applications: Toward High‐Density Data Storage in Nonvolatile Memories

Because of current fabrication limitations, miniaturizing nonvolatile memory devices for managing the explosive increase in big data is challenging. Molecular memories constitute a promising candidate for next‐generation memories because their properties can be readily modulated through chemical synthesis. Moreover, these memories can be fabricated through mild solution processing, which can be easily scaled up. Among the various materials, polyoxometalate (POM) molecules have attracted considerable attention for use as novel data‐storage nodes for nonvolatile memories. Here, an overview of recent advances in the development of POMs for nonvolatile memories is presented. The general background knowledge of the structure and property diversity of POMs is also summarized. Finally, the challenges and perspectives in the application of POMs in memories are discussed.     

Methods for improving the signal-to-noise ratio of photon and electron beam accessed magnetic-film memory systems

Methods are described for reducing shot noise in magnetic-film memories which are to be read magnetooptically with the auxiliary aid of an electron beam. In such memories the principal source of shot noise is from the light which is used to illuminate the memory array. The following methods of reducing array shot noise are considered: 1) selective background, 2) magnetooptical balance, 3) temperature control of magnetooptical spectra in rare-earth iron garnets (REIG). It is concluded that the use of REIG spectra appears to offer not only the best but also a satisfactory solution to the array shot-noise problem.     

A built-in self-testing method for embedded multiport memory arrays

With recent advances in semiconductor technologies, the design and use of memories for realizing complex system-on-a-chip (SoC) is very widespread. The growing need for storage in computer, communication, and network appliances has motivated new advancements in faster and more efficient ways to test memories. Efficient testing schemes for single-port memories have been readily available. Multiport memories are widely used in multiprocessor systems, telecommunication application-specific integrated circuits (ASICs), etc. Research papers which define multiport memory fault models and give march tests for the same are currently available. However, little work has been done to use the power of serial interfacing for testing multiport memories. In this paper, we develop a powerful test architecture for two-port memories using the serial interfacing technique. Based on the serial testing mechanism, we propose new march algorithms which can prove effective to reduce hardware cost considerably for a chip with many two-port memories. Once we understand how serial interfacing helps test two-port memories, one possible extension is to use serial interfacing for p-port memories (p > 2). The proposed method based on the serial interfacing technique has the advantages of high fault coverage, low hardware overhead, and tolerable test application time.     

Review Modern magnetic materials in data storage

The current status of the technology of magnetic recording as used in disk drives is reviewed. The emphasis is on the magnetic materials used in the application and on some of the technical problems that may limit the increase in areal density. The new technology of magnetic random access memory (MRAM), which has evolved from the magnetic recording application, is also reviewed. A wide range of magnetic materials is essential for the advance of magnetic recording and the MRAM technology. For the magnetic-recording application the requirements are for high-magnetization, soft magnetic materials for write heads, new antiferromagnetic alloys with high blocking temperatures, large coupling to ferromagnetic films and low susceptibility to corrosion for pinning films in giant magnetoresistive sensors, and for the MRAM application, the requirement is for new ferromagnetic alloys with large values of tunneling polarization ratio. A significant limitation to magnetic recording is found to be the inconsistent demands on media thickness: small media thicknesses are required for large values of signal-to-noise ratio, while large values of thickness are required to reduce the impact of the superparamagnetic effect, which results in the potential for data loss over time. Both of these requirements are discussed. Multilayer ferromagnetic films for recording surfaces are shown to allow both large signal-to-noise ratio and adequate resistance to data loss.     

Characterization of Domain Switching Behavior of MTJ Cells Using Magnetic Force Microscopy (MFM) and R–H Loop Analysis

Correlation between electrical and magnetic properties of magnetic tunnel junctions (MTJ) for magnetic random access memory (MRAM) was studied. The MTJ (Ta/NiFeCr/ PtMn/CoFe/Ru/CoFe/Al₂O₃/CoFe/NiFe/Ta) was analyzed by utilizing R-H loops and MFM images. We verified that a kink in an R-H loop comes from a vortex domain of free layer. In addition, we also observed a close relationship between a domain switching behavior and an irregular R-H curve. These results would be useful for the characterization of the MTJ cell, thereby optimizing the process to realize an ultrahigh density MRAM.     

Magnetoelektronik. Magnetoelectronics

The discovery of strong spin‐dependent transport processes in magnetic materials has triggered the advent of a new research field with a strong application potential: magnetoelectronics. This field is concerned with the development of microelectronic devices based on magnetotransport phenomena. Since these phenomena occur predominantly in ultrathin film systems, their technological exploitation poses significant challenges to thin film preparation and requires careful spin engineering. Magnetoresistive read heads for hard disks have already been successfully introduced on the market, and further applications in information technology, for example, nonvolatile magnetic memory banks (MRAM) are coming within reach. The realization of active magnetoelectronic devices, however e.g., a spin transistor, will need further research work.     

隧道磁电阻效应的原理及应用

隧道磁电阻具有饱和磁场低、工作磁场小、灵敏度高、温度系数小等优点,在磁随机存取存储器(MRAM)、TMR磁头和磁传感器等自旋电子器件上颇受欢迎,有着广阔的应用前景.重点介绍了隧道磁电阻效应中自旋相关输运特点及原理,阐述了最近几年国内外最新研究进展,最后讨论了隧道磁电阻效应在实际应用中所面临的一些问题.     

Design of on-chip error correction systems for multilevel NOR and NAND flash memories

The design of on-chip error correction systems for multilevel code-storage NOR flash and data-storage NAND flash memories is concerned. The concept of trellis coded modulation (TCM) has been used to design on-chip error correction system for NOR flash. This is motivated by the non-trivial modulation process in multilevel memory storage and the effectiveness of TCM in integrating coding with modulation to provide better performance at relatively short block length. The effectiveness of TCM-based systems, in terms of error-correcting performance, coding redundancy, silicon cost and operational latency, has been successfully demonstrated. Meanwhile, the potential of using strong Bose-Chaudhiri-Hocquenghem (BCH) codes to improve multilevel data-storage NAND flash memory capacity is investigated. Current multilevel flash memories store 2 bits in each cell. Further storage capacity may be achieved by increasing the number of storage levels per cell, which nevertheless will correspondingly degrade the raw storage reliability. It is demonstrated that strong BCH codes can effectively enable the use of a larger number of storage levels per cell and hence improve the effective NAND flash memory storage capacity up to 59.1% without degradation of cell programming time. Furthermore, a scheme to leverage strong BCH codes to improve memory defect tolerance at the cost of increased NAND flash cell programming time is proposed.     

Attacking the bottleneck in a bus‐based multiprocessor system

Abstract

Connection through a single bus is the simplest architecture for multiprocessor systems. However, as the number of processors scales up, the common bus will eventually become the bottleneck of the system. Three different bus‐based architectures, multiprocessors without local memories, multiprocessors with single port local memories, and multiprocessors with dual port memories, are analyzed in this paper. It shows to what degree increasing the local execution probability of a multiprocessor system with dual port memories can relieve the load of the common bus and thus increase the effective computing power. A multiprocessor operating system (MOS) designed at National Chiao Tung University (NCTU) has suffered bottleneck trouble in the previous year. Problems in MOS are discussed. A new design of this operating system kernel, MOS*, is then proposed. Performance of these two different designs are evaluated and compared by simulation. The simulation results show that MOS*, with a localizing process strategy, can increase effective computing power 30–100 percent. The saturation point of MOS* is also explored in the paper.     

A new 40-nm SONOS structure based on backside trapping for nanoscale memories

Silicon-on-nothing (SON) devices have been analyzed for the first time in view of nanoscaled nonvolatile memories (NVM) applications. Two reliable steady states have been demonstrated using backside charge trapping in the nitride layer under the channel as a memory effect in a 40-nm gate-length pMOS silicon-oxide-nitride-oxide-silicon device realized with SON technology. Low voltages (/spl sim/3 V) are required for memory operations and a threshold voltage memory window superior to 0.5 V can be achieved. Charge loss mechanism is analyzed and very promising data retention behavior is demonstrated at 125/spl deg/C. This architecture, with a storage node localized under the channel, is exactly the same device that can operate as a high-performance transistor at low voltages and as an NVM cell at higher voltage ranges. A total compatibility between logic and the embedded NVM process is thus insured. In view of high-density memories, the feasibility of 2-bit storage in a longer SON device is also demonstrated.     

Low-density parity-check codes for volume holographic memory systems

We investigate the application of low-density parity-check (LDPC) codes in volume holographic memory (VHM) systems. We show that a carefully designed irregular LDPC code has a very good performance in VHM systems. We optimize high-rate LDPC codes for the nonuniform error pattern in holographic memories to reduce the bit error rate extensively. The prior knowledge of noise distribution is used for designing as well as decoding the LDPC codes. We show that these codes have a superior performance to that of Reed-Solomon (RS) codes and regular LDPC counterparts. Our simulation shows that we can increase the maximum storage capacity of holographic memories by more than 50 percent if we use irregular LDPC codes with soft-decision decoding instead of conventionally employed RS codes with hard-decision decoding. The performance of these LDPC codes is close to the information theoretic capacity.