共查询到20条相似文献,搜索用时 868 毫秒
1.
A fully integrated burst-mode GaAs MESFET optoelectronic integrated circuit (OEIC) receiver, 215 mil×109 mil, that has been designed and implemented for point-to-point data links for application as a phased-array antenna controller is described. The chip provides a low-cost means for passing 400-Mb/s antenna control information using fiber optics with a very low bit-error rate (BER). Approximately 350 source-coupled FET logic gates are present on the chip. A new data coding and timing recovery scheme that is highly tolerant to jitter over a wide bandwidth has been developed. The OEIC uses an on-chip metal-semiconductor-metal (MSM) photodiode with 0.12-A/W responsivity measured at 780 nm and was fabricated in a 1.0-mm GaAs MESFET manufacturing technology. The low capacitance semi-insulating GaAs substrate minimizes the coupling between analog and digital circuitry. The circuit operates from a single 5-V supply, consumes 1 W of power, and provides an 8-b CMOS output bus together with various utility flags. Optical sensitivity is estimated at -20 dBm for 10-14 BER 相似文献
2.
Mino S. Ohyama T. Akahori Y. Hashimoto T. Yamada Y. Yanagisawa M. Muramoto Y. 《Lightwave Technology, Journal of》1996,14(11):2475-2482
A planar lightwave circuit (PLC) platform for optoelectronic hybrid integration shows potential for achieving 10 Gb/s operation. It uses AuSn bump-type bonding pads on a silica layer to decrease parasitic capacitance, which limited the CR time constant in the optical chip assembly region, and two-layer electrical wiring to reduce parasitic inductance, which caused resonance in the electrical circuit region. An arrayed receiver module fabricated by integrating a two-channel monolithic opto-electronic integrated circuit (OEIC) chip on the PLC platform demonstrated a 3 dB-bandwidth of 8 GHz in both channels, which is equal to the bandwidth of the OEIC chip. This shows the feasibility of using this PLC platform for multichannel 10 Gb/s operation. Furthermore, this PLC platform can combine the versatile optical circuit functions of a PLC, such as an arrayed-waveguide grating wavelength multiplexer, with the high-speed signal processing function of mature electronic IC circuits. Consequently, this platform is a key device that will lead to high-capacity optical signal processing systems using optical wavelength/frequency routing 相似文献
3.
Plant D.V. Venditti M.B. Laprise E. Faucher J. Razavi K. Chateauneuf M. Kirk A.G. Ahearn J.S. 《Lightwave Technology, Journal of》2001,19(8):1093-1103
Two-dimensional parallel optical interconnects (2-D-POIs) are capable of providing large connectivity between elements in computing and switching systems. Using this technology we have demonstrated a bidirectional optical interconnect between two printed circuit boards containing optoelectronic (OE) very large scale integration (VLSI) circuits. The OE-VLSI circuits were constructed using vertical cavity surface emitting lasers (VCSELs) and photodiodes (PDs) flip-chip bump-bonded to a 0.35-μm complementary metal-oxide-semiconductor (CMOS) chip. The CMOS was comprised of 256 laser driver circuits, 256 receiver circuits, and the corresponding buffering and control circuits required to operate the large transceiver array. This is the first system, to our knowledge, to send bidirectional data optically between OE-VLSI chips that have both VCSELs and photodiodes cointegrated on the same substrate 相似文献
4.
针对应用于850nm光通信中的10/100Mbit/s收发器,提出采用0.5μm标准CMOS工艺对其光接收芯片实现Si基单片集成。整体芯片面积为0.6mm2,共集成了一个双光电二极管的(DPD)光电探测器和一个跨阻前置放大电路,功耗为100mW,并给出了具体的测试性能结果。结果表明,在850nm光照下,光接收芯片带宽达到53MHz,工作速率为72Mbit/s。重点介绍了DPD光电探测器的原理和结构,并给出了相应的制造过程和电路等效模型,对整个光接收芯片进行了多种实用性测试,可以满足系统的性能要求。 相似文献
5.
Liu J.J. Olver K.A. Monica Taysing-Lara Taylor T. Wayne Chang Horst S. 《Components and Packaging Technologies, IEEE Transactions on》2003,26(3):548-553
Oxide-confined top-emitting 850 nm and bottom-emitting 980 nm vertical-cavity surface-emitting laser (VCSEL) 8/spl times/8 arrays were designed and fabricated for applications of optical interconnects. The arrays were flip-chip bonded onto sapphire substrates that contain complimentary metal-oxide-semiconductor (CMOS) driver and fan-out circuitries. The off-sited bonding contacts and minimized bonding force produced very high yield of the hybridization process without causing damage to the VCSEL mesas. The hybridized devices were further mounted either on printed circuit board (PCB) or in 68-pin pin-grid-array (PGA) packages. The transparent sapphire substrate allowed optical outputs from the top-emitting VCSEL arrays to transmit directly through without additional substrate removal procedure. Lasing thresholds below 250 /spl mu/A for 850 nm VCSELs and 800 /spl mu/A for 980 nm VCSEL were found at room temperature. The oxide confinement apertures of VCSELs were measured to be around 6 /spl mu/m in diameter. High-speed data transmission demonstrated a bandwidth of up to 1 Gbits/s per channel for these hybridized VCSEL transmitters. 相似文献
6.
R. Urata R. Takahashi T. Nakahara K. Takahata H. Suzuki 《Photonics Technology Letters, IEEE》2006,18(1):67-69
We propose an optically clocked transistor array optoelectronic integrated circuit (OEIC) for both serial-to-parallel and parallel-to-serial conversion (demux/mux), enabling an interface between high-speed asynchronous burst optical labels and CMOS circuitry for optical label swapping. Dual functionality of the OEIC reduces size, power, and cost of the optical label swapper. The capability for greater than 20-Gb/s conversion operation is demonstrated. 相似文献
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Results of a monolithically integrated Si optical receiver for applications in optical data transmission and in optical interconnects with wavelengths of 638 and 850 nm are presented. The optoelectronic integrated circuit (OEIC) implementing a vertical p-type-intrinsic-n-type photodiode achieves a data rate of 1 Gb/s for 638 nm with a sensitivity of -15.4 dBm at a bit-error rate of 10-9 . The sensitivity of this OEIC in a 1.0-μm CMOS technology is improved by at least a factor of four compared to that of published submicrometer OEICs. A 25-THz.Ω effective transimpedance bandwidth product of the implemented amplifier is achieved 相似文献
9.
A new BiCMOS optoelectronic integrated circuit (OEIC) for applications in advanced optical storage systems is presented. It is optimized with respect to high sensitivity and high speed. The photodiode and the amplifier are monolithically integrated on the same substrate in a commercial 0.8-/spl mu/m BiCMOS process. Analytical expressions for the compensation capacitors and for the bandwidth of the OEIC are derived. Neglecting antireflection coating, no process modifications are necessary to produce the integrated photodiodes. A new offset compensation scheme is implemented in the amplifiers to allow for a small chip area and low power consumption. The OEIC shows a sensitivity of 43.3 mV//spl mu/W in combination with a -3-dB bandwidth of 60.2 MHz. 相似文献
10.
《Solid-State Circuits, IEEE Journal of》1981,16(5):435-443
A fault-tolerant 30950 mil/SUP 2/ (19.9 mm/SUP 2/) 16K/spl times/1 static MOS RAM has been fabricated with a single polysilicon E/D NMOS process. Using circuit techniques normally restricted to dynamic RAMs, but adapted for asynchronous operation, the device achieves a typical access time of 30 ns while dissipating only 375 mW. Among the topics discussed in a new single-polysilicon memory cell configuration, the first truly asynchronous bootstrap circuit, an active bit-line equilibration and precharge scheme, and a new power-efficient substrate bias generator. Also described is an on-chip redundancy scheme which consumes approximately 2 percent of the total chip area, does not compromise access time and can be programmed using standard test equipment. 相似文献
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A 10 Gb/s OEIC (optoelectronic integrated circuit) optical receiver front-end has been studied and fab ricated based on the φ-76 mm GaAs PHEMT process; this is the first time that a limiting amplifier (LA) has been designed and realized using depletion mode PHEMT. An OEIC optical receiver front-end mode composed of an MSM photodiode and a current mode transimpedance amplifier (TIA) has been established and optimized by simu lation software ATLAS. The photodiode has a bandwidth of 10 GHz, a capacitance of 3 fF/μm and a photosensitive area of 50×50 μm~2. The whole chip has an area of 1511×666 μm~2. The LA bandwidth is expanded by spiral inductance which has been simulated by software HFSS. The chip area is 1950×1910μm~2 and the measured results demonstrate an input dynamic range of 34 dB (10-500 mVpp) with constant output swing of 500 tnVpp. 相似文献
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14.
《Solid-State Circuits, IEEE Journal of》1985,20(1):137-143
High-performance 1.0-/spl mu/m n-well CMOS/bipolar on-chip technology was developed. For process simplicity, an n-well and a collector of bipolar transistors were formed simultaneously, and base and NMOS channel regions were also made simultaneously resulting in collector-isolated vertical n-p-n bipolar transistor fabrication without any additional process step to CMOS process. On the other hand, 1.0-/spl mu/m CMOS with a new "hot carrier resistant" seIf-defined Polysilicon sidewall spacer (SEPOS) LDD NMOS was developed. It can operate safely under supply voltage over 5 V without performance degradation of CMOS circuits. By evaluating ring oscillators and differential amplifiers constructed by both CMOS and bipolar transistors. it can be concluded that in a digital and in an analog combined system, CMOS has sufficiently high-speed performance for digital parts, while bipolar is superior for analog parts. In addition, bipolar transistors with an n/sup +/-buried layer were also fabricated to reduce collector resistance. Concerning the bipolar input/output buffers, the patterned n/sup +/-buried layer improves the drivability and high-frequency response. As a result, the applications of n-well CMOS/bipolar technology become clear. This technology was successfully applied to a high-speed 64-kbit CMOS static RAM, and improvement in access time was observed. 相似文献
15.
Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test 总被引:1,自引:0,他引:1
《Solid-State Circuits, IEEE Journal of》2008,43(11):2533-2545
16.
CMOS RF amplifier and mixer circuits utilizing complementary Characteristics of parallel combined NMOS and PMOS devices 总被引:1,自引:0,他引:1
Design and chip fabrication results for complementary RF circuit topologies that utilize the complementary RF characteristics of both NMOS and PMOS field-effect-transistor devices combined in parallel way are reported, which can inherently provide single-ended differential signal-processing capability, requiring neither baluns, nor differential signal generating/combining circuits. The proposed complementary CMOS parallel push-pull (CCPP) amplifier gives an order of magnitude improvement in IP/sub 2/ than an NMOS common-source amplifier and single-balanced CCPP resistive mixer, which functions effectively as a double-balanced one, provides more than an order of magnitude better linearity in IP/sub 2/, and similar order of magnitude better local oscillator (LO)-IF and LO-RF isolations than NMOS counterparts. 相似文献
17.
《Industrial Electronics, IEEE Transactions on》2009,56(7):2299-2307
18.
An optical receiver configuration based on the concept of using a single optically gated metal-semiconductor-fieid-effect transistor (MESFET) to perform the function of a photodetector and preamplifier has been introduced. The proposed optoelectronic integrated circuit (OEIC) receiver has been analyzed theoretically. A simplified noise model of the receiver has also been developed. Results have been presented for an OEIC receiver based on InGaAs MESFET supposed to be fabricated with matured InGaAs-InP MMIC technology. Theoretical results based on a simplistic noise model reveal that the proposed OEIC receiver has superior performance characteristics over the existing optical receivers 相似文献
19.
Kyounghoon Yang Gutierrez-Aitken A.L. Xiangkun Zhang Haddad G.I. Bhattacharya P. 《Lightwave Technology, Journal of》1996,14(8):1831-1839
High-speed, long-wavelength InAlAs/InGaAs OEIC photoreceivers based on a p-i-n/HBT shared layer integration scheme have been designed, fabricated and characterized. The p-i-n photodiodes, formed with the 6000 Å-thick InGaAs precollector layer of the HBT as the absorbing layer, exhibited a responsivity of ~0.4 A/W and a -3 dB optical bandwidth larger than 20 GHz at λ=1.55 μm. The fabricated three-stage transimpedance amplifier with a feedback resistor of 550 Ω demonstrated a transimpedance gain of 46 dBΩ and a -3 dB bandwidth of 20 GHz. The monolithically integrated photoreceiver with a 83 μm p-i-n photodiode consumed a small dc power of 35 mW and demonstrated a measured -3 dB optical bandwidth of 19.5 GHz, which is the highest reported to date for an InAlAs/InGaAs integrated front-end photoreceiver. The OEIC photoreceiver also has a measured input optical dynamic range of 20 dB. The performance of individual devices and integrated circuits was also investigated through detailed CAD-based analysis and characterization. Transient simulations, based on a HSPICE circuit model and previous measurements of eye diagrams for a NRZ 231-1 pseudorandom binary sequence (PRBS), show that the OEIC photoreceiver is capable of operation up to 24 Gb/s 相似文献
20.
Shyh-Yih Ma Liang-Gee Chen 《Solid-State Circuits, IEEE Journal of》1999,34(10):1415-1418
A complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) camera chip with direct frame difference output is reported in this paper. The proposed APS cell circuit has in-pixel storage for previous frame image data so that the current frame image and the previous frame image can be read out simultaneously in differential mode. The signal swing of the pixel circuit is maximized for low supply voltage operation. The pixel circuit occupies 32.2×32.2 μm2 of chip area with a fill factor of 33%. A 128×98 element prototype camera chip with an on-chip 8-bit analog-to-digital converter has been fabricated in a 0.5-μm double-poly double-metal CMOS process and successfully tested. The camera chip consumes 56 mW at 30 frames/s with 3.3 V power supply 相似文献