Mobility Management for Hierarchical Wireless Networks

In this paper, we consider the mobility management in large, hierarchically organized multihop wireless networks. The examples of such networks range from battlefield networks, emergency disaster relief and law enforcement etc. We present a novel network addressing architecture to accommodate mobility using a Home Agent concept akin to mobile IP. We distinguish between the physical routing hierarchy (dictated by geographical relationships between nodes) and logical hierarchy of subnets in which the members move as a group (e.g., company, brigade, battalion in the battlefield). The performance of the mobility management scheme is investigated through simulation.     

Scheduling and bandwidth allocation for the distribution of archived video in VOD systems

Providing costeffective videoondemand (VOD) services necessitates reducing the required bandwidth for transporting video over highspeed networks. In this paper, we investigate efficient schemes for transporting archived MPEGcoded video over a VOD distribution network. A video stream is characterized by a timevarying traffic envelope, which provides an upper bound on the bit rate. Using such envelopes, we show that video streams can be scheduled for transmission over the network such that the perstream allocated bandwidth is significantly less than the source peak rate. In a previous work [13], we investigated stream scheduling and bandwidth allocation using global traffic envelopes and homogeneous streams. In this paper, we generalize the scheduling scheme in [13] to include the heterogeneous case. We then investigate the allocation problem under windowbased traffic envelopes, which provide tight bounds on the bit rate. Using such envelopes, we introduce three streamscheduling schemes for multiplexing video connections at a server. The performance of these schemes is evaluated under static and dynamic scenarios. Our results indicate a significant reduction in the perstream allocated bandwidth when stream scheduling is used. While this reduction is obtained through statistical multiplexing, the transported streams are guaranteed stringent, deterministic quality of service (i.e., zero loss rate and small, bounded delay). In contrast to video smoothing, our approach requires virtually no buffer at the settop box since frames are delivered at their playback rate.     

Tree multicast strategies in mobile,multihop wireless networks

Tree multicast is a well established concept in wired networks. Two versions, persource tree multicast (e.g., DVMRP) and shared tree multicast (e.g., Core Based Tree), account for the majority of the wireline implementations. In this paper, we extend the tree multicast concept to wireless, mobile, multihop networks for applications ranging from ad hoc networking to disaster recovery and battlefield. The main challenge in wireless, mobile networks is the rapidly changing environment. We address this issue in our design by: (a) using soft state (b) assigning different roles to nodes depending on their mobility (2level mobility model); (c) proposing an adaptive scheme which combines shared tree and persource tree benefits, and (d) dynamically relocating the shared tree Rendezvous Point (RP). A detailed wireless simulation model is used to evaluate various multicast schemes. The results show that persource trees perform better in heavy loads because of the more efficient traffic distribution; while shared trees are more robust to mobility and are more scalable to large network sizes. The adaptive tree multicast scheme, a hybrid between shared tree and persource tree, combines the advantages of both and performs consistently well across all load and mobility scenarios. The main contributions of this study are: the use of a 2level mobility model to improve the stability of the shared tree, the development of a hybrid, adaptive persource and shared tree scheme, and the dynamic relocation of the RP in the shared tree.     

Current Mode Circuit Implementations of PWL Functions

Current-mode techniques have been used to realize improved basic building blocks of elementary piecewise linear (PWL) functions. These alternative circuit implementations, used for synthesis of precision PWL transfer characteristics, are described and compared in performance. In this paper, two optional topologies of the PWL function building blocks are proposed, based on the regulated cascode current mirror, current sources, Schottky prebiased diodes, and improved CMOS class AB prebiased diodes. The comparison of DC and high frequency performances is based on HSPICE simulation results and shows very good DC accuracy and transient time response of the proposed building blocks.     

Floor acquisition multiple access (FAMA) in single‐channel wireless networks

The FAMANCS protocol is introduced for wireless LANs and adhoc networks that are based on a single channel and asynchronous transmissions (i.e., no time slotting). FAMANCS (for floor acquisition multiple access with nonpersistent carrier sensing) guarantees that a single sender is able to send data packets free of collisions to a given receiver at any given time. FAMANCS is based on a threeway handshake between sender and receiver in which the sender uses nonpersistent carrier sensing to transmit a requesttosend (RTS) and the receiver sends a cleartosend (CTS) that lasts much longer than the RTS to serve as a busy tone that forces all hidden nodes to back off long enough to allow a collisionfree data packet to arrive at the receiver. It is shown that carrier sensing is needed to support collisionfree transmissions in the presence of hidden terminals when nodes transmit RTSs asynchronously. The throughput of FAMANCS is analyzed for singlechannel networks with and without hidden terminals; the analysis shows that FAMANCS performs better than ALOHA, CSMA, and all prior proposals based on collision avoidance dialogues (e.g., MACA, MACAW, and IEEE 802.11 DFWMAC) in the presence of hidden terminals. Simulation experiments are used to confirm the analytical results.     

Quality Determination for Gate Delay Fault Tests Considering Three-State Elements

Most industrial digital circuits contain three-state elements besides pure logic gates. This paper presents a gate delay fault simulator for combinational circuits that can handle three-state elements like bus drivers, transmission gates and pulled busses. The well known delay faults--slow-to-rise and slow-to-fall--are considered as well as delayed transitions from isolating signal state high impedance to binary states 0 and 1 and vice versa. The presented parallel delay fault simulator distinguishes between non-robust, robust and hazard free tests and determines the quality of a test. Experimental results for ISCAS85/89 benchmark circuits are presented as well as results for industrial circuits containing three-state elements.     

Noise considerations for mixed‐signal RF IC transceivers

This paper discusses design tradeoffs for mixedsignal radio frequency integrated circuit (RF IC) transceivers for wireless applications in terms of noise, signal power, receiver linearity, and gain. During air wave transmission, the signal is corrupted by channel noise, adjacent interfering users, image signals, and multipath fading. Furthermore, the receiver corrupts the incoming signal due to RF circuit nonlinearity (intermodulation), electronic device noise, and digital switching noise. This tutorial paper gives an overview of the design tradeoffs needed to minimize RF noise in an integrated wireless transceiver. Fundamental device noise and the coupling of switching noise from digital circuits to sensitive analog sections and their impact on RF circuits such as frequency synthesizers are examined. Methods to minimize mixedsignal noise coupling and to model substrate noise effects are presented.     

The discrete Einstein relation

In this paper the connection between massM, resistance and commute time for random walks on graphs is further explored, and the relation=2M · is proved. An extension of the result is made to multigraphs, which are an extension of the graph concept where a black box is treated like an edge.     

Assigning codes in wireless networks: bounds and scaling properties

In the Code Division Multiple Access (CDMA) framework, collisions that can occur in wireless networks are eliminated by assigning orthogonal codes to stations, a problem equivalent to that of coloring graphs associated to the physical network. In this paper we present new upper and lower bounds for two versions of the problem (hidden and primary collision avoidance – HPCA – or hidden collision avoidance only – HCA). In particular, optimal assignments for special topologies and heuristics for general topologies are proposed. The schemes show better average results with respect to existing alternatives. Furthermore, the gaps between the upper bound given by the heuristic solution, the lower bound obtained from the maximumclique problem, and the optimal solution obtained by branch and bound are investigated in the different settings. A scaling law is then proposed to explain the relations between the number of codes needed in Euclidean networks with different station densities and connection distances. The substantial difference between the two versions HPCA and HCA of the problem is investigated by studying the probabilistic distribution of connections as a function of the distance, and the asymptotic size of the maximum cliques.     

Bounds on the sizes of irredundant test sets and sequences for combinational logic networks

We present a method of determining lower and upper bounds on the number of tests required to detect all detectable faults in combinational logic networks. The networks are composed of AND, OR, NAND, NOR, and XOR gates. The fault model assumes that single stuck-at-zero faults occur on the lines of the networks, with the additional requirement that XOR gates be tested with all possible input combinations. The goal is to provide a simple and efficient implementation that processes the fanout-free subnetworks separately, and then combines the results without the need to consider the effects of reconvergent fanout. We introduce the concepts of irredundant test sets, where no test can be deleted regardless of the order of test application, and irredundant test sequences, where every test detects at least one additional fault when tests are applied in order. Identifying and differentiating between these types of collections of tests allows us to understand more precisely the mechanisms and expected performance of test generation and test compaction methods. We apply our test counting technique and two other published procedures to a set of benchmark circuits. Our bounds are shown to compare favorably to the results obtained by the other published approaches. We obtain minimal and maximal test sets and test sequences using a greedy optimization technique. Our bounds are shown to produce tight bounds for the smaller circuits; they grow more conservative as the size of the circuits increase.     

A pattern classification proposal for object‐oriented audio coding in MPEG‐4

The future MPEG4 standard will adopt an objectoriented encoding strategy whereby an audio source is encoded at a very low bitrate by adapting a suitable coding scheme to the local characteristics of the signal. One of the most delicate issues in this approach is that the overall performance of the audio encoder greatly depends on the accuracy with which the input signal is classified. This paper shows that the difficult problem of audio classification for objectoriented coding can be effectively solved by selecting a salient set of acoustic parameters and adopting a fuzzy model for each audio object, obtained by a soft computinghybrid learning tool. The audio classifier proposed operates at two levels: recognition of the class to which the input signal belongs (talkspurt, music, noise, signaling tones) and then recognition of the subclass to which it belongs. The results obtained show that fuzzy logic is a valid alternative to the matching techniques of a traditional pattern recognition approach.     

The Satchel system architecture: Mobile access to documents and services

Mobile professionals require access to documents and documentrelated services, such as printing, wherever they may be. They may also wish to give documents to colleagues electronically, as easily as with paper, facetoface, and with similar security characteristics. The Satchel system provides such capabilities in the form of a mobile browser, implemented on a device that professional people would be likely to carry anyway, such as a pager or mobile phone. Printing may be performed on any Satchelenabled printer, or any fax machine. Scanning, too, may be accomplished at any Satchelenabled scanner. Access rights to individual documents may be safely distributed, without regard to document formats. Access to document services is greatly simplified by the use of context sensitivity. The system has been extensively tested and evaluated. This paper describes the architecture of the Satchel system.     

A 640 by 480 Pixels Readout Circuit for IR Imaging

A readout circuit for a 640 × 480 pixels FPA (focal plane array) has been successfully designed, fabricated and tested. The circuit solution is based on a per pixel source-follower direct injection (SFDI) pre-amplifier. Signal multiplexing is performed in both X and Y direction. The pixel size is 25 m × 25m. The chip is optimized for a QWIP (quantum well infrared photodetector) operating at a temperature of 70 K. The circuit has been realized in a standard 0.8 m CMOS process.     

1 V All-MOS ΣΔ A/D Converters in the Log-domain

This paper presents novel low-voltage all-MOS analog circuit techniques for the synthesis of oversampling A/D converters. The new approach exploits the possibilities of Log-domain processing by using the MOSFET in subthreshold operation. Based on this strategy, a complete set of very low-voltage (down to 1 V) low-power (below 100 W) all-MOS basic building blocks is proposed. The resulting analog circuit techniques allow the integration of A/D converters for low-frequency (below 100 KHz) applications in digital CMOS technologies. Examples are given for a standard 0.35 m VLSI process.     

The Effect of Ballistic Conduction Electrons on the Current–Voltage Characteristics of Thin-Film Bismuth-Based Cross-Shaped Microstructures

A decrease in the residual pressure to 10^–6 Pa during the deposition of bismuth films results in low-temperature metallic conductance of the films. Cross-shaped microstructures made of these films exhibit the property of ballistic transport, which is typical of two-dimensional systems. This property shows up as a bend of the current–voltage characteristics (CVCs). The value of bend resistance changes in inverse proportion to the width of interconnects and drops with increasing temperature in the range of 4.2–77 K. The free path of conduction electrons, are responsible for the CVC bend, was estimated at more than 1 m.     

Simulation‐based performance evaluation of routing protocols for mobile ad hoc networks

In this paper we evaluate several routing protocols for mobile, wireless, ad hoc networks via packetlevel simulations. The ad hoc networks are multihop wireless networks with dynamically changing network connectivity owing to mobility. The protocol suite includes several routing protocols specifically designed for ad hoc routing, as well as more traditional protocols, such as link state and distance vector, used for dynamic networks. Performance is evaluated with respect to fraction of packets delivered, endtoend delay, and routing load for a given traffic and mobility model. Both small (30 nodes) and medium sized (60 nodes) networks are used. It is observed that the new generation of ondemand routing protocols use much lower routing load, especially with small number of peertopeer conversations. However, the traditional link state and distance vector protocols provide, in general, better packet delivery and endtoend delay performance.     

RF CMOS Cells for Wireless Applications

There is increasing interest in the use of CMOS circuits for high frequency highly integrated wireless telecommunications systems. This paper presents the results of on-going work into the development of a cell library that includes many of the circuit elements required for the high frequency sub-systems of communications integrated circuits. The cell library studied included an RF control element, single ended Class A amplifier, RF isolator, and Gilbert cell mixer circuit topologies. Circuit design criteria and measurement results are presented. All cells were fabricated using standard 2.0, 1.2, and 0.8 m CMOS integrated circuit fabrication processes with no post-processing performed. The results indicate that 2.0 m CMOS can be used successfully up to approximately 250 MHz with 0.8 m cells useful up to approximately 1000 MHz.     

A mean-value analysis of slotted-ring network models

In this paper, we analyse Stochastic Petri Net (SPN) models of slotted-ring networks. We show that a simple SPN model of a slotted-ring network, which exhibits a product-form solution, yields similar results to a more detailed SPN model that has to be analysed by numerical means. Furthermore, we demonstrate a Mean-Value Analysis (MVA) approach to calculate efficiently the results for the simple model. This MVA approach allows for the movement of groups of tokens (customers) rather than just individual customers, as traditional MVA schemes for queueing network models do. Also, the MVA allows for non-disjoint place invariants, whereas previous MVA schemes addressed disjoint place invariants only. From the MVAs, it can be concluded that slotted-rings have very attractive performance characteristics, even under overload conditions (there is no thrashing). Also, we found that the choice of the slot size is a key factor in calibrating slotted-ring systems for optimal performance. Having a fast and reasonably accurate means available to evaluate the performance of slotted-ring systems, such as our proposed MVA, eases this calibration task. The proposed MVA for the product-form SPN models should therefore be regarded as a quick engineering tool.     

On the design of feedback controllers to achieve prescribed initial value constraints

The problem of designing a stabilizing compensator for a control system to achieve prescribed initial value constraints ⁽ⁱ⁾(0⁺)=y_i is considered. Indeed, modulo certain technical conditions, such a compensator exists if and only if y_i=0;i= 0,1,...,rp +rt –2; whererp is the relative degree of the plant andrt is the relative degree of the system input. This theorem is derived and a complete parameterization of the set of compensators that achieve the prescribed design constraints is formulated.This research was supported in part by NSF Grant No. 921106.     

VLSI Implementation of Fuzzy Adaptive Resonance and Learning Vector Quantization

We present a mixed-mode VLSI chip performing unsupervised clustering and classification, implementing models of Fuzzy Adaptive Resonance Theory (ART) and Learning Vector Quantization (LVQ), and extending to variants such as Kohonen Self-Organizing Maps (SOM). The parallel processor classifies analog vectorial data into a digital code in a single clock, and implements on-line learning of the analog templates, stored locally and dynamically using the same adaptive circuits for on-chip quantization and refresh. The unit cell performing fuzzy choice and vigilance functions, adaptive resonance learning and long-term analog storage, measures 43 m×43 m in 1.2 m CMOS technology. Experimental learning results from a fabricated 8-input, 16-category prototype are included.