Low-voltage constant-gm rail-to-rail CMOS operational amplifier input stage

This paper presents a rail-to-rail constant-g_m operational amplifier input stage. The proposed circuit changes the tail current of the input differential pairs dynamically for a constant-g_m by using dummy input differential pairs. The problem which causes total g_m variation is input pairs and dummy input pairs can not take effect at the same time with the common-mode input voltage changes, because the tail current transistor of the input pairs are in triode region when the input pairs are turned off, the dummy input pairs will enter subthreshold region from cut-off region before the input pairs when common-mode voltage changes. The effect of this problem is more obviously in low supply voltage design. To solve this problem, compensate current sources is added to the tail current transistors of each dummy input differential pairs for lower g_m variation. The g_m of this Op Amp’s input stage varies around ±2%.     

An Electrometer Amplifier with Low Input Capacitance and Large Input Dynamic Range

An electrometer amplifier has been designed for biological research with the following data: input resistance larger than 1012; input current 10-12 A; low input capacitance; and an input dynamic range from 0 to ± 7 v. The input stage consists of JFET.     

A rail-to-rail amplifier input stage with /spl plusmn/0.35%g/sub m/ fluctuation

A new scheme for achieving rail-to-rail input to an amplifier is introduced. Constant g/sub m/ is obtained by using tunable level shifters and a single differential pair. Feedback circuitry controls the level shifters in a manner that fixes the common-mode input of the differential pair, resulting in consistent and stable operation for rail-to-rail inputs. As the new technique avoids using complimentary input differential pairs, this method overcomes problems such as common-mode rejection ratio and gain-bandwidth product degradation that exist in many other designs. The circuit was fabricated in 0.5-/spl mu/m process. The resulting differential pair had a constant transconductance that varied by only /spl plusmn/0.35% for rail-to-rail input common-mode levels. The input common-mode range extended well past the supply levels of /spl plusmn/1.5V, resulting in only /spl plusmn/1% fluctuation in g/sub m/ for input common modes from -2 to 2 V.     

Compact CMOS constant-gm rail-to-rail input stage with gm-control by an electronic zener diode

A family of compact CMOS rail-to-rail input stages with constant-g _m is presented. To attain a constant-g_m over the whole common-mode input range, an electronic zener diode is inserted between the tails of the complementary input pairs. This zener keeps the sum of the gate-source voltages of the input pairs, and therefore the g _m of the rail-to-rail input stage, constant. Two possible implementations of the zener have been realized and inserted in a rail-to-rail input stage. These input stages are implemented in two two-stage compact amplifiers. Both amplifiers have been realized in a 1 μm BiCMOS process. They have a unity-gain frequency of 2-MHz, for a capacitive load of 20 pF     

The small bare loop antenna immersed in a dissipative medium

The input admittance of a small thin-wire circular loop antenna, driven by a slice generator, immersed in a dissipative medium, is considered. It is found that the solution given by Storer for the loop antenna in a lossless medium can be carded over readily by replacingzeta_{0}byzeta, andk_{0}byk. The numerical values of the normalized input conductance and input susceptance of a small loop antenna, namelybeta b leq 0.3,Omega = 10, are calculated. It is to be noted that the input susceptance is practically independent ofkwhile the input conductance changes as much as seventeen times in this special case.     

一种正负输入电压ASIC的输入保护电路设计

提出一种适用于正负输入电压专用集成电路的输入保护电路。该电路设计思想新颖 ,可在不影响电路工作的情况下 ,对正负过压都能起良好的保护作用。     

非均匀业务下反压型输入/输出排队ATM交换机的性能分析

本文分析了一种内部无阻塞反压型输入／输出排队ＡＴＭ交换机，在非均匀负载输入下的信元丢失、信元延时指标，文中采用一一种Ｇｅｏｍ／ＰＨ／Ｉ／Ｋ排队模型分析输入排队系统仲裁系统的分析采用了一种二维Ｍａｒｋｏｖ过程，结论对设计一种反压型输入／输出排队ＡＴＭ交换机有参考意义。     

基于单片机和555定时器的A/D转换器设计

为克服在A/D转换中输入电压范围窄的问题,介绍了一种采用单片机AT89C51和NE555定时器构成的A/D转换器.详细分析了其工作原理和A/D转换的特性.该A/D转换器对低频输入信号在较高电压范围内具有一定的实用价值.     

Random Test Generation With Input Cube Avoidance

Test generation procedures attempt to assign values to the inputs of a circuit so as to detect target faults. We investigate a complementary view whereby the goal is to avoid the assignment of certain input values in order not to prevent faults from being detected. We describe a procedure for computing input cubes (or incompletely specified input vectors) that should be avoided during test generation for target faults. We demonstrate that avoiding such input cubes leads to the detection of target faults after the application of limited numbers of random input vectors. This indicates that explicit test generation is not necessary once certain input values are precluded. Other potential uses of the computed input cubes are in a deterministic test generation procedure to reduce the search space, and during built-in test generation to preclude input vectors that will not lead to the detection of target faults. We consider stuck-at faults in full-scan circuits. We also extend the discussion to four-way bridging faults.      

Ku-band subsampling track-and-hold amplifier with 8 ENOB resolution

A wideband subsampling track-and-hold amplifier has been designed for input frequencies up to Ku-band and clock rates up to 2.5 GS/s. Circuits were fabricated in 1 /spl mu/m InP SHBT technology. Spur-free dynamic range measured with two-tone input frequencies of 12.6 and 12.602 GHz and a 2.5 GS/s clock rate ranges from 53-69 dB at an input level of -1 dBFS for each tone. Signal-to-noise ratio (SNR) test results show that the master/slave (M/S) track-and-hold design provides 59 dB of SNR in a 1 GHz bandwidth at input frequencies up to at least 2.6 GHz. A single track-and-hold dissipates 1.5 W while the M/S configuration dissipates 2.5 W.     

A Monolithic 8-Bit Video A/D Converter

A monolithic 8-bit two-step flash type A/D converter has been designed. To obtain full resolution and good linearity at high frequencies, a double folding analog signal processing system is used. Delay time errors between the coarse and the fine quantizes used can be corrected for in this system. An on-chip input amplifier allows adjustment of the input sensitivity with a high input impedance and a low input capacitance. the 3 x 4.2 mm/sup 2/ chip made in a standard bipolar technology consumes 100 mA from a 5.2 V supply.     

A fast, latching comparator for 12 bit A/D applications

High-speed, 12 bit accurate successive approximation A/D converters demand a comparator with both excellent input specifications and fast response time. The author describes a voltage comparator with 50 ns response time to 1/2 LSB overdrive (1.2 mV) and 0.1 LSB (250 /spl mu/V) total input error. Unique features of the circuit include a super-/spl beta/ input stage, a fast buried-zener level-shift, a fully differential output stage, a floating-zener biasing scheme, and a fast latch circuit which does not interfere with input accuracy. The comparator is manufactured on a bipolar, double-implanted, thin epi, junction-isolated process.     

A 10-Gb/s 16:1 multiplexer and 10-GHz clock synthesizer in0.25-μm SiGe BiCMOS

A 10-Gb/s 16:1 multiplexer, 10-GHz clock generator phase-locked loop (PLL), and 6 × 16 b input data buffer are integrated in a 0.25-μm SiGe BiCMOS technology. The chip multiplexes 16 parallel input data streams each at 622 Mb/s into a 9.953-Gb/s serial output stream. The device also produces a 9.953-GHz output clock from a 622- or 155-MHz reference frequency. The on-board 10-GHz voltage-controlled oscillator (VCO) has a 10% tuning range allowing the chip to accommodate both the SONET/SDH data rate of 9.953 Gb/s and a forward error correction coding rate of 10.664 Gb/s. The 6 × 16 b input data buffer accommodates ±2.4 ns of parallel input data phase drift at 622 Mb/s. A delay-locked loop (DLL) in the input data buffer allows the support of multiple input clocking modes. Using a clock generator PLL bandwidth of 6 MHz, the 9.953-GHz output clock exhibits a generated jitter of less than 0.05 UI_P-P over a 50-kHz to 80-MHz bandwidth and jitter peaking of less than 0.05 dB     

A Current-Mode Circuit With a Linearized Input V/I Conversion Scheme and the Realization of a 2-V/2.5-V Operational, 100-MS/s, MOS SHA

This paper proposes a circuit to linearize the signal current and improve the distortion characteristics at the input of a current-mode circuit. Input voltage-to-current (V/I) conversion is carried out by a resistor that connects the signal source and the current input terminal of the current-mode circuit. The signal current flowing into the current-mode circuit through this resistor is distorted because of the signal-dependent voltage change at the current input terminal, and it is linearized by injecting a current that is proportional to the signal-dependent voltage change at the current input terminal, into the same current input terminal of the current-mode circuit. A current-mode sample-and-hold amplifier (SHA) that adopts the proposed scheme was fabricated and a 0.35-$mu{hbox {m}}$ CMOS process was used to verify the effectiveness of the scheme. It operated from a 2-V supply voltage in the analog part and a 2.5 V in the digital part with a 100-MHz clock and realized a 77- and a 86-dB spurious-free dynamic range values for 0 and $-$10 dB of full-scale signal current level $(pm hbox{100} mu{hbox {A}})$, respectively, of the 1-MHz signal input. More than a 13-bit equivalent SFDR for $-$14 to $-$4 dB of full-scale input was obtained, proving the effectiveness of the proposed scheme at realizing distortionless signal current processing.      

一种基于BiFET工艺的高输入阻抗运算放大器

针对CMOS运算放大器存在的输入失调电压高、噪声性能差等问题,提出了一种基于双极结型场效应晶体管(BiFET)工艺的高输入阻抗运算放大器。采用P沟道JFET差分对作为输入级,实现了pA量级的极低输入偏置电流/失调电流和nV/Hz量级的极低输入噪声电压谱密度。采用双极晶体管构成的共集-共射增益级和互补推挽输出级,实现了100 dB的开环增益、10 V/μs的输出电压转换速率和10 MHz的带宽。该运算放大器适用于对微弱模拟信号的采集和放大。     

Yield and speed optimization of a latch-type voltage sense amplifier

A quantitative yield analysis of a latch-type voltage sense amplifier with a high-impedance differential input stage is presented. It investigates the impact of supply voltage, input DC level, transistor sizing, and temperature on the input offset voltage. The input DC level turns out to be most significant. Also, an analytical expression for the sensing delay is derived which shows low sensitivity on the input DC bias voltage. A figure of merit indicates that an input dc level of 0.7 V/sub DD/ is optimal regarding speed and yield. Experimental results in 130-nm CMOS technology confirm that the yield can be significantly improved by lowering the input DC voltage to about 70% of the supply voltage. Thereby, the offset standard deviation decreases from 19 to 8.5 mV without affecting the delay.     

SW3424电源电压监控保护电路的设计与应用

本文介绍并分析了一种电源电压监控保护电路的工作原理及应用。该保护电路采用了双通道输入／双通运输出。输入比较器有较宽的共模电压范围，有可编程磁滞输入和可编程输入／输出延时。输出采用了大电流驱动输出和显示输出。本文给出了其主要性能指标、典型应用连接图及需注意的问题。该电路可广泛用于航空、航天、雷达、通信及精密仪器等领域。     

Polarity coincidence correlation detection of a weak noise source

One application of sample polarity coincidence correlation to the detection of a weak noise source in background noise is briefly described. Assuming an input SNR much less than one, and Gaussian input signals and noise with identical normalized power spectra, expressions for the output SNR are derived for the analog and the polarity coincidence correlator, with and without sampling. The loss in attainable SNR due to clipping and sampling is computed for three different input spectra, viz.; white noise which is passed through an RC low-pass filter, a single-tuned band-pass filter or a rectangular filter. The resulting loss is given in three diagrams, as a function of relative bandwidth of the input signal and sampling frequency. For broad-band input signals the loss is between10and1db, and between4and1db for narrow-band signals.     

Active input-voltage and load-current sharing in input-series and output-parallel connected modular DC-DC converters using dynamic input-voltage reference scheme

This paper explores a new configuration for modular DC/DC converters, namely, series connection at the input, and parallel connection at the output, such that the converters share the input voltage and load current equally. This is an important step toward realizing a truly modular power system architecture, where low-power, low-voltage, building block modules can be connected in any series/parallel combination at input or at output, to realize any given system specifications. A three-loop control scheme, consisting of a common output voltage loop, individual inner current loops, and individual input voltage loops, is proposed to achieve input voltage and load current sharing. The output voltage loop provides the basic reference for inner current loops, which is modified by the respective input voltage loops. The average of converter input voltages, which is dynamically varying, is chosen as the reference for input voltage loops. This choice of reference eliminates interaction among different control loops. The input-series and output-parallel (ISOP) configuration is analyzed using the incremental negative resistance model of DC/DC converters. Based on the analysis, design methods for input voltage controller are developed. Analysis and proposed design methods are verified through simulation, and experimentally, on an ISOP system consisting of two forward converters.     

Constant-g/sub m/ constant-slew-rate high-bandwidth low-voltage rail-to-rail CMOS input stage for VLSI cell libraries

This paper introduces a general-purpose low-voltage rail-to-rail input stage suitable for analog and mixed-signal applications. The proposed circuit provides, simultaneously, constant small-signal and large-signal behaviors over the entire input common-mode voltage range, while imposing no appreciable constraint for high-frequency operation. In addition, the accuracy of the circuit does not rely on any strict matching of the devices, unlike most of the traditional approaches based on complementary input pairs, which need to compensate for the difference in mobility between electrons and holes with the transistor aspect ratios. Also, the technique is compatible with deep submicrometer CMOS devices, where the familiar voltage-to-current square law in saturation is not completely satisfied. Based on the proposed input stage, a transconductor with rail-to-rail input common-mode range and an input/output rail-to-rail operational amplifier were developed. Both cells were designed to operate with a 3-V single supply and fabricated in standard 0.8-/spl mu/m CMOS technology. Experimental results are provided.