电流型汉明神经网络的设计

本文提出了两种新的电流型汉明神经网络电路。第一种风络包括电流型模板匹配电路和全互连的电流型求大网络，结构简单，没有时钟模拟显示该电路具有高速度、高精度和低功耗等特点。在该电路的基础上，又提出了一种采用电流型模板匹配电路和电压型求大网络的汉明神经网络电路，同样具有上述特点。     

A Current-Mode Hysteretic Winner-take-all Network, with Excitatory and Inhibitory Coupling

Winner-take-all (WTA) circuits are commonly used in a wide variety of applications. One of the most used current-mode WTA designs is the one originally proposed by Lazzaro et al. [1]. Several extensions to this design have been suggested in the past. In this paper we present a variant of this current-mode WTA circuit, containing all of the enhancements previously proposed, together with new additional modifications that endow it with interesting hysteretic and lateral inhibition and excitation properties. We compare the performance of this WTA circuit to the original WTA design, providing experimental data obtained from a VLSI chip containing both types of circuits, designed using closely matched layouts. We derive analytically the response properties of the circuit's lateral diffusion network, pointing out the differences to previously proposed diffusion networks, and present experimental data confirming the theoretical predictions. We also describe application domains that can best exploit these types of hysteretic WTA circuits.     

Min-net winner-take-all CMOS implementation

A charge-based winner-take-all (WTA) circuit is proposed. This WTA circuit is a min-net capable of selecting the minimum value among its input nodes and gives only one low voltage for the corresponding output node. The charge-based circuit uses a power supply of 3 V, with low power dissipation due to the lack of static DC current involved. The WTA circuit is used in associative neural networks.<>     

A MODEL OF NEURAL CIRCUIT WITH ADAPTION AND NONLINEAR CONNECTION

Based on physiological properties of synapse, soma and axon, this paper presents and analyses a model of neural circuit which can approximately simulate input-output relation, strength-duration curve, adaption and nonlinear connection of real neuron. The obtained results show that the model approximates to realistic principles of neural computation better than the available neural networks. The impulse-coded WTA(winner takes all) networks constructed with the above model find the winner more effectively than the analog WTA. Finally, the two important concepts: time competition and strength competition are introduced, which illustrate that the model has abilities to perform series and parallel information processing.     

Winner-Take-All Networks with Lateral Excitation

In this paper we present two analog VLSI circuits thatimplement current mode winner-take-all (WTA) networks with lateralexcitation. We describe their principles of operation and comparetheir performance to previously proposed circuits. The desirableproperties of these circuits, namely compactness, low power consumption,collective processing and robustness to noisy inputs make themideal for system level integration in analog VLSI neuromorphicsystems. As application example, we implemented a circuit thatemploys an adaptive photoreceptor array as the input stage tothe WTA network for edge enhancement.     

Sub 0.5-V bulk-driven winner take all circuit based on a new voltage follower

A new solution for a bulk-driven ultra-low-voltage winner take all (WTA) circuit is described. The WTA structure is based on a new voltage follower (VF) circuit which could also be used in other applications as a general purpose precise VF for sub 0.5-V operation. Both proposed circuits are compact and provide precision operation confirmed by theoretical analysis.     

Single-electron winner-take-all network

A winner-take-all (WTA) single-electron neuron is developed for the first time. This new single-electron circuit is proposed in order to implement a WTA neural network with lateral inhibition architecture. An expression for the neuron's activation function is presented. Furthermore, a dot pattern recognition task is successfully performed by the implemented network considering effects such as offset charges and co-tunnelling.     

A Normalizing aVLSI Network with Controllable Winner-Take-All Properties

We describe an aVLSI network consisting of a group of excitatory neurons and a global inhibitory neuron. The output of the inhibitory neuron is normalized with respect to the input strengths in a manner that is useful in any system where we wish the output signal to code only the strength of the inputs, and not be dependent on the number of active inputs. The circuitry in each neuron is equivalent to that in Lazzaro's winner-take-all (WTA) circuit [1] with one additional transistor and a voltage reference. As in Lazzaro's circuit, the outputs of the excitatory neurons code for the neuron with the largest input. The novel feature is that multiple winners can be chosen (soft-max). By varying one parameter, the network can operate in a soft-max regime or a WTA regime. We show results from two different fabricated networks.     

异步并行蚂蚁策略在网络化舰艇编队武器目标分配中的应用

武器目标分配(WTA)是现代海上编队防空作战的关键技术之一,其目标是合理利用网络化舰艇编队内各项资源,对来袭目标进行拦截,以求拦截效果最优。引入了综合毁伤阈值和综合毁伤矩阵的概念,提出了一种基于异步并行蚂蚁策略的目标分配新方法,并建立分配模型,最后以实例仿真验证了方法的可行性。     

融合多属性决策和深度Q值网络的反导火力分配方法

针对中大规模武器-目标分配(WTA)决策空间复杂度高、求解效率低的问题,该文提出一种基于多属性决策和深度Q网络(DQN)的WTA优化方法。建立基于层次分析法(AHP)的导弹威胁评估模型,引入熵值法表征目标属性差异,提升威胁评估客观性。根据最大毁伤概率准则,建立基于DQN的WTA分段决策模型,引入经验池均匀采样策略,确保各类目标分配经验的等概率抽取;设计综合局部和全局收益的奖励函数,兼顾DQN火力分配模型的训练效率和决策准确性。仿真结果表明,相较于传统启发式方法,该方法具备在线快速求解大规模WTA问题的优势,且对于WTA场景要素变化具有较好的鲁棒性。     

On Noninterruptive Rearrangeable Networks

In this paper, we study a new class of nonblocking networks called noninterruptive rearrangeable (NIR) networks, which are rearrangeable under the additional condition that existing connections are not interrupted while their paths being possibly rerouted to accommodate a new request. We give a complete characterization of NIR Clos networks built of switching elements of various nonblocking properties. In particular, we propose a novel class of NIR Clos networks that leads to recursive constructions of various cost-efficient multistage NIR networks. Finally, we present examples of such constructions and compare them with the best previously known results.     

Associative IC memories with relational search and nearest-matchcapabilities

The authors present the design and implementation of content addressable memories (CAMs) that execute relational and nearest-match instructions. Implementation of a novel relational search cell is presented. Direct performance comparison shows an order-of-magnitude improvement over existing designs with similar cell area. The design and implementation of a neural-inspired nearest-match CAM using a winner-take-all (WTA) network is presented. An original approach to analyzing such neural-inspired CAMs is presented. A model which describes the behavior of the WTA network is derived to be utilized in the design and performance prediction of the network. Performance of the WTA network in differentiating between words with large bit mismatches is analyzed, and an upper bound is set. Fully functional prototype chips have been fabricated through MOSIS using 2-μm double-metal CMOS technology. Theoretical, simulation, and physical chip measurements are in good agreement     

事件驱动的动态武器目标分配研究

动态武器目标分配（Weapon Target Assignment,WTA）问题是军事运筹学研究的重要理论问题,也是防空作战中迫切需要解决的问题。根据防空作战中事件对动态WTA问题的影响。提出了基于事件驱动的动态WTA的改进蚁群算法。通过处理事件,动态地调整蚁群算法的参数,使武器目标分配方案反映事件的影响。并根据当前最...     

Compact associative-memory architecture with fully parallel searchcapability for the minimum Hamming distance

An associative-memory architecture for a fully parallel minimum Hamming distance search is proposed, which uses digital circuitry for bit comparison and fast analog circuitry for word comparison as well as winner-take-all (WTA) functionality. Following this original approach allows compact and high-performance integration in conventional CMOS technology. First, static encoding of word-comparison results as a current-sink capability reduces word-comparison circuitry to the theoretical minimum, namely, one transistor per bit and one signal line per word. Second, a new WTA principle, which we call self-adapting winner line-up amplification (WLA), regulates the winner row output automatically into the narrow maximum-gain region of a distance amplifier. Third, winner search circuit complexity scales linear with reference-word number and not quadratic as inevitable for digital approaches. Due to static distance encoding and WLA regulation, transient noise and fabrication process variations are largely tolerated. Only relative chip-internal transistor-parameter variations, creating effective mismatch of matched transistors, limit winner search result correctness. Practical feasibility is verified     

具有旋转不变性的二值化的互连权重研究

采用线性组合Ｃｌｉｐｐｅｄ方法得到初始的具有旋转不变性的ＷＴＡ模型输入层与中间层间的二值互连权重，并利用局部ＭｏｎｔｅＣａｒｌｏ方法对权值进行优化提高系统的正确识别率，以４类飞行目标进行了计算机模拟，实验结果表明此模型用于识别旋转目标是可行的，还提出一个实现此模型的光电混合系统。     

Normal Transmission-Line Networks and Their Lumped LC Presentation

A previous result is extended and a new presentation is described for Richards' transmission-line (TL) networks. The new presentation is in a lumped LC form; therefore, classical analysis and synthesis techniques are directly applicable. The class of networks for which this presentation is possible is studied in detail. This class of networks, called normal TL networks, is found to be a necessary and sufficient condition for driving-point immittance functions to be rational positive real functions of /spl lambda/ =tanh /spl tau//spl rho/. The effectiveness of this representation is further demonstrated by applying it to graph-transformation analysis method. It simplifies the procedure considerably and reveals additional physical insight into the TL network.     

An APS with 2-D winner-take-all selection employing adaptive spatial filtering and false alarm reduction

An active pixel sensor (APS) with two-dimensional winner-take-all (WTA) detection is presented. This system-on-a-chip employs adaptive spatial filtering of the processed image, with bad pixel elimination and false alarm reduction in case of a missing object. The circuit has a unique ability of adaptive spatial filtering that allows removal of the background from the image, one stage before it is transferred to the WTA detection circuit. A test chip of a 64/sup */64 array has been implemented in 0.5-/spl mu/m CMOS technology, has a 49% fill factor, is operated by a 3.3-V supply, and dissipates 36 mW at video rate. System architecture and operation are discussed and measurements from the prototype chip are presented.     

On the blocking performance of EGS networks under multicast traffic

Extended generalized shuffle (EGS) networks are a wide class of interconnection networks introduced by Richards (1993). In this work, we study the blocking performance of EGS networks under point-to-multipoint traffic. Two new routing algorithms for multicast connections in EGS networks are defined, and a theorem proving that these algorithms construct minimum-cost connection trees is enclosed. Simulation results show that the blocking performance of EGS networks under multicast traffic is much better than that of three-stage Clos networks of equal complexity     

具时延的细胞神经网络的全局渐近稳定性分析

本文通过Lyapunov泛函方法和新的不等式a2b(2a3+b3)/3,(a,b0)分析技巧,讨论了一类具时延的细胞神经网络DCNN全局渐近稳定性问题,得到了若干新的充分判据,这些判据可用于设计出各种全局稳定的网络。