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一种CMOS动态闩锁电压比较器的优化设计 总被引:3,自引:0,他引:3
提出了一种应用于Pipeline ADC和Sigma-Delta ADC中改进的动态闩锁电压比较器。采用0.35μm CMOS N阱工艺设计,工作于2.5V单电源电压。通过详细的分析和优化,使比较器具有较小的输入失调电压和踢回噪声,仿真结果表明它的输入失调电压分布范围为28.6mV,最高工作频率200MHz、功耗230μW。 相似文献
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提出了一种应用于逐次逼近模数转换器的高速高精度比较器。该比较器由2级预放大器、1级锁存比较器以及缓冲电路构成。在前置预放大器中采用共源共栅结构、复位和箝位技术,提高了比较器的精度和速度,降低了功耗。在锁存比较器中引入额外的正反馈路径,提高了响应速度,降低了功耗。将锁存比较器输入对管与锁存结构隔离,降低了踢回噪声的影响,提高了比较器的精度。比较器基于SMIC 0.18 μm CMOS工艺进行设计与仿真。仿真结果表明,在1.8 V电源电压、800 MHz时钟下,比较器的精度为50 μV,传输延迟为458 ps,功耗为432 μW,芯片面积仅为0.009 mm2。 相似文献
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为满足10位高分辨率A/D转换器的需要,设计了一种高速高精度钟控电压比较器,着重对其速度和回馈噪声进行了分析与优化.该比较器采用前置预放大器结构实现了高比较精度,利用两级正反馈环路结构的比较锁存器提高了比较器的速度,隔离技术和互补技术的应用实现了低回馈噪声.基于TSMC 0.18 μm CMOS标准工艺,用Ca-dence Spectre模拟器进行仿真验证,结果表明比较器的工作频率可达300 MHz,LSB(Least Significant Bit)为±1 mV,传输延时为360 ps,功耗为2.6 mW,可达到10住的比较精度.该电路可适用于高速高精度模数转换器与模拟IP核的设计. 相似文献
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设计一种中速高精度模拟电压比较器,该比较器采用3级前置放大器加锁存器和数字触发电路的多级结构,应用失调校准技术消除失调,应用共源共栅结构抑制回程噪声干扰;应用数字触发电路获得高性能数字输出信号,设计采用0.35μm5VCMOS工艺实现一个输入电压2.5V、速度1MS/s、精度12位的逐次逼近型MD转换器。Hspice仿真结果表明:在5V供电电压下,速度可达20MHz,准确比较0.2mV电压,有效校准20mV输入失调,功耗约1mW。 相似文献
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一种中速高精度模拟电压比较器的设计 总被引:1,自引:0,他引:1
设计一种中速高精度模拟电压比较器,该比较器采用3级前置放大器加锁存器和数字触发电路的多级结构,应用失调校准技术消除失调,应用共源共栅结构抑制回程噪声干扰;应用数字触发电路获得高性能数字输出信号,设计采用0.35μm 5 V CMOS工艺实现一个输入电压2.5 V、速度1 MS/s、精度12位的逐次逼近型A/D转换器.Hspice仿真结果表明:在5 V供电电压下,速度可达20 MHz,准确比较0.2 mV电压,有效校准20 mV输入失调,功耗约1 mW. 相似文献
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基于预放大锁存快速比较理论,提出了一种高速高精度CMOS比较器的电路拓扑.该比较器采用负载管并联负电阻的方式提高预放大器增益,以降低失调电压.采用预设静态电流的方式提高再生锁存级的再生能力,以提高比较器的速度.在TSMC0.18μm工艺模型下,采用Cadence Specture进行仿真.结果表明,该比较器在时钟频率为1GHz时,分辨率可以达到0.6mV,传输延迟时间为320ps,功耗为1mW. 相似文献
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The accuracy of A/D and D/A converters depend largely upon their inner comparators. To guarantee 12-bit high resolution for an A/D converter, a precise CMOS comparator consisting of a three-stage differential preamplifier together with a positive feedback latch is proposed. Circuit structure, gain, the principle of input offset voltage storage and latching time constant for the comparator will be analyzed and optimized in this article. With 0.5 μm HYNIX mixed signal technology, the simulation result shows that the circuit has a precision of 400 μV at 20 MHz. The test result shows that the circuit has a precision of 600 μV at 16 MHz, and dissipates only 78 μW of power dissipation at 5 V. The size of the chip is 210 × 180 μm2. The comparator has been successfully used in a 10 MSPS 12-bit A/D converter. The circuit can be also used in a less than 13-bit A/D converter. 相似文献
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比较器的设计对于A/D,D/A转换器的精度至关重要。为了满足12位高分辨率的A/D转换器的需要,设计了一种高精度CMOS比较器,采用三级差分比较和一级动态正反馈的Latch结构实现了高比较精度。论文对该比较器的电路结构,增益,带宽,输入失调消除原理和锁存时间常数进行了分析,并利用Hynix 0.5um CMOS工艺提供的器件模型进行了仿真,在20MHZ频率下,比较器的精度达到了400uV。测试结果显示,在16MHZ频率下,比较器的精度达到了600uV。在电源电压为5V时,功耗为78uw。芯片面积是210um *180um 。该比较器已经成功用于一种10MSPS 12位A/D转换器中。该器件还可以用于13位以下的其他A/D转换器电路。 相似文献
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A high-speed current conveyor based current comparator 总被引:1,自引:0,他引:1
R. Chavoshisani 《Microelectronics Journal》2011,42(1):28-32
In this paper, a new high-speed current mode comparator based on inherent current conveyor and positive feedback properties is presented. This novel approach has resulted in major reduction of the response time and hence a wide band application of the circuit. Simulation results using HSPICE and 0.18 μm CMOS technology with 1.8 V supply confirms a propagation delay of less than 0.4 ns in the high frequency range of 700 MHz with 158 μw power dissipation. Under the above conditions, the accuracy of the input current is as low as 50 nA. 相似文献
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A low power 20 GHz CMOS dynamic latched regeneration comparator for ultra-high-speed, low-power analog-to-digital converters (ADCs) is proposed. The time constant in both the tracking and regeneration phases of the latch are analyzed based on the small signal model. A dynamic source-common logic (SCL) topology is adopted in the master-slave latch to increase the tracking and regeneration speeds. Implemented in 90 nm CMOS technology, this comparator only occupies a die area of 65 × 150 μm^2 with a power dissipation of 14 mW from a 1.2 V power supply. The measurement results show that the comparator can work up to 20 GHz. Operating with an input frequency of 1 GHz, the circuit can oversample up to 20 Giga-sampling-per-second (GSps) with 5 bits resolution; while operating at Nyquist, the comparator can sample up to 20 GSps with 4 bits resolution. The comparator has been successfully used in a 20 GSps flash ADC and the circuit can be also used in other high speed applications. 相似文献