A novel dual p-/p+ poly gate CMOS VLSItechnology

A CMOS VLSI technology using p^- and p⁺ poly gates for NMOS and PMOS devices is presented. Due to the midgap work function of the p^- poly gate, the NMOS native threshold voltage is 0.7 V and, therefore, no additional threshold adjust implantation is required. The NMOS transistor is a surface-channel device with improved field-effect mobility and lower body effect due to the reduction in the channel doping concentration. In addition, the p ^- poly gate is shown to be compatible with p⁺ poly-gated surface-channel PMOS devices     

A novel technique for profiling the lateral n- dopingconcentrations of submicron LDD MOS devices

This paper reports a simple I-V method for the first time to determine the lateral lightly-doped source/drain (S/D) profiles (n^- region) of LDD n-MOSFETs. One interesting result is the direct observation of the reverse-short-channel effect (RSCE). It is observed that S/D n^- doping profile is channel length dependent if reverse short-channel effect exists as a result of the interstitial imperfections caused by Oxide Enhanced Diffusion (OED) or S/D implant. Not only the lateral profiles for long-channel devices but also for short-channel devices can be determined. One other practical application of the present method for device drain engineering has been demonstrated with a LATID MOS device drain engineering work. It is convincible that the proposed method is well suited for the characterization and optimization of submicron and deep-submicron MOSFETs in the current ULSI technology     

A silicon homojunction infrared detector having an active metalfilm on an n++ layer

A silicon n⁺⁺pn homojunction infrared detector, in which a degenerate n⁺⁺ layer is backed by a metal film forming an ohmic contact, has been proposed and studied. The metal film is a photoelectric conversion region along with the n⁺⁺ layer. Although, for an n⁺⁺pn detector without the metal film, very poor rectifying properties are observed when the n⁺⁺ layer thickness is extremely reduced, the new detector, employing a thin PtSi film as the metal film, shows normal diode I-V characteristics, since the PtSi film provides increased surface conductivity. The new detector has achieved an increase in operatable temperature, or an extension of cutoff wavelength, and operated with cutoff wavelengths of 11.9 μm, 18.7 μm and about 30 μm at 70 K, 50 K, and 30 K, respectively, because the saturation current density for the new detector has been reduced to about one tenth that for the previously reported n⁺⁺pn detector. The responsivity for the new detector has increased to 1.1-3.8 times as large as that for the previously reported n⁺⁺pn detector, when both detectors have the same cutoff wavelength     

A mechanism of gate oxide deterioration during As+ ionimplantation

The deterioration or catastrophic breakdown of thin gate oxides during ion implantation is studied. The effect of ion beam density, the distribution of the gate oxide deterioration over a wafer, and the effect of photoresist coverage are shown quantitatively by measuring the number of interface states generated in MOS capacitors. It is shown that the four charge sources contribute to the deterioration of gate oxide: the irradiated ion beam, the secondary electrons emitted from the gate electrode, the charges accumulated on the photoresist surface around the gate electrode, and the secondary electrons emitted from a wafer holder. The first three charges accelerate the deterioration of the gate oxide and the last one reduces it. A model of the gate oxide deterioration in ion implantation that is very useful for finding methods of reducing the charging damage is presented     

An As-P(n+-n-)double diffused drain MOSFET for VLSI's

An As-P(n⁺-n^-) double diffused drain is characterized as one of the most feasible device structures for VLSI's from the overall viewpoint of device design. This device makes good use of both As, suitable for microfabrication, and P, in realizing a graded junction. The feasibility of this double diffused drain is investigated comparing it with a conventional As drain over the wide range of effective channel length from 0.5 to 5 µm. We have also succeeded in directly measuring hot-hole gate current as low as on the order of 10^-15A. This current seems to have an important influence on the hot-carrier effects. On the basis of the experiments and simulations using the two-dimensional process/device analysis programs SUPREM and CADDET, it is shown that this device structure provides remarkable improvements, not only in terms of channel hot-electron effects, but also avalanche hot-carrier effects, which are more responsible for hot-carrier related device degradation due to impact ionization at the drain. In addition, this structure has almost the same short channel effect characteristics, for example threshold-voltage lowering as a conventional MOSFET.     

Plasma damage immunity of thin gate oxide grown on very lightly N+ implanted silicon

Plasma damage immunity of gate oxide grown on very low dose (2×10¹³/cm²) N⁺ implanted silicon is found to be improved compared to a regular gate oxide of similar thickness. Both hole trapping and electron trapping are suppressed by the incorporation of nitrogen into the gate oxide. Hole trapping behavior was determined from the relationship between initial electron trapping slope (IETS) and threshold voltage shifts due to current stress. This method is believed to be far more reliable than the typical method of initial gate voltage lowering during current stress     

Improved stability of short-channel hydrogenated N-channelpolycrystalline silicon thin-film transistors with very thin ECR N2O-plasma gate oxide

Stability has been investigated for short-channel hydrogenated n-channel polycrystalline thin-film transistors (poly-Si TFTs) with very thin (12 nm) electron cyclotron resonance (ECR) N₂O-plasma gate oxide. The TFTs show negligible changes in the electrical characteristics after hot-carrier stresses, which is due to the highly reliable interface and gate oxide. The hydrogenated TFTs with 3-μm gate length TFTs exhibit very small degradation (ΔV_th<15 mV) under hot-carrier stresses and Fowler-Nordheim (F-N) stress (ΔV_th=₈₁ mV, ΔGm/Gm=2.2%, ΔS/S=4.7%)     

A new MOS Type metal tunnel-oxide silicon switch (MOSMISS)

A new MISS device with MOSFET gating is described. The MISS structure employs the thin tunnel oxide to produce the reverse biased field induced drain junction. The quantum mechanical tunneling allows the passage of current and the device to switch to on or off state.     

A model of front-illuminated n+-p-p+high-efficiency silicon solar cell

A realistic model of a front-illuminated n⁺-p-p⁺ silicon solar cell is developed by solving the current continuity equations for minority carriers in the quasi-neutral regions in steady state, assuming the light in the cell is trapped as a result of multiple reflections at the front and the back of the cell. This model is used to study the effects of the front emitter thickness and doping level and the light trapping on the J-V characteristic and thereby on the open-circuit voltage, short-circuit current density, curve factor, and the efficiency of the cell. A textured cell with an emitter thickness in the range of 0.3-1.0 μm with its doping ≈5×10¹⁸ cm^-3 and the recombination velocities of minority carriers as large as 200 cm/s at the n⁺ front surface and 10 cm/s at the back of the p base can exhibit an efficiency in excess of 26% (under AM 1.5 sunlight of 100 mW/cm² intensity) at 25°C if the light reflection losses at the front surface can be made small     

MBE grown n+-i-δ(p+)-i-n+GaAs V-groove barrier transistor

The three-terminal n⁺-i-δ(p⁺)-i-n⁺V-groove barrier transistor (VBT) has been successfully fabricated by molecular beam epitaxy (MBE). The base terminal is connected to the δ(p⁺), the thin p⁺layer, by depositing aluminum on the etched V-groove. The demonstrated device possesses high potential of ultra-high-frequency (f_{r} > 30-GHz), high-power, and low-noise capability due to carriers transporting by thermionic emission and being controlled by the base-emitter bias.     

MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8nm)

An equivalent circuit approach to MOS capacitance-voltage (C-V) modeling of ultrathin gate oxides (1.3-1.8 nm) is proposed. Capacitance simulation including polysilicon depletion is based on quantum mechanical (QM) corrections implemented in a two-dimensional (2-D) device simulator; tunneling current is calculated using a one-dimensional (1-D) Green's function solver. The sharp decrease in capacitance observed for gate oxides below 2.0 nm in both accumulation and inversion is modeled using distributed voltage-controlled RC networks. The imaginary components of small-signal input admittance obtained from AC network analysis agree well with measured capacitance     

A self-aligned gate superlattice (Al,GA)As/n+-GaAs MODFET 5 × 5-bit parallel multiplier

A 5 × 5-bit parallel multiplier circuit has been demonstrated with self-aligned gate superlattice (Al,Ga)As/n+-GaAs modulation-doped FET's (MODFET's). Multiplication times (gate delays) and corresponding power dissipations of 1.80 ns (73 ps/gate) at 0.43 mW/gate and 1.08 ns (43 ps/gate) at 0.75 mW/gate were measured at room temperature and 77 K, respectively. These are the shortest gate propagation delays ever reported for parallel multiplier circuits at room temperature or 77 K using any semiconductor IC technology.     

(100) and (111) Si MOS transistors fabricated with low growthtemperature (400°C) gate oxide by Kr/O2 microwave-excitedhigh-density plasma

A drastic reduction in the growth temperature (400°C) of highly reliable SiO₂ gate oxides grown by a Kr/O₂ microwave-excited high-density plasma technique is shown to yield MOS I-V characteristics comparable to those obtained in transistors with conventionally grown dry gate oxides at 900°C. The benefits of this technique are summarized     

Characteristics of metal-oxide-semiconductor (MOS) device with Er metal gate on SiO2 film

We have investigated the structural and electrical properties of metal-oxide-semiconductor (MOS) devices with Er metal gate on SiO₂ film. Rapid thermal annealing (RTA) process leads to the formation of a high-k Er-silicate gate dielectric. The in situ high-voltage electron microscopy (HVEM) results show that thermally driven Er diffusion is responsible for the decrease in equivalent oxide thickness (EOT) with an increase in annealing temperature. The effective work function (Φ_m,eff) of Er metal gate, extracted from the relations of EOT versus flat-band voltage (V_FB), is calculated to be ∼2.86 eV.     

Impact of nitrogen (N2+) implantation intopolysilicon gate on thermal stability of cobalt silicide formed onpolysilicon gate

A novel process which uses N₂⁺ implantation into polysilicon gates to suppress the agglomeration of CoSi₂ in polycide gated MOS devices is presented. The thermal stability of CoSi₂/polysilicon stacked layers can be dramatically improved by using N₂⁺ implantation into polysilicon. The sheet resistance of the samples without N₂⁺ implantation starts to increase after 875°C RTA for 30 s, while the sheet resistance of CoSi₂ film is not increased at all after 950 and 1000°C RTA for 30 s if the dose of nitrogen is increased up to 2×10¹⁵ cm^-2 and 6×10¹⁵ cm², respectively, and TEM photographs show that the agglomeration of CoSi₂ film is completely suppressed. It is found that the transformation to CoSi₂ from CoSi is impeded by N₂⁺ implantation such that the grain size of CoSi₂ with N₂⁺ implantation is much smaller than that without N₂⁺ implantation. As a result, the thermal stability of CoSi₂ is significantly improved by N₂⁺ implantation into polysilicon     

A physically based compact gate C-V model for ultrathin (EOT /spl sim/1 nm and below) gate dielectric MOS devices

A computationally efficient and accurate physically based gate capacitance model of MOS devices with advanced ultrathin equivalent oxide thickness (EOT) oxides (down to 0.5 nm explicitly considered here) is introduced for the current and near future integrated circuit technology nodes. In such a thin gate dielectric regime, the modeling of quantum-mechanical (QM) effects simply with the assumption of an infinite triangular quantum well at the Si-dielectric interface can result in unacceptable underestimates of calculated gate capacitance. With the aid of self-consistent numerical Schro/spl uml/dinger-Poisson calculations, the QM effects have been reconsidered in this model. The 2/3 power law for the lowest quantized energy level versus field relations (E/sub 1//spl prop/F/sub ox//sup 2/3/), often used in compact models, was refined to 0.61 for electrons and 0.64 for holes, respectively, in the substrate in the regimes of moderate to strong inversion and accumulation to address primarily barrier penetration. The filling of excited states consistent with Fermi statistics has been addressed. The quantum-corrected gate capacitance-voltage (C-V) calculations have then been tied directly to the Fermi level shift as per the definition of voltage (rather than, for example, obtained indirectly through calculation of quantum corrections to the charge centroids offset from the interface). The model was implemented and tested by comparisons to both numerical calculations down to 0.5 nm, and to experimental data from n-MOS or p-MOS metal-gate devices with SiO/sub 2/, Si/sub 3/N/sub 4/ and high-/spl kappa/ (e.g., HfO/sub 2/) gate dielectrics on (100) Si with EOTs down to /spl sim/1.3 nm. The compact model has also been adapted to address interface states, and poly depletion and poly accumulation effects on gate capacitance.     

NCl(a~1Δ)自猝灭对NCl(a~1Δ)/I激光能量提取的影响

利用连续流平面型光腔动力学模型对NCl(a1Δ)/I 激光体系进行了模拟计算,探讨了温度在300 K 时NCl(a1Δ)自猝灭对NCl(a1Δ)/I激光能量提取的影响。计算结果表明,NCl(a1Δ)自猝灭反应对光腔位置的选取、功率密度沿流动方向的分布和总输出功率都有较大的影响。其中,光腔位置的可选范围大大缩短,在较小的初始HI粒子数密度和适当的输出镜反射率下总输出功率大幅度降低,而随着HI粒子数密度的增加,NCl(a1Δ)自猝灭对总输出功率的影响逐渐减小。     

Forward current—Voltage and switching characteristics of p+-n-n+(epitaxial) diodes

The forward-biased current-voltage and forward-to-reverse biased switching characteristics of p⁺-n-n⁺epitaxial diodes are investigated. The manner in which the n-n⁺junction affects the flow of injected minority carriers in the epitaxial region is characterized by a leakage parameter a. Experimentally, for diodes with epitaxial film widths much less than a diffusion length, a "box" profile accurately describes the injected minority carriers in the n region. The current is found to increase with increased epitaxial width at a fixed bias. A general switching expression for epitaxial diodes is presented and the validity of the expression is shown experimentally. The experimental values of a, determined independently from the current-voltage and switching characteristics, are in good agreement and show that the leakage of the high-low junction is dominated by the recombination of minority carriers in the n-n⁺space-charge region.     

Epitaxial strontium oxide layers on silicon for gate-first and gate-last TiN/HfO2 gate stack scaling

We show that a thin epitaxial strontium oxide (SrO) interfacial layer enables scaling of titanium nitride/hafnium oxide high-permittivity (high-k) gate stacks for field-effect transistors on silicon. In a low-temperature gate-last process, SrO passivates Si against SiO₂ formation and silicidation and equivalent oxide thickness (EOT) of 5 Å is achieved, with competitive leakage current and interface trap density. In a gate-first process, Sr triggers HfO₂-SiO₂ intermixing, forming interfacial high-k silicate containing both Sr and Hf. Combined with oxygen control techniques, we demonstrate an EOT of 6 Å with further scaling potential. In both cases, Sr incorporation results in an effective workfunction that is suitable for n-channel transistors.