MPSoC上的NoC通信架构的实现

本文介绍了片上网络的相关概念,采用2D Mesh拓扑结构和XY路由算法,实现了一款用于构建MPSoC的片上网络.通过在EDK中构建4个MicroBlaze核的处理器,并用片上网络进行连接,最终在XUP Virtex-ⅡPro FPGA开发板上验证了片上网络的正确性.     

片上网络节点编码的设计和在路由方面的应用

网络拓扑选择和路由算法设计是片上网络设计的关键问题.在比较现有的三种网络拓扑结构的基础上,提出了一种隐含着相邻节点以及节点之间链路关系并适合二维Torus拓扑结构的节点编码方法.该编码和Torus结构的结合能拓扑结果够简化路由算法的设计和实现,改善了网络路由性能.实验结果表明,提出的编码方法与二维Torus拓扑结构的结合有效地提高了片上网络通信性能.     

片上网络关键技术及仿真方法研究

片上网络(NoC)的研究借鉴了计算机网络的设计思想,将计算机网络技术移植到芯片设计中来.介绍了片上网络的关键技术和仿真方法,包括拓扑结构、路由与交换协议、流量控制、缓存设计、性能评估与仿真等,并对今后的研究做出了展望.     

针对片上网络组播通信模型的设计与仿真

文章提出了一种针对片上网络的组播通信模型,能够为片上网络提供无死锁的通信.该模型能显著减少总通信量,增加通道利用率;在测试模式下,能有效节省测试时间.将该模型仿真应用到二维带环网格拓扑结构的片上网络中,试验结果表明,该模型较单播通信具有更小的平均传输延迟和更高的吞吐量.     

一种自适应动态缓存策略准入控制算法

针对片上网络的死锁问题,基于虚拟网络的自适应路由算法,设计了一个完全自适应片上路由器.重点介绍了路由算法及路由器的系统结构,设计实现了一个低代价、高效的完全自适应路由器,并在2DMesh拓扑结构下对其性能进行了模拟验证.实验结果表明,该路由器实现了无死锁的自适应路由,并提高了网络吞吐量,降低了平均网络延迟.     

一种3D Octagon双环片上网络拓扑结构

随着片上网络IP核结点的增加,芯片面积受限的问题日益突出,利用39拓扑,用体积换取芯片面积是一种可行的方案,这种结构使各个结点的物理距离更近,从而充分地利用了空间资源,可以有效地减少芯片面积.提出一种3D Octagon双环拓扑结构,在均衡负载模式和对称随机负载模式下分析了其网络延迟和吞吐率.结果表明,3D Octagon双环是一种性能良好、可行性高的片上网络拓扑结构.     

一种分层结构的片上网络路由设计

随着同一芯片中处理器数日的不断增加,层次化网络结构将成为片上网络(NoC)拓扑研究的热点.针对典型的NoC不规则分层拓扑结构,设计了一套新的免死锁混合路由算法以及新的节点编址方式.同时提出了一种新的交换节点设计构想,并给出了一种有效的拥塞控制策略.仿真结果表明,当网络中数据流量变大时分层网络比传统二维网络具有更小的传输时延以及更大的吞吐量.     

一种完全自适应片上路由器的设计

针对片上网络的死锁问题,文中根据所提出的完全自适应路由思想—基于虚拟网络的自适应路由算法,设计了一个完全自适应片上路由器.重点介绍了路由算法及路由器的系统结构,最终设计实现了一个高效、低代价的完全自适应路由器,并在2D Mesh拓扑结构下对其性能进行了模拟验证.实验得出该路由器实现了无死锁的自适应路由,并降低了平均网络延迟,提高了网络吞吐量.     

基于共享缓存的三维片上网络的功耗建模及分析

片上网络是为应对未来片上通信架构各种挑战而提出的一种新型解决方案。三维芯片技术相对于二维结构可以实现更高的集成度,更优越的性能,如混合集成和低延时。用于垂直互联的硅通孔技术,可以降低水平长互联线的长度,进而实现低延时、低功耗。本文根据具体的硅通孔的电容模型建立了三维网状片上网络的功耗模型。该模型可用于片上网络设计早期阶段的评估,实现快速的功耗预测。本文根据具体的尺寸信息选择了两种三维网状片上网络结构,分别具有一层和两层存储单元。仿真结果表明,在注入率为0.35的情况下,两种三维网状片上网络与传统的二维网状片上网络相比,功耗分别降低了14%和26.96%。     

无缓存片上网络的研究

对芯片面积、能耗上的严格限制是片上网络与宏观网络的最大不同。片上网络路由器中的缓存占用了大量的芯片面积和功耗,因此无缓存片上网络得到广泛关注。它完全去掉路由器内的缓存,通过偏转未获得有效端口的微片,处理微片对输出端口的竞争。本文对无缓存偏转网络的原理及关键技术进行了研究,包括拓扑结构、仲裁策略等。最后,通过与有缓存网络的对比,对无缓存网络的优势与劣势进行了总结。     

3D NOC for many-core processors

With an increasing number of processors forming many-core chip multiprocessors (CMP), there exists a need for easily scalable, high-performance and low-power intra-chip communication infrastructure for emerging systems. In CMPs with hundreds of processing elements, 3D integration can be utilized to shorten long wires forming communication links. In this paper, we propose a Clos network-on-chip (CNOC) in conjunction with 3D integration as a viable network topology for many core CMPs. The primary benefit of 3D CNOC is scalability and a clear upper bound on power dissipation. We present the architectural and physical design of 3D CNOC and compare its performance with several other topologies. Comparisons are made among several topologies (fat tree, flattened butterfly, mesh and Clos) showing the power consumption of a 3D CNOC increases only minimally as the network size is scaled from 64 to 512 nodes relative to the other topologies. Furthermore, in a 512-node system, 3D CNOC consumes about 15% less average power than any other topology. We also compare 3D partitioning strategies for these topologies and discuss their effect on wire delay and the number of through-silicon vias.     

芯片散热微通道仿生拓扑结构研究

为提升高热流密度芯片的散热能力,借鉴自然界中众多具有优良传质传热特性的网络拓扑,设计了多种仿生微通道拓扑结构.利用数值模拟方法,分析了不同拓扑结构的散热效果及压降特性,结果表明不同拓扑结构的散热能力存在一定差异,且芯片热流密度越高差异越明显.对数值分析中综合性能优秀的蜘蛛网结构的散热特性进行了理论分析,并通过3D打印加工了微通道散热器,测试表明其散热能力和压降相对现有平直微通道均有明显提高.     

Performance centric design of subnetwork-based diagonal mesh NoC

Performance of NoC relies heavily on underlying interconnect network and related message forwarding technique. Here, Mesh is an obvious network choice by the designer due to its regular grid-based structure, making it easy to implement in chip surface. However, mesh suffers from degrading network performance issue in large-scale dimension due to the increasing hop count that leads to both congestion and link contention at the same time. Conventional topologies like Folded Torus, Butterfly-fat-tree (BFT) and recently proposed topologies like Flattened BFT, Sc-mesh and SD2D mesh topologies are mostly relying on express bypass links to mitigate this limitation in large-scale dimension. Proposed work presents a low latency oriented diagonally linked network that combines both 2 × 2 and a 1 × 1 diagonal links over the generic mesh connection to shorten the network diameter rendering chip designers more flexibility in regulating important performances centric design trade-offs such as packet delay, throughput and network energy while employing a low area overhead (~7%). Experimental results over 8 × 8 and 12 × 12 sized network show 8–11%, 18–66% and 60–66% lower packet delay while gain in throughput raises to 15–17%, 29–64% and 46–58% compared to 2-hop Dia-mesh (2x2 diagonal), Sc-mesh (1x1 diagonal) and conventional mesh topologies, respectively, under uniformly distributed traffic.     

三维集成技术的现状和发展趋势

给出了三维技术的定义,并给众多的三维技术一个明确的分类,包括三维封装(3D-P)、三维晶圆级封装(3DWLP)、三维片上系统(3D-SoC)、三维堆叠芯片(3D-SIC)、三维芯片(3D-IC)。分析了比较有应用前景的两种技术,即三维片上系统和三维堆叠芯片和它们的TSV技术蓝图。给出了三维集成电路存在的一些问题,包括技术问题、测试问题、散热问题、互连线问题和CAD工具问题,并指出了未来的研究方向。     

Ambient RF energy harvesting system: a review on integrated circuit design

This paper presents a comprehensive review of ambient RF energy harvester circuitry working on integrated circuits. The review covers 3 main blocks in an RF energy harvesting system implemented on chip. The blocks are the rectifier, impedance matching circuit and power management unit. The review of each block includes its operational principle, reported state-of-the-art circuit enhancement techniques, and design trade-offs. We compare the circuits in each block with respect to the techniques adopted to improve the performances for RF energy harvesting. To identify the benefits and limitations associated with the architecture we discuss the advantages and disadvantages of the circuit topologies in each block of an ambient RF energy harvester.     

用FIFO实现超声测厚系统A/D与ARM接口设计

在基于ARM的超声波测厚系统中,ARM处理器的数据接收能力往往与A/D芯片的工作速率不匹配,为避免有效数据丢失,提高系统工作效率,用FIFO作为高速A/D与ARM处理器之间的中转接口会得到很好的效果。这里以FIFO存储器CY7C4261作为中转器件实现了A/D芯片AD9283与ARM处理器S3C2410的接口设计,并叙述了数据从A/D芯片到ARM的整个数据采集过程。该接口电路用FIFO实现了超声测厚系统中A/D与ARM之间的无缝连接,提高了系统测厚精度。它的电路简单,调试方便,具有较高的应用价值。     

The multiple-processor PPS chip of the NON-VON 3 supercomputer

In this paper, we describe an experimental prototype VLSI chip that was designed to serve as the basis for a massively parallel supercomputer called NON-VON 3. The chip, which is implemented in 3-micron nMOS technology, contains eight 8-bit processing elements (PE's), each embodying 64 bytes of static RAM. Significant features of the design include: an unusually high processor density; a novel I/O switch that allows the machine to dynamically reconfigure to realize several logical communication topologies; logic supporting the pipelining of instructions, both within and among the individual PE's; a shared partial instruction decoder that reduces pinout and area, and a parallel self-testing, dynamically reconfigurable, fault-tolerant RAM that significantly increases both yield and reliability. The design and operation of the chip are discussed, along with its speed, area, and power dissipation characteristics.     

A 3D multilayer optical network on chip based on mesh topology

Optical Network-on-Chip (ONoC) is becoming a promising solution for high performance on chip interconnection, which draws much attention from many researchers. ONoC combined with 3D integration technology can address some issues of two-dimensional ONoC such as long distance and limited scalability, which have been shown to be effective solutions for further promoting the performance of ONoC. However, the infeasibility of most existing routers with four or five ports poses a problem in 3D optical interconnect as seven-port optical routers are required in 3D networks. To solve this problem, in this paper, we propose a 3D multilayer optical network on chip (3D MONoC) based on Votex, a non-blocking optical router with seven ports. We describe the optical router and the 3D network in detail. The proposed router architecture not only realizes 3D interconnection and can be utilized in most 3D ONoC, but also can be beneficial in achieving smaller area, lower cost of ONoC. We compare Votex with the traditional \(7\times 7\) optical router based on crossbar, which indicated that Votex can save cost. Moreover, we make a comparison of 3D MONoC employing Votex against its 2D counterpart. Simulation results show that the performance including ETE delay and throughput of 3D MONoC can be improved.     

线阵扫描三维成像激光雷达系统

针对小型智能机动平台对三维成像激光雷达小型化、低功耗、高精度、快速成像的特定应用要求,基于集成激光器阵列和APD探测阵列设计并实现了12元线阵扫描三维成像激光雷达系统;基于高速数字处理芯片和高精度时间间隔测量芯片实现了并行高精度激光脉冲飞行时间测量和实时数据处理和传输。详细描述了系统原理、组成部分以及实验结果。实验验证该系统激光脉冲重复频率大于10 kHz,垂直方向激光单元角度间隔小于2.5 mrad,近距离距离分辨率优于2.4 cm,测量数据统计标准差小于1,各通道一致性良好。在高速水平扫描转动平台驱动下实现了室内三维场景重构以及高塔大视场远距离目标探测成像实验。     

Universal biquad filters using low-voltage current mirrors

Novel Single Input Multiple Output (SIMO) and Multiple Input Single Output (MISO) current-mode universal biquad topologies are introduced in this paper. The proposed topologies have been realized by employing low-voltage current mirrors as active elements. As a result, an absence of resistors is achieved in the derived filter topologies; also only grounded capacitors are required. The resonant frequency of the filters can be electronically controlled by an appropriate dc current. In addition, the derived filters offer the feature of orthogonal adjustment between the resonant frequency and Q factor. The behavior evaluation of the proposed filters has been performed through a test chip prototype fabricated in AMS 0.35 μm CMOS technology.