TFT-LCD中隔垫物密度与Push Mura和低温气泡的关系

研究了隔垫物密度对Push Mura和低温气泡的影响.实验表明,通过增加隔垫物密度,能提高液晶面板的抗压强度,降低Push Mura发生率.但是,隔垫物密度过高会引起低温气泡发生.当隔垫物密度控制在适当范围内时,既能大大改善Push Mura,又不会发生低温气泡,且不影响产品的光学特性.     

固液界面纳米气泡的研究

在经典热力学理论中，室温下水中纳米气泡被认为是不能稳定存在的。近年来随着对疏水表面研究的深入，越来越多的现象暗示固液界面存在纳米气泡，并引起疏水长程作用力。目前直接探测固液界面纳米气泡的最有力手段是AFM，但它只能观察纳米气泡的形貌，无法对其进行直接定性，很有必要提供纳米气泡存在和来源的更直接证据。在云母表面进行乙醇和水替换形成纳米气泡，从成像条件和脱气对纳米气泡的影响两方面进行系统研究。不同成像模式和成像条件下AFM观察到的差异在一定程度上证明了观察到的就是纳米气泡。脱气实验结果表明，经脱气后乙醇和水形成纳米气泡的数量和概率明显降低，表明乙醇和水中溶解的气体是纳米气泡的来源，并为固液界面存在纳米气泡提供了更直接的证据。     

独一无二的“气泡”签名辨识系统

Novatec公司与法国国家科学研究中心图卢兹信息技术研究所(IRIT-CNRS)进行合作,于近日开发出一种新型认证方法,并研制出了相应的产品。这种新的认证方法是,在树脂中注入一些气泡,就能把一滴树脂变成独一无二的签名。气泡的注入过程是随机且不可重复的,从而保证了签名的唯一性。与之配套的是一种分为两个阶段运行的读出系统。首先,一个光传感器获取气泡的位置和形状的两维图像信息,然后再通过一个形状识别程序把两维的图像变成数字签名。在第二个阶段,通过改     

舰船尾流的前向光散射对光束衰减测量的影响

为优化前向光尾流自导的探测系统的设计,分析了舰船远程尾流中气泡群的前向光散射对测量气泡群衰减系数的影响。根据消光定理和Mie理论,推导了单散射条件下测量气泡群衰减系数的公式,给出了因前向光散射导致的测量误差因子和修正因子的表达式。基于此表达式对干净的尾流气泡群和覆盖着两种典型有机膜的脏尾流气泡群的误差因子和修正因子进行了数值计算,分析了探测系统的接收视场角和气泡表面附着的有机膜对衰减系数测量的影响。结果表明,前向散射对尾流气泡群的衰减测量影响很大,在前向1°的散射角范围内这种影响尤为显著;气泡表面附着的有机膜对尾流气泡群的衰减测量影响很小。     

多尺度复杂水质尾流气泡的激光探测仿真与实验

舰船尾流气泡具有尺度范围大、稀疏、离散等特征。利用蓝绿激光的海水穿透性能以及气泡对激光的后向散射特性，可以实现舰船尾流气泡的远场检测。舰船尾流的稀疏、离散特征导致气泡的激光散射回波信噪比极低，对光学接收处理系统及尾流信号处理方法带来了困难与挑战。建立了舰船尾流气泡的激光后向散射模型，通过蒙特卡罗仿真验证了不同水质、不同气泡距离和不同尺度气泡的激光后向散射特性，设计了可抑制近场水体强散射干扰的水下气泡激光测试分析系统，实现了激光能量与雪崩光电二极管接收增益间的匹配调节。针对室内和湖泊环境，开展了不同水质和光电探测参数下的尾流气泡检测性能测试，通过对数据进行统计处理分析得到了舰船尾流气泡的激光探测特征规律。设计的水下气泡激光测试分析系统可以实现对舰船尾流气泡的有效探测，为舰船尾流探测系统在不同水质环境下的工程应用提供了理论及数据支撑。     

ODF工艺中液晶滴下量的优化

研究了小尺寸液晶显示器件ODF(One Drop Filling)工艺中液晶滴下量对漏液晶和低温气泡的影响,确定了液晶滴下量的安全范围。开发了液晶滴下设备与PS高度检测设备联动的新型液晶滴下方法,有效地解决了PS产品在ODF工艺中发生漏液晶和低温气泡的问题。     

电容式触摸屏气泡线不良的研究与改善

在触控产品的制作过程中,气泡线不良严重影响着产品的外观品质。本文从气泡线的产生机理入手进行研究,发现该不良是由贴附偏光片时传感器保护层有机膜段差处与偏光片之间残留气泡导致。本文从设计面、工艺面对气泡线的影响因子进行了研究,实验发现有机膜边界设计位置、有机膜厚度、偏光片贴附相关工艺以及偏光片中PSA厚度对气泡线不良影响显著。其中有机膜边界设计位置远离显示区,降低有机膜与偏光片交叠宽度,可以使脱泡时气泡更容易排出而改善气泡线不良;降低有机膜厚度,可以减少偏光片贴附时有机膜断差位置气泡积累而改善气泡线不良;偏光片贴附相关工艺中增加贴附压力、降低贴附速度、增加脱泡时间,可以减少气泡积累以及增加排出而改善气泡线不良;增加偏光片中PSA胶层的厚度,可以在偏光片贴附时获得更大的弹性及压入量,减少气泡的积累而改善气泡线不良。研究结果表明,以上改善方法均能有效降低气泡线的发生率,实际生产时可采用组合对策,避免气泡线不良的发生。     

5G功放板填孔覆盖镀层耐热性能研究

5G功放板覆盖镀层（POFV）的耐热性能直接影响印制线路板（PCB）组装之后的可靠性，因此在制作此类产品之前，重点对5G功放板填孔POFV的耐热性能的影响因子进行了研究。通过采用鱼骨图对影响因子进行梳理，找出关键的流程及影响因子，针对性对印制线路板制作的树脂填孔流程的树脂烤板参数、电镀通孔（PTH）流程除胶参数、在流程中的停留时间，以及填孔树脂本身的热膨胀（CTE）特性等影响因子进行对比实验，并对各测试结果进行总结分析。根据实验测试结果，确认了影响填孔覆盖镀层与树脂分离的主要因素是所选填孔树脂与基板CTE特性的匹配性，此外填孔后的树脂固化烤板参数、磨树脂后到电镀通孔的停留时间、电镀通孔过程中除胶条件等对POFV镀层与填孔树脂分离有少许影响。     

焊锡中气泡对电子元件热传导的影响

采用有限元软件ANSYS建立了空调中一种电子元件的三维模型,利用有限元"生死单元"技术,模拟电子元件焊锡层中存在不同大小和位置的气泡时的情形,分别对模型的热传导进行模拟计算,并对分析结果进行比较,以研究焊锡中气泡对电子元件热传导的影响。结果表明,气泡大小占焊锡体积比达4/49时,气泡对热传导影响开始明显化。气泡位于边缘位置对热传导影响更大,与中间位置相比,温度约低3K。     

水下气泡幕消光特性研究

为了研究水下气泡幕对激光传输特性的影响,采用米氏散射理论对水下气泡的消光截面和消光系数进行了计算,并在此基础上采用朗伯特-比尔定律对水下气泡幕的消光特性进行了理论分析和实验验证,取得了不同密度、不同厚度以及处于不同位置处气泡幕的透射光功率数据。结果表明,透过气泡幕的光功率随气泡密度以及气泡幕厚度呈指数衰减,而与气泡幕所处的位置没有密切关系。这一结论对舰船气泡尾流的光学探测是有帮助的。     

Thermal and mechanical effects of voids within flip chip soldering in LED packages

This paper investigates the effect of void percentage in the solder layer on the shear strength and thermal property of DA3547 packages by SAC soldering technology. X-ray observation and shear tests revealed that the increase of solder paste volume significantly decreases the void percentage in the solder layer and thus improved the shear strength of the packages. Furthermore, packages with lower void percentage showed a lower junction temperature based on the results of IR test and finite element simulation. The temperature difference due to the effect void percentage shows a correlation with the input power. For the DA3547 packages studied in this research, voids show limited influence on the junction temperature under 50 mA, the typical current recommended by Cree.     

Drainage ratio impact on void creation in gold interconnect

This articles details investigation into metal voiding observed on electroplated gold interconnect during high temperature wafer-scale bake. The test structures and methodology to measure this effect are discussed in detail. Various factors affecting a metal voiding phenomenon were examined and measured. A drainage ratio is defined to quantify the effects of test structure layout proportions on gold void formation. Different metal formulations were also investigated to better comprehend the influence of metal composition on gold void formation. Furthermore the effect of temperature on void formation was studied and an activation energy of 2.0 eV was estimated for this phenomena. Several methods are proposed to minimize any reliability impact from this phenomenon.     

Electromigration-induced UBM consumption and the resulting failure mechanisms in flip-chip solder joints

Eutectic PbSn flip chip solder joint was subjected to 5×10³ A/cm² current stressing at 150°C and 3.5 × 10⁴ A/cm² current stressing at 30°C. The under bump metallurgy (UBM) on the chip was sputtered Ni/Cu, and the substrate side was a thick Cu trace. It was shown through in-situ observation that the local temperature near the entrance of electrons from the Al interconnect to the solder became higher than the rest of the joint. The accelerated local Ni UBM consumption near the entrance was also observed. Once the Ni was consumed at a location, a porous structure formed, and the flow of the electrons was blocked there. It was found that the formation of the void and the formation of the porous structure were competing with each other. If the porous structure formed first, then the void would not be able to nucleate there. On the other hand, if the void could nucleate before the UBM above lost its conductivity, then the joint would fail by the void formation-and-propagation mechanism.     

芯片粘接空洞对功率器件散热特性的影响

芯片粘结层的空洞是造成功率半导体芯片由于散热不良而失效的主要原因.运用有限元法对芯片封装结构进行了热学模拟分析,研究了粘结层材料、粘结层厚度、粘结层空洞的面积、空洞的位置对芯片温度分布以及芯片最高温度造成的影响.对标准中规定应避免出现的粘结状况进行了分析,研究结果表明空洞的面积越大,芯片的温度越高.空洞位于拐角,即粘结区域四角的位置时,芯片散热情况最差.而在标准中给出的,芯片空洞面积达50%,且位于拐角时,芯片的温度最高.     

Effect of Selected Process Parameters on Durability and Defects in Surface-Mount Assemblies for Portable Electronics

This paper presents a systematic approach to study the effect of manufacturing variables on the creation of defects and the effect of those defects on the durability of lead-free (Pb-free) solder joints. An experiment was designed to systematically vary the printing and reflow process variables in order to fabricate error-seeded test assemblies. The error-seeded samples were then inspected visually and with X-ray, to identify different types of defects, especially voids, and then test for electrical performance. The specimens were subjected to an accelerated thermal cycling test to characterize the durability of these error-seeded specimens and to study the effect of each manufacturing variable on the durability of the solder joints. The response variables for the design of experiments are thermal cycling durability of the solder joints and void area percentage in ball grid array (BGA) solder joints. Pretest microstructural analysis showed that specimens produced under inadequate reflow profiles suffered from insufficient wetting and insufficient intermetallic formation. Statistical analysis of the response variables shows that waiting time, heating ramp, peak temperature, and cooling rate have nonlinear effects on thermal cycling durability. Two variables in particular [peak temperature and waiting time (the time waited after the solder paste barrel was opened and before print)] appear to have optimum values within the ranges investigated. Statistical analysis of void percentage area for all design of experiment (DOE) runs show that higher stencil thickness results in higher void percentage and that void percentage increases as time above melt and peak temperature increases.     

Solder void position and size effects on electro thermal behaviour of MOSFET transistors in forward bias conditions

This research aims to enhance the understanding on position and size effects on the electro thermal behaviour of low voltage power MOSFET transistors in forward bias condition. The numerical simulations are based on a fractional design of experiments (DoE). The performance of a finite elements model is discussed by comparing thermal and electrical measurements to results of finite elements simulation on a module of free void and voided solder. The void in the model is afterwards parameterized on position and size, according to the fractional DoE of the study. The combined functions issued from the parametric simulations and the DoE show the main impact of void size on temperature of the device and on the surface temperature of the bonding wires. From the numerical viewpoint, the most impacting position of void depends highly on the void size. The redistribution of current density and temperature on MOSFET chip and bonding wires due to solder void is also observed. A future experimental study in respect to the same DoE is expected in prospect, in order to fulfil the complementarity for this approach.     

Investigation of Void Nucleation and Propagation in the Joule Heating Effect During Electromigration in Flip-Chip Solder Joints

This study analyzes the effect of void propagation on the temperature increase of solder joints by using x-ray microscopy, Kelvin probes, and infrared microscopy. It was found that the temperature rise due to void formation was less than 1.3°C when the voids depleted about 75% of the contact opening, even though bump resistance had increased to 10.40 times its initial value. However, the temperature rose abruptly with an increase of up to 8.0°C when the voids depleted 96.2% of the contact opening. A hot spot was observed immediately before the occurrence of open failure in the solder bump. The local increase in temperature was about 30.2°C at the spot. This spot may be the remaining contact area immediately before the occurrence of open failure.     

半导体封装中的可视化技术

树脂传递模封装是广泛使用的可靠性量产性均好的半导体封装方法。但随着封装体（PACKAGE）尺寸的日益薄型化和多腿化,不可避免地会发生与树脂在模腔中流动状态有关的空隙等使制品失效的不良模式。这样,通过观察树脂流动状态及对空隙的分布进行研究,对于研究空隙发生机理从而抑制空隙发生具有重要意义。本文将着重介绍两种新的研究实验方法：（1）应用玻璃嵌入式新型可视化模具观察树脂在模腔中的流动状态;（2）采用超声波探查图像装置（简称SAT）进行树脂封装体内部的观察。     

LSI failure analysis using focused laser beam heating

Three new applications of a focused laser beam to VLSI interconnect diagnosis have been reported, in which interconnect heating by a laser beam and current change measurement are used. One is a void and Si nodule detection method that monitors current changes caused by resistance changes induced by the laser beam heating, through temperature dependence of resistance. Another is a current measurement method that monitors current changes caused by resistance changes induced by the laser beam heating, through temperature dependence of resistance. The last is a void and other types of anomalies detection method that monitors current changes caused by the laser beam heating through the thermoelectric effect. In this paper, we present new results on these three methods, and discuss the advantages and disadvantages of these methods over other methods.     

Geometrical effect of bump resistance for flip-chip solder joints: Finite-element modeling and experimental results

The bump resistance of flip-chip solder joints was measured experimentally and analyzed by the finite-element method. Kelvin structures for flip-chip solder joints were designed and fabricated to measure the bump resistance. The measured value was only about 0.9 mΘ at room temperature, which was much lower than that expected. Three-dimensional (3-D) modeling was performed to examine the current and voltage distribution in the joint. The simulated value was 7.7 mΘ, which was about 9 times larger than the experimental value. The current crowding effect was found to be responsible for the difference in bump resistance. Therefore, the measured bump resistance strongly depended on the layout of the Kelvin structure. Various layouts were simulated to investigate the geometrical effect of bump resistance, and a significant geometrical effect was found. A proper layout was proposed to measure the bump resistance correctly. The Kelvin structure would play an important role in monitoring void formation and microstructure changes during the electromigration of flip-chip solder joints.