RS码与LDPC码的联合迭代译码

针对RS码与LDPC码的串行级联结构,提出了一种基于自适应置信传播(ABP)的联合迭代译码方法.译码时,LDPC码置信传播译码器输出的软信息作为RS码ABP译码器的输入;经过一定迭代译码后,RS码译码器输出的软信息又作为LDPC译码器的输入.软输入软输出的RS译码器与LDPC译码器之间经过多次信息传递,译码性能有很大提高.码长中等的LDPC码采用这种级联方案,可以有效克服短环的影响,消除错误平层.仿真结果显示:AWGN信道下这种基于ABP的RS码与LDPC码的联合迭代译码方案可以获得约0.8 dB的增益.     

基于VHDL的TPC译码器设计

Turbo乘积码是一种性能卓越的前向纠错码,具有译码复杂度低,且在低信噪比时可以获得近似最优的性能。介绍基于Chase算法的Turbo乘积码软入软出（SISO）迭代译码算法,提出基于VHDL硬件描述语言的TPC译码器设计方案,并在FPGA芯片上进行了仿真和验证。仿真结果证明该译码器有很大的实用性和灵活性。     

LDPC编码调制系统中基于反馈LLR均值的迭代解调/译码算法

该文针对LDPC码编码的BICM系统,提出一种对LDPC码译码器输出外附信息的计算方法进行改进的迭代解调/译码算法。与传统的解调/译码算法不同在于,该算法对每次BP迭代中译码器输出的各编码比特的外附LLR分别求均值后,再将其作为先验信息反馈给软解调器开始下次的迭代解调/译码。采用该方法可有效地减轻LDPC码在BP迭代过程中某些比特LLR值的振荡现象,从而使得传递给软解调器的外附信息更准确。仿真结果表明,和传统的两种迭代解调/译码算法相比,该算法能进一步提高LDPC编码BICM迭代系统的译码性能,而复杂度并无明显增加。     

BCH-Turbo编码的设计与仿真实现

本文针对Turbo码在低信噪比下迭代次数多、译码时延长问题,在分析了Turbo码的编译码原理和算法基础上,提出一种可以有效降低平均迭代次数、减少译码时延的基于BCH迭代停止准则的Turbo码迭代译码的设计方案。本方案采用BCH码作为Turbo迭代译码的停止准则。并对每一个分量译码器结果都进行判断。可提前停止迭代。通过Monte Carlo仿真表明在AWGN信道下,误码率有所降低。Turbo码译码的平均迭代次数与交叉熵准则相比有明显下降。本文还分析了BCH码编码效率和分组长度的选择对系统性能的影响。     

乘积码基于相关运算的迭代译码

乘积码是一种能以Turbo码的思想实现译码的级联码，具有一般编码无法达到的纠错能力。本文提出一种新的乘积码迭代译码算法，其核心思想是通过输出软信息与接收软信息进行线性迭加的方式来实现反馈，此时只须提供-1和1组成的软输出矩阵就能获得很高的编码增益，仿真表明，将子译码器译码后的结果再进行一次相关运算作为软输出，译码性能可以得到进一步的提高。     

Turbo码的编译码器及性能分析

介绍Turbo码的编译码器和迭代译码器的结构 ,并分析Turbo的性能     

Turbo码软判决输出维特比译码方案的改造

Turbo码是一种新的纠错编码，具有十分强的纠错能力。Turbo码编码端采用两个或两个以上的卷积并行级联构成，译码端则采用以基于软判决信息输入／输出的反馈迭代译码结构。译码算法是Turbo码设计的核心，现已有的两种主要的译码算法——MAP和SOVA。SOVA是一种改进的维特比算法，使其可以逐比特输出与MAP算法类似的软判决信息。该文综述了Turbo码SOVA译码的几种改进方式，并分析了这几种改进方式及仿真结果。     

Turbo码软判决输出维持比译码方案的改进

Turbo码是一种新的纠错编码，具有十分强的纠错能力，Turbo码编码端采用两个或两个以上的卷积并行级联构成，译码端则采用以基于软判决信息输入/输出的反馈迭代译码结构。译码算法是Turbo码设计的核心，现巳有的两种主要的译码算法-MAP和SOVA。SOVA是一种改进的维持比算法，使其可以逐比特输出与MAP算法类似的软判决信息。该文综述了Turbo码SOVA译码的几种改进方式，并分析了这几种改进方式及仿真结果。     

Turbo乘积码的两种迭代译码器的比较

提出了Turbo乘积码的并行迭代译码原理,对比分析了一种新的并行迭代译码器和传统的串行译码器,给出了以扩展汉明码(32,26,4)、(64,57,4)为子码的二维Turbo乘积码(32,26,4)。、(64,57,4)。在通过两种不同的译码器时的仿真结果。仿真结果表明,采取并行迭代译码器,在保持同样的译码性能的同时降低了译码延时。     

BCH-Turbo码的设计与仿真实现

本文针对Turbo码在低信噪比下迭代次数多、译码时延长问题,在分析了Turbo码的编译码原理和算法基础上,提出一种可以有效降低平均迭代次数、减少译码时延的基于BCH迭代停止准则的Turbo码迭代译码的设计方案.本方案采用BCH码作为Turbo迭代译码的停止准则,并对每一个分量译码器结果都进行判断,可提前停止迭代.通过Monte Carlo仿真表明在AWGN信道下,误码率有所降低,Turbo码译码的平均迭代次数与交叉熵准则相比有明显下降.本文还分析了BCH码编码效率和分组长度的选择对系统性能的影响.     

并行级联Gallager码的动态最大外迭代次数译码方案的研究

PCGC(Parallel Concatenated Gallager Code,并行级联Gallager码)是将LDPC(Low Density Parity Check,低密度奇偶校验)码运用于并行级联编码形式而得到的一种新型编码,它的译码器采用双层迭代的形式.传统的PCGC译码器采用FMSIN(Fixed Maximum Super Iteration Number,固定最大外迭代次数)的方案,在信道SNR(Signal-to-Noise Ratio,信噪比)较低时会导致译码器平均迭代次数,也即译码器复杂度偏高.针对于此,本文提出一种根据信道信噪比状况动态调整译码器中最大外迭代次数的方案,并通过计算机仿真,验证了运用此方案后,译码器复杂度可得到较大程度的降低.     

一种短时延的Turbo码并行译码算法

由于迭代译码是Turbo码译码的主要特点,因而在译码的过程中会带来很大的时延.为了减小译码延时,本文将整块译码器分成w个子块,并且运用计算复杂度低的T-BCJR算法,在相邻的子块译码器之间相互运用边界分配值作为下一次迭代的初始值,而不是采用各相邻的子块之间重叠部分进行译码,故使译码延时下降为原来的1/w。     

Complexity Reduction in SISO Decoding of Block Codes

SISO decoding for block codes can be carried out based on a trellis representation of the code. However, the complexity entailed by such decoding is most often prohibitive and thus prevents practical implementation. This paper examines a new decoding scheme based on the soft-output Viterbi algorithm (SOVA) applied to a sectionalized trellis for linear block codes. The computational complexities of the new SOVA decoder and of the conventional SOVA decoder, based on a bit-level trellis, are theoretically analyzed and derived for different linear block codes. These results are used to obtain optimum sectionalizations of a trellis for SOVA. For comparisons, the optimum sectionalizations for Maximum A Posteriori (MAP) and Maximum Logarithm MAP (Max-Log-MAP) algorithms, and their corresponding computational complexities are included. The results confirm that the new SOVA decoder is the most computationally efficient SISO decoder, in comparisons to MAP and Max-Log-MAP algorithms. The simulation results of the bit error rate (BER) performance, assuming binary phase -- shift keying (BPSK) and additive white Gaussian noise (AWGN) channel, demonstrate that the performance of the new decoding scheme is not degraded. The BER performance of iterative SOVA decoding of serially concatenated block codes shows no difference in the quality of the soft outputs of the new decoding scheme and of the conventional SOVA.     

一种乘积码译码器设计方案的研究

介绍了一种乘积码迭代译码器的硬件设计方案。基于软判决译码规则,使用VHDL硬件描述语言,提出了基于Modelsim6.Oa仿真平台的两维乘积码的EDA实现方法,给出了仿真波形,迭代次数为四次时最大译码速率可达到50Mbit/s,并通过了在Xilinx公司的FPGA芯片XC2S200上的综合验证实验。该译码器的功能仿真和硬件实现都证明了这种方案的可行性和正确性。     

迭代结构的信源信道联合解码及其简化算法

信源信道联合解码算法中的迭代信道解码需要进行比特似然值和概率值转换,以及联乘、累加运算,增加了信道解码的计算复杂度,该文针对这一问题,直接利用信道解码的比特硬判决值和参数的先验概率,估计比特的外信息,用于迭代信道解码。基于高斯-马尔可夫信源参数的仿真实验表明,该简化算法大大降低了迭代信道解码算法的计算复杂度。与独立解码算法相比,简化的联合解码算法明显改善了接收参数的信噪比,同时不会明显降低原迭代结构解码算法的性能。     

Advanced decoding algorithms for Reed-Solomon/Convolutional concatenated codes

The evaluation of the union bound for theber of Reed-Solomon/Convolutional concatenated codes indicates that their performance might largely improve through the application of soft iterative decoders. This paper presents an iterative decoding algorithm for concatenated codes consisting of an outer Reed-Solomon code, a symbol interleaver and an inner convolutional code. The performance improvement for iterative and non-iterative decoders is evaluated. Existing solutions for the different decoding stages and their interfaces are discussed and their performance is compared. A new procedure is proposed to define the feedback signal from the output of the Reed-Solomon decoder to the input of the convolutional decoder, which captures the reliability information that can be inferred from errors-and-era-suresrs decoders and includes the “state pinning” approach as a particular case. The decoding schemes are applied to the specificdvb-s concatenated code.     

基于SSCANL译码器的联合迭代检测译码算法

为了提升基于极化码的稀疏码多址接入（sparse code multiple access,SCMA）系统接收机性能,提出了基于简化软消除列表（simplify soft cancellation list,SSCANL）译码器的循环冗余校验（cyclic redundancy check,CRC）辅助联合迭代检测译码接收机方案。该方案中极化码译码器使用SSCANL译码算法,采用译码节点删除技术对软消除列表（soft cancellation list,SCANL）算法所需要的L次软消除译码（soft cancellation, SCAN）进行简化,通过近似删除冻结位节点,简化节点间软信息更新计算过程,从而降低译码算法的计算复杂度。仿真结果表明,SSCANL算法可获得与SCANL算法一致的性能,其计算复杂度与SCANL算法相比有所降低,码率越低,算法复杂度降低效果越好;且基于SSCANL译码器的CRC 辅助联合迭代检测译码接收机方案相较基于SCAN译码器的联合迭代检测译码（joint iterative detection and decoding based on SCAN decoder, JIDD-SCAN）方案、基于SCAN译码器的CRC辅助联合迭代检测译码（CRC aided joint iterative detection and decoding based on SCAN decoder,C-JIDD-SCAN）方案,在误码率为10^-4时,性能分别提升了约0.65 dB、0.59 dB。     

Neural network decoding of the block Markov superposition transmission

A neural network (NN)-based decoding algorithm of block Markov superposition transmission (BMST) was researched.The decoders of the basic code with different network structures and representations of training data were implemented using NN.Integrating the NN-based decoder of the basic code in an iterative manner,a sliding window decoding algorithm was presented.To analyze the bit error rate (BER) performance,the genie-aided (GA) lower bounds were presented.The NN-based decoding algorithm of the BMST provides a possible way to apply NN to decode long codes.That means the part of the conventional decoder could be replaced by the NN.Numerical results show that the NN-based decoder of basic code can achieve the BER performance of the maximum likelihood (ML) decoder.For the BMST codes,BER performance of the NN-based decoding algorithm matches well with the GA lower bound and exhibits an extra coding gain.     

SCMA场景下的极化码编解码方案改进研究

极化码是目前唯一一种被证明可达到信道容量的编码方式,稀疏码分多址接入(Sparse Code Division Multiple Access,SCMA)可以提高频谱资源的利用率和接入系统的用户接入数量。为了提升SCMA与极化码的联合系统的误码率性能和译码时延,使联合系统的应用越来越广泛,提出了2种降低译码复杂度的方式:简化的左信息更新方式和剪枝译码算法。简化的左信息更新方式对于N=256,N=1024的极化码分别能降低37.6%和44.6%的存储资源占用数;剪枝译码算法在码率为0.5时能降低50%左右的计算复杂度。基于简化的SCAN算法改进了联合检测译码算法,在接收机采用外循环迭代的结构,引入了阻尼机制,选取最优的阻尼方式和最优阻尼值。仿真分析了所提联合检测译码算法与原有联合检测译码算法的误码率性能差异,外迭代接收机性能与内外双循环迭代的接收机性能相同,采用阻尼机制联合接收机的性能比无阻尼接收机的性能高0.8 dB左右,SJIDD的误帧率性能比保留宽度为32的SCLJDD的性能低0.7 dB左右,但能使接收机处理时延降至原来的1/4~1/8。     

Using linear programming to Decode Binary linear codes

A new method is given for performing approximate maximum-likelihood (ML) decoding of an arbitrary binary linear code based on observations received from any discrete memoryless symmetric channel. The decoding algorithm is based on a linear programming (LP) relaxation that is defined by a factor graph or parity-check representation of the code. The resulting "LP decoder" generalizes our previous work on turbo-like codes. A precise combinatorial characterization of when the LP decoder succeeds is provided, based on pseudocodewords associated with the factor graph. Our definition of a pseudocodeword unifies other such notions known for iterative algorithms, including "stopping sets," "irreducible closed walks," "trellis cycles," "deviation sets," and "graph covers." The fractional distance d/sub frac/ of a code is introduced, which is a lower bound on the classical distance. It is shown that the efficient LP decoder will correct up to /spl lceil/d/sub frac//2/spl rceil/-1 errors and that there are codes with d/sub frac/=/spl Omega/(n/sup 1-/spl epsi//). An efficient algorithm to compute the fractional distance is presented. Experimental evidence shows a similar performance on low-density parity-check (LDPC) codes between LP decoding and the min-sum and sum-product algorithms. Methods for tightening the LP relaxation to improve performance are also provided.