应用于IEEE 802.11b无线局域网系统的2.4GHzCMOS单片收发机射频前端

实现了一个应用于IEEE 802.11b无线局域网系统的2.4GHz CMOS单片收发机射频前端,它的接收机和发射机都采用了性能优良的超外差结构.该射频前端由五个模块组成:低噪声放大器、下变频器、上变频器、末前级和LO缓冲器.除了下变频器的输出采用了开漏级输出外,各模块的输入、输出端都在片匹配到50Ω.该射频前端已经采用0.18μm CMOS工艺实现.当低噪声放大器和下变频器直接级联时,测量到的噪声系数约为5.2dB,功率增益为12.5dB,输入1dB压缩点约为-18dBm,输入三阶交调点约为-7dBm.当上变频器和末前级直接级联时,测量到的噪声系数约为12.4dB,功率增益约为23.8dB,输出1dB压缩点约为1.5dBm,输出三阶交调点约为16dBm.接收机射频前端和发射机射频前端都采用1.8V电源,消耗的电流分别为13.6和27.6mA.     

A 5-GHz highly integrated receiver front-end

In this paper a radio front-end for a IEEE 802.11a and HIPERLAN2 sliding-IF receiver is presented. The circuit, implemented in a low-cost 46-GHz-f _T silicon bipolar process, includes a variable-gain low noise amplifier and a double-balanced mixer. Thanks to monolithic LC filters and on-chip single-ended-to-differential conversion of the RF signal, the proposed solution does not require the expensive image rejection filter and an external input balun. The receiver front-end exhibits a 4.3-dB noise figure and a power gain of 21 dB, providing an image rejection ratio higher than 50 dB. By using a 1-bit gain control, it achieves an input 1-dB compression point of −11 dBm, while drawing only 22 mA from a 3-V supply voltage.     

用于IEEE802．11b／g WLAN直接下变频接收机的射频前端设计

介绍了一种应用于IEEE802．11b／g无线局域网接收机射频前端的设计。基于直接下变频的系统架构。接收机集成了低噪声放大器、I／Q下变频器、去直流偏移滤波器、基带放大器和信道选择滤波器。电路采用TSMC0．18μm CMOS工艺设计,工作在2．4GHz ISM（工业、科学和医疗）频段,实现的低噪声放大器噪声系数为0．84dB,增益为16dB,S11低于-15dB,功耗为13mW;I／Q下变频器电压增益为2dB,输入1dB压缩点为-1 dBm,噪声系数为13dB,功耗低于10mw。整个接收机射频前端仿真得到的噪声系数为3．5dB,IIP3为-8dBm,IP2大于30dBm,电压增益为31dB,功耗为32mW。     

An auto-I/Q calibrated CMOS transceiver for 802.11g

The CMOS transceiver IC exploits the superheterodyne architecture to implement a low-cost RF front-end with an auto-I/Q calibration function for IEEE 802.11g. The transceiver supports I/Q gain and phase mismatch auto tuning mechanisms at both the transmitting and receiving ends, which are able to reduce the phase mismatch to within 1/spl deg/ and gain mismatch to 0.1dB. Implemented in a 0.25 /spl mu/m CMOS process with 2.7 V supply voltage, the transceiver delivers a 5.1 dB receiver cascade noise figure, 7 dBm transmit, and a 1 dB compression point.     

A 900 MHz Zero‐IF RF Transceiver for IEEE 802.15.4g SUN OFDM Systems

This paper presents a 900 MHz zero‐IF RF transceiver for IEEE 802.15.4g Smart Utility Networks OFDM systems. The proposed RF transceiver comprises an RF front end, a Tx baseband analog circuit, an Rx baseband analog circuit, and a ΔΣ fractional‐N frequency synthesizer. In the RF front end, re‐use of a matching network reduces the chip size of the RF transceiver. Since a T/Rx switch is implemented only at the input of the low‐noise amplifier, the driver amplifier can deliver its output power to an antenna without any signal loss; thus, leading to a low dc power consumption. The proposed current‐driven passive mixer in Rx and voltage‐mode passive mixer in Tx can mitigate the IQ crosstalk problem, while maintaining 50% duty‐cycle in local oscillator clocks. The overall Rx‐baseband circuits can provide a voltage gain of 70 dB with a 1 dB gain control step. The proposed RF transceiver is implemented in a 0.18 μm CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. The fabricated chip shows a Tx average power of ?2 dBm, a sensitivity level of ?103 dBm at 100 Kbps with , an Rx input P_1dB of ?11 dBm, and an Rx input IP3 of ?2.3 dBm.     

A 5.4 mW/0.07 mm$^{2}$ 2.4 GHz Front-End Receiver in 90 nm CMOS for IEEE 802.15.4 WPAN Standard

An integrated 2.4 GHz CMOS receiver front-end according to the IEEE 802.15.4 standard is presented in this paper. It integrates the overall RF part, from the balun up to the first stage of the channel filter, as well as the cells for the LO signal conditioning. The proposed architecture is based on a 6 MHz low-IF topology, which uses an inductorless LNA and a new clocking scheme for driving a passive mixer. When integrated in a 90 nm CMOS technology, the receiver front-end exhibits an area of only 0.07 mm², or 0.23 mm² when including an input integrated balun. The overall chip consumes 4 mA from a single 1.35 V supply voltage and it achieves a 35 dB conversion gain from input power in dBm to output voltage in dBvpk, a 7.5 dB NF value, -10 dBm of IIP3 and more than 32 dB of image rejection.     

A Low-Power Fullband 802.11a/b/g WLAN Transceiver With On-Chip PA

A low-power fullband 802.11a/b/g WLAN transceiver in 0.15-mum CMOS technology is described. The zero-IF transceiver achieves a receiver noise figure of 4.4/4 dB for the 2.4-GHz/5-GHz bands, respectively. The corresponding sensitivity at 54-Mb/s operation is -72 dBm for 802.11g and -74 dBm for 802.11a using actual PER measurement. An on-chip PA delivers 20 dBm output P1-dB. A new I/Q compensation scheme is implemented in local oscillator (LO) and an image rejection of better than 52 dB is observed. The transmitter delivers 10/1.5 dBm (2.4-/5-GHz) EVM-compliant output power for a 64-QAM OFDM signal at 54-Mb/s. The power consumption is 117/135 mW (1.8-V) in the receive mode and 570/233.1 mW in the transmit mode for 2.4/5 GHz, respectively. The low power consumption, high integration and robustness (-40 to 140degC) make this transceiver suitable for portable applications     

A low power 3-5 GHz CMOS UWB receiver front-end

A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below-8.5 dB across the 3.1-4.7 GHz frequency range, max-imum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of-11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm2.     

一种基于OFDM的新型低功耗RF收发器设计

为实现低功耗信号传输,提出一种基于OFDM的IEEE 802.15.4g低功耗无线电频率（RF）收发器。该新型RF收发器电路由Tx BBA（基带模拟）、片上RF开关前端、Rx BBA及锁相环（PLL）构成,采用0.18?m CMOS技术制作,满足了IEEE 802.15.4g OFDM系统低功耗信号传输的需要。实际测试结果显示,相比传统的RF收发器,提出的RF收发器具有较低的功耗和良好的灵敏度,当电源电压为1.8 V时,Tx模式下会消耗14.7mA,Rx模式下会消耗15.7mA。     

一个双频带可重构的直接变频接收机射频前端

A dual-band reconfigurable wireless receiver RF front-end is presented, which is based on the directconversion principle and consists of a low noise amplifer （LNA） and a down-converter. By utilizing a compact switchable on-chip symmetrical inductor, the RF front-end could be switched between two operation frequency bands without extra die area cost. This RF front-end has been implemented in the 180 nm CMOS process and the measured results show that the front-end could provide a gain of 25 dB and IIP3 of 6 dBm at 2.2 GHz, and a gain of 18.8 dB and IIP3 of 7.3 dBm at 4.5 GHz. The whole front-end consumes 12 mA current at 1.2 V voltage supply for the LNA and 2.1 mA current at 1.8 V for the mixer, with a die area of 1.2 × 1 mm^2.     

A CMOS RF front-end for a multistandard WLAN receiver

This letter describes the design and performance of a dual band tri-mode receiver front-end compliant with the IEEE 802.11a, b, and g standards. The receiver front-end was built in a 0.18-/spl mu/m CMOS process and achieves a noise figure of 4.7 dB/5.1 dB for the 2.4-GHz/5-GHz bands, respectively. The receiver front-end provides a dual gain mode of 5 dB/30 dB with an IIP3 of -1dBm for the low gain mode. The front-end draws 25 mA/27 mA from a 1.8-V supply for the 2.4-GHz/5-GHz bands, respectively.     

A low noise CMOS RF front-end for UWB 6-9 GHz applications

An integrated fully differential ultra-wideband CMOS RF front-end for 6-9 GHz is presented.A resistive feedback low noise amplifier and a gain controllable IQ merged folded quadrature mixer are integrated as the RF front-end. The ESD protected chip is fabricated in a TSMC 0.13μm RF CMOS process and achieves a maximum voltage gain of 23-26 dB and a minimum voltage gain of 16-19 dB,an averaged total noise figure of 3.3-4.6 dB while operating in the high gain mode and an in-band IIP3 of-12.6 dBm while in th...     

A fully integrated 24-dBm CMOS power amplifier for 802.11a WLAN applications

A fully integrated 24-dBm complementary metal oxide semiconductor (CMOS) power amplifier (PA) for 5-GHz WLAN applications is implemented using 0.18-/spl mu/m CMOS foundry process. It consists of differential three-stage amplifiers and fully integrated input/output matching circuits. The amplifier shows a P/sub 1/ of 21.8 dBm, power added efficiency of 13%, and gain of 21 dB, respectively. The saturated output power is above 24.1 dBm. This shows the highest output power among the reported 5-GHz CMOS PAs as well as completely satisfying IEEE 802.11a transmitter back off requirement.     

A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g wireless LAN

A single-chip dual-band tri-mode CMOS transceiver that implements the RF and analog front-end for an IEEE 802.11a/b/g wireless LAN is described. The chip is implemented in a 0.25-/spl mu/m CMOS technology and occupies a total silicon area of 23 mm/sup 2/. The IC transmits 9 dBm/8 dBm error vector magnitude (EVM)-compliant output power for a 64-QAM OFDM signal. The overall receiver noise figure is 5.5/4.5 dB at 5 GHz/2.4 GHz. The phase noise is -105 dBc/Hz at a 10-kHz offset and the spurs are below -64 dBc when measured at the 5-GHz transmitter output.     

433MHz ASK接收机射频前端电路设计

设计了一款应用在433MHz ASK接收机中的射频前端电路。在考虑了封装以及ESD保护电路的寄生效应的同时,从噪声、匹配、增益和线性度等方面详细讨论了低噪声放大器和下混频器的电路设计。采用0.18μm CMOS工艺,在1.8V的电源电压下射频前端电路消耗电流10.09 mA。主要的测试结果如下:低噪声放大器的噪声系数、增益、输入P1dB压缩点分别为1.35 dB、17.43 dB、-8.90dBm;下混频器的噪声系数、电压增益、输入P1dB压缩点分别为7.57dB、10.35dB、-4.83dBm。     

A highly integrated dual-band multimode wireless LAN transceiver

A fully integrated radio transceiver chip for the 2.4- and 5-GHz WLAN standards 802.11a/b/g is presented in a 0.25-/spl mu/m 40-GHz BiCMOS technology. The chip integrates the low-noise amplifiers, mixers, channel filters, programmable gain control, synthesizers with voltage-controlled oscillators and reference oscillator, transmitters, antialiasing filters, and voltage regulators. The key performances of the presented transceiver are a receive sensitivity of -85 dBm and -74 dBm for 11-Mb/s complementary code keying (CCK) and 54 Mb/s orthogonal frequency division multiplexing (OFDM) modes, respectively, and an error vector magnitude of -35 dB measured at the transmitter with an output power of -4 dBm at 54-Mb/s 802.11a mode. The transceiver exceeds all IEEE requirements for the 802.11a/b/g CCK and OFDM standards and supports a frequency range of 4.9 to 6 GHz for the future extensions of the 802.11a standard in different countries.     

A Fully Integrated 2.4-GHz IEEE 802.15.4-Compliant Transceiver for ZigBee™ Applications

A single-chip 2.4-GHz CMOS radio transceiver with integrated baseband processing according to the IEEE 802.15.4 standard is presented. The transceiver consumes 14.7 mA in receive mode and 15.7 mA in transmit mode. The receiver uses a low-IF topology for high sensitivity and low power consumption, and achieves -101 dBm sensitivity for 1% packet error rate. The transmitter topology is based on a PLL direct-modulation scheme. Optimizations of architecture and circuit design level in order to reduce the transceiver power consumption are described. Special attention is paid to the RF front-end design which consumes 2.4mA in receive mode and features bidirectional RF pins. The 5.77 mm² chip is implemented in a standard 0.18-mum CMOS technology. The transmitter delivers +3 dBm into the 100-Omega differential antenna port     

应用于无线传感器网络低噪声放大器的设计

本文给出一种应用于无线传感器网络射频前端低噪声放大器的设计,采用SMIC0．18μmCMOS工艺模型。在CadenceSpectre仿真环境下的仿真结果表明：该低噪声放大器满足射频前端的系统要求,在2．45GHz的中心频率下增益可调,高增益时,噪声系数为2．9dB,输入P1dB压缩点为-19．8dBm,增益为20．5dB;中增益时,噪声系数为3．6dB,输入P1dB压缩点为-15．8dBm,增益为12．5dB;低增益时,噪声系数为6．0dB,输入P1dB压缩点为-16．4dB,增益为2．2dB。电路的输入输出匹配良好,在电源电压1．8V条件下,工作电流约为6mA。     

A monolithic 3.1-4.8 GHz MB-OFDM UWB transceiver in 0.18-μm CMOS

A monolithic RF transceiver for an MB-OFDM UWB system in 3.1-4.8 GHz is presented.The transceiver adopts direct-conversion architecture and integrates all building blocks including a gain controllable wideband LNA,a I/Q merged quadrature mixer,a fifth-order Gm-C bi-quad Chebyshev LPF/VGA,a fast-settling frequency synthesizer with a poly-phase filter,a linear broadband up-conversion quadrature modulator,an active D2S converter and a variablegain power amplifier.The ESD protected transceiver is fabricated in Jazz Semiconductor's 0.18-μm RF CMOS with an area of 6.1 mm2 and draws a total current of 221 mA from 1.8-V supply.The receiver achieves a maximum voltage gain of 68 dB with a control range of 42 dB in 6 dB/Step,noise figures of 5.5-8.8 dB for three sub-bands,and an inband/out-band IIP3 better than-4 dBm/+9 dBm.The transmitter achieves an output power ranging from-10.7 to-3dBm with gain control,an output P1dB better than-7.7 dBm,a sideband rejection about 32.4 dBc,and LO suppression of 31.1 dBc.The hopping time among sub-bands is less than 2.05 ns.     

A highly linear receiver front-end employing modified derivative superposition method with tuned inductors for 5.25 GHz

We design a highly linear CMOS RF receiver front-end operating in the 5 GHz band using the modified derivative superposition (DS) method with one- or two-tuned inductors in the low noise amplifier (LNA) and mixer. This method can be used to adjust the magnitude and phase of the third-order currents at output, and thus ensure that they cancel each other out. We characterize the two front-ends by the third-order input intercept point (IIP3), voltage conversion gain, and a noise figure based on the TSMC 0.18 μm RF CMOS process. Our simulation results suggest that the front-end with one-tuned inductor in the mixer supports linearization with the DS method, which only sacrifices 1.9 dB of IIP3 while the other performance parameters are improved. Furthermore, the front-end with two-tuned inductors requires a precise optimum design point, because it has to adjust two inductances simultaneously for optimization. If the inductances have deviated from the optimum design point, the front-end with two-tuned inductors has worse IIP3 characteristic than the front-end with one-tuned inductor. With two-tuned inductors, the front-end has an IIP3 of 5.3 dBm with a noise figure (NF) of 4.7 dB and a voltage conversion gain of 23.1 dB. The front-end with one-tuned inductor has an IIP3 of 3.4 dBm with an NF of 4.4 dB and a voltage conversion gain of 24.5 dB. There is a power consumption of 9.2 mA from a 1.5 V supply.